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1 | /* |
2 | * OMAP54xx CM1 instance offset macros | |
3 | * | |
4 | * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com | |
5 | * | |
6 | * Paul Walmsley (paul@pwsan.com) | |
7 | * Rajendra Nayak (rnayak@ti.com) | |
8 | * Benoit Cousson (b-cousson@ti.com) | |
9 | * | |
10 | * This file is automatically generated from the OMAP hardware databases. | |
11 | * We respectfully ask that any modifications to this file be coordinated | |
12 | * with the public linux-omap@vger.kernel.org mailing list and the | |
13 | * authors above to ensure that the autogeneration scripts are kept | |
14 | * up-to-date with the file contents. | |
15 | * | |
16 | * This program is free software; you can redistribute it and/or modify | |
17 | * it under the terms of the GNU General Public License version 2 as | |
18 | * published by the Free Software Foundation. | |
19 | * | |
20 | */ | |
21 | ||
22 | #ifndef __ARCH_ARM_MACH_OMAP2_CM1_54XX_H | |
23 | #define __ARCH_ARM_MACH_OMAP2_CM1_54XX_H | |
24 | ||
dfab439f BC |
25 | /* CM1 base address */ |
26 | #define OMAP54XX_CM_CORE_AON_BASE 0x4a004000 | |
27 | ||
28 | #define OMAP54XX_CM_CORE_AON_REGADDR(inst, reg) \ | |
29 | OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_AON_BASE + (inst) + (reg)) | |
30 | ||
31 | /* CM_CORE_AON instances */ | |
32 | #define OMAP54XX_CM_CORE_AON_OCP_SOCKET_INST 0x0000 | |
33 | #define OMAP54XX_CM_CORE_AON_CKGEN_INST 0x0100 | |
34 | #define OMAP54XX_CM_CORE_AON_MPU_INST 0x0300 | |
35 | #define OMAP54XX_CM_CORE_AON_DSP_INST 0x0400 | |
36 | #define OMAP54XX_CM_CORE_AON_ABE_INST 0x0500 | |
37 | #define OMAP54XX_CM_CORE_AON_RESTORE_INST 0x0e00 | |
38 | #define OMAP54XX_CM_CORE_AON_INSTR_INST 0x0f00 | |
39 | ||
40 | /* CM_CORE_AON clockdomain register offsets (from instance start) */ | |
41 | #define OMAP54XX_CM_CORE_AON_MPU_MPU_CDOFFS 0x0000 | |
42 | #define OMAP54XX_CM_CORE_AON_DSP_DSP_CDOFFS 0x0000 | |
43 | #define OMAP54XX_CM_CORE_AON_ABE_ABE_CDOFFS 0x0000 | |
44 | ||
45 | /* CM_CORE_AON */ | |
46 | ||
47 | /* CM_CORE_AON.OCP_SOCKET_CM_CORE_AON register offsets */ | |
48 | #define OMAP54XX_REVISION_CM_CORE_AON_OFFSET 0x0000 | |
49 | #define OMAP54XX_CM_CM_CORE_AON_PROFILING_CLKCTRL_OFFSET 0x0040 | |
50 | #define OMAP54XX_CM_CM_CORE_AON_PROFILING_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_OCP_SOCKET_INST, 0x0040) | |
51 | #define OMAP54XX_CM_CORE_AON_DEBUG_CFG_OFFSET 0x0080 | |
52 | #define OMAP54XX_CM_CORE_AON_DEBUG_OUT_OFFSET 0x0084 | |
53 | #define OMAP54XX_CM_CORE_AON_DEBUG_MPU_FD_TRANS_OFFSET 0x0090 | |
54 | #define OMAP54XX_CM_CORE_AON_DEBUG_DSP_FD_TRANS_OFFSET 0x0094 | |
55 | #define OMAP54XX_CM_CORE_AON_DEBUG_ABE_FD_TRANS_OFFSET 0x0098 | |
56 | #define OMAP54XX_CM_CORE_AON_DEBUG_ABE_FD_TRANS2_OFFSET 0x009c | |
57 | #define OMAP54XX_CM_CORE_AON_DEBUG_CM_CORE_AON_FD_TRANS_OFFSET 0x00a0 | |
58 | #define OMAP54XX_CM_CORE_AON_DEBUG_C2C_FD_TRANS_OFFSET 0x00a4 | |
59 | #define OMAP54XX_CM_CORE_AON_DEBUG_CAM_FD_TRANS_OFFSET 0x00a8 | |
60 | #define OMAP54XX_CM_CORE_AON_DEBUG_COREAON_FD_TRANS_OFFSET 0x00ac | |
61 | #define OMAP54XX_CM_CORE_AON_DEBUG_CUSTEFUSE_FD_TRANS_OFFSET 0x00b0 | |
62 | #define OMAP54XX_CM_CORE_AON_DEBUG_DMA_FD_TRANS_OFFSET 0x00b4 | |
63 | #define OMAP54XX_CM_CORE_AON_DEBUG_DSS_FD_TRANS_OFFSET 0x00b8 | |
64 | #define OMAP54XX_CM_CORE_AON_DEBUG_EMIF_FD_TRANS_OFFSET 0x00bc | |
65 | #define OMAP54XX_CM_CORE_AON_DEBUG_GPU_FD_TRANS_OFFSET 0x00c0 | |
66 | #define OMAP54XX_CM_CORE_AON_DEBUG_IPU_FD_TRANS_OFFSET 0x00c4 | |
67 | #define OMAP54XX_CM_CORE_AON_DEBUG_IVA_FD_TRANS_OFFSET 0x00c8 | |
68 | #define OMAP54XX_CM_CORE_AON_DEBUG_L3INIT_FD_TRANS_OFFSET 0x00cc | |
69 | #define OMAP54XX_CM_CORE_AON_DEBUG_L3INIT_FD_TRANS2_OFFSET 0x00d0 | |
70 | #define OMAP54XX_CM_CORE_AON_DEBUG_L3INSTR_FD_TRANS_OFFSET 0x00d4 | |
71 | #define OMAP54XX_CM_CORE_AON_DEBUG_L3MAIN1_FD_TRANS_OFFSET 0x00d8 | |
72 | #define OMAP54XX_CM_CORE_AON_DEBUG_L3MAIN2_FD_TRANS_OFFSET 0x00dc | |
73 | #define OMAP54XX_CM_CORE_AON_DEBUG_L4CFG_FD_TRANS_OFFSET 0x00e0 | |
74 | #define OMAP54XX_CM_CORE_AON_DEBUG_L4PER_FD_TRANS_OFFSET 0x00e4 | |
75 | #define OMAP54XX_CM_CORE_AON_DEBUG_L4PER_FD_TRANS2_OFFSET 0x00e8 | |
76 | #define OMAP54XX_CM_CORE_AON_DEBUG_L4SEC_FD_TRANS_OFFSET 0x00ec | |
77 | #define OMAP54XX_CM_CORE_AON_DEBUG_MIPIEXT_FD_TRANS_OFFSET 0x00f0 | |
78 | ||
79 | /* CM_CORE_AON.CKGEN_CM_CORE_AON register offsets */ | |
80 | #define OMAP54XX_CM_CLKSEL_CORE_OFFSET 0x0000 | |
81 | #define OMAP54XX_CM_CLKSEL_CORE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0000) | |
82 | #define OMAP54XX_CM_CLKSEL_ABE_OFFSET 0x0008 | |
83 | #define OMAP54XX_CM_CLKSEL_ABE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0008) | |
84 | #define OMAP54XX_CM_DLL_CTRL_OFFSET 0x0010 | |
85 | #define OMAP54XX_CM_CLKMODE_DPLL_CORE_OFFSET 0x0020 | |
86 | #define OMAP54XX_CM_CLKMODE_DPLL_CORE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0020) | |
87 | #define OMAP54XX_CM_IDLEST_DPLL_CORE_OFFSET 0x0024 | |
88 | #define OMAP54XX_CM_IDLEST_DPLL_CORE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0024) | |
89 | #define OMAP54XX_CM_AUTOIDLE_DPLL_CORE_OFFSET 0x0028 | |
90 | #define OMAP54XX_CM_AUTOIDLE_DPLL_CORE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0028) | |
91 | #define OMAP54XX_CM_CLKSEL_DPLL_CORE_OFFSET 0x002c | |
92 | #define OMAP54XX_CM_CLKSEL_DPLL_CORE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x002c) | |
93 | #define OMAP54XX_CM_DIV_M2_DPLL_CORE_OFFSET 0x0030 | |
94 | #define OMAP54XX_CM_DIV_M2_DPLL_CORE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0030) | |
95 | #define OMAP54XX_CM_DIV_M3_DPLL_CORE_OFFSET 0x0034 | |
96 | #define OMAP54XX_CM_DIV_M3_DPLL_CORE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0034) | |
97 | #define OMAP54XX_CM_DIV_H11_DPLL_CORE_OFFSET 0x0038 | |
98 | #define OMAP54XX_CM_DIV_H11_DPLL_CORE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0038) | |
99 | #define OMAP54XX_CM_DIV_H12_DPLL_CORE_OFFSET 0x003c | |
100 | #define OMAP54XX_CM_DIV_H12_DPLL_CORE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x003c) | |
101 | #define OMAP54XX_CM_DIV_H13_DPLL_CORE_OFFSET 0x0040 | |
102 | #define OMAP54XX_CM_DIV_H13_DPLL_CORE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0040) | |
103 | #define OMAP54XX_CM_DIV_H14_DPLL_CORE_OFFSET 0x0044 | |
104 | #define OMAP54XX_CM_DIV_H14_DPLL_CORE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0044) | |
105 | #define OMAP54XX_CM_SSC_DELTAMSTEP_DPLL_CORE_OFFSET 0x0048 | |
106 | #define OMAP54XX_CM_SSC_MODFREQDIV_DPLL_CORE_OFFSET 0x004c | |
107 | #define OMAP54XX_CM_DIV_H21_DPLL_CORE_OFFSET 0x0050 | |
108 | #define OMAP54XX_CM_DIV_H21_DPLL_CORE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0050) | |
109 | #define OMAP54XX_CM_DIV_H22_DPLL_CORE_OFFSET 0x0054 | |
110 | #define OMAP54XX_CM_DIV_H22_DPLL_CORE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0054) | |
111 | #define OMAP54XX_CM_DIV_H23_DPLL_CORE_OFFSET 0x0058 | |
112 | #define OMAP54XX_CM_DIV_H23_DPLL_CORE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0058) | |
113 | #define OMAP54XX_CM_DIV_H24_DPLL_CORE_OFFSET 0x005c | |
114 | #define OMAP54XX_CM_DIV_H24_DPLL_CORE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x005c) | |
115 | #define OMAP54XX_CM_CLKMODE_DPLL_MPU_OFFSET 0x0060 | |
116 | #define OMAP54XX_CM_CLKMODE_DPLL_MPU OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0060) | |
117 | #define OMAP54XX_CM_IDLEST_DPLL_MPU_OFFSET 0x0064 | |
118 | #define OMAP54XX_CM_IDLEST_DPLL_MPU OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0064) | |
119 | #define OMAP54XX_CM_AUTOIDLE_DPLL_MPU_OFFSET 0x0068 | |
120 | #define OMAP54XX_CM_AUTOIDLE_DPLL_MPU OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0068) | |
121 | #define OMAP54XX_CM_CLKSEL_DPLL_MPU_OFFSET 0x006c | |
122 | #define OMAP54XX_CM_CLKSEL_DPLL_MPU OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x006c) | |
123 | #define OMAP54XX_CM_DIV_M2_DPLL_MPU_OFFSET 0x0070 | |
124 | #define OMAP54XX_CM_DIV_M2_DPLL_MPU OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0070) | |
125 | #define OMAP54XX_CM_SSC_DELTAMSTEP_DPLL_MPU_OFFSET 0x0088 | |
126 | #define OMAP54XX_CM_SSC_MODFREQDIV_DPLL_MPU_OFFSET 0x008c | |
127 | #define OMAP54XX_CM_BYPCLK_DPLL_MPU_OFFSET 0x009c | |
128 | #define OMAP54XX_CM_BYPCLK_DPLL_MPU OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x009c) | |
129 | #define OMAP54XX_CM_CLKMODE_DPLL_IVA_OFFSET 0x00a0 | |
130 | #define OMAP54XX_CM_CLKMODE_DPLL_IVA OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00a0) | |
131 | #define OMAP54XX_CM_IDLEST_DPLL_IVA_OFFSET 0x00a4 | |
132 | #define OMAP54XX_CM_IDLEST_DPLL_IVA OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00a4) | |
133 | #define OMAP54XX_CM_AUTOIDLE_DPLL_IVA_OFFSET 0x00a8 | |
134 | #define OMAP54XX_CM_AUTOIDLE_DPLL_IVA OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00a8) | |
135 | #define OMAP54XX_CM_CLKSEL_DPLL_IVA_OFFSET 0x00ac | |
136 | #define OMAP54XX_CM_CLKSEL_DPLL_IVA OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00ac) | |
137 | #define OMAP54XX_CM_DIV_H11_DPLL_IVA_OFFSET 0x00b8 | |
138 | #define OMAP54XX_CM_DIV_H11_DPLL_IVA OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00b8) | |
139 | #define OMAP54XX_CM_DIV_H12_DPLL_IVA_OFFSET 0x00bc | |
140 | #define OMAP54XX_CM_DIV_H12_DPLL_IVA OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00bc) | |
141 | #define OMAP54XX_CM_SSC_DELTAMSTEP_DPLL_IVA_OFFSET 0x00c8 | |
142 | #define OMAP54XX_CM_SSC_MODFREQDIV_DPLL_IVA_OFFSET 0x00cc | |
143 | #define OMAP54XX_CM_BYPCLK_DPLL_IVA_OFFSET 0x00dc | |
144 | #define OMAP54XX_CM_BYPCLK_DPLL_IVA OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00dc) | |
145 | #define OMAP54XX_CM_CLKMODE_DPLL_ABE_OFFSET 0x00e0 | |
146 | #define OMAP54XX_CM_CLKMODE_DPLL_ABE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00e0) | |
147 | #define OMAP54XX_CM_IDLEST_DPLL_ABE_OFFSET 0x00e4 | |
148 | #define OMAP54XX_CM_IDLEST_DPLL_ABE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00e4) | |
149 | #define OMAP54XX_CM_AUTOIDLE_DPLL_ABE_OFFSET 0x00e8 | |
150 | #define OMAP54XX_CM_AUTOIDLE_DPLL_ABE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00e8) | |
151 | #define OMAP54XX_CM_CLKSEL_DPLL_ABE_OFFSET 0x00ec | |
152 | #define OMAP54XX_CM_CLKSEL_DPLL_ABE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00ec) | |
153 | #define OMAP54XX_CM_DIV_M2_DPLL_ABE_OFFSET 0x00f0 | |
154 | #define OMAP54XX_CM_DIV_M2_DPLL_ABE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00f0) | |
155 | #define OMAP54XX_CM_DIV_M3_DPLL_ABE_OFFSET 0x00f4 | |
156 | #define OMAP54XX_CM_DIV_M3_DPLL_ABE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00f4) | |
157 | #define OMAP54XX_CM_SSC_DELTAMSTEP_DPLL_ABE_OFFSET 0x0108 | |
158 | #define OMAP54XX_CM_SSC_MODFREQDIV_DPLL_ABE_OFFSET 0x010c | |
159 | #define OMAP54XX_CM_SHADOW_FREQ_CONFIG1_OFFSET 0x0160 | |
160 | #define OMAP54XX_CM_SHADOW_FREQ_CONFIG2_OFFSET 0x0164 | |
161 | #define OMAP54XX_CM_DYN_DEP_PRESCAL_OFFSET 0x0170 | |
162 | #define OMAP54XX_CM_RESTORE_ST_OFFSET 0x0180 | |
163 | ||
164 | /* CM_CORE_AON.MPU_CM_CORE_AON register offsets */ | |
165 | #define OMAP54XX_CM_MPU_CLKSTCTRL_OFFSET 0x0000 | |
166 | #define OMAP54XX_CM_MPU_STATICDEP_OFFSET 0x0004 | |
167 | #define OMAP54XX_CM_MPU_DYNAMICDEP_OFFSET 0x0008 | |
168 | #define OMAP54XX_CM_MPU_MPU_CLKCTRL_OFFSET 0x0020 | |
169 | #define OMAP54XX_CM_MPU_MPU_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_MPU_INST, 0x0020) | |
170 | #define OMAP54XX_CM_MPU_MPU_MPU_DBG_CLKCTRL_OFFSET 0x0028 | |
171 | #define OMAP54XX_CM_MPU_MPU_MPU_DBG_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_MPU_INST, 0x0028) | |
172 | ||
173 | /* CM_CORE_AON.DSP_CM_CORE_AON register offsets */ | |
174 | #define OMAP54XX_CM_DSP_CLKSTCTRL_OFFSET 0x0000 | |
175 | #define OMAP54XX_CM_DSP_STATICDEP_OFFSET 0x0004 | |
176 | #define OMAP54XX_CM_DSP_DYNAMICDEP_OFFSET 0x0008 | |
177 | #define OMAP54XX_CM_DSP_DSP_CLKCTRL_OFFSET 0x0020 | |
178 | #define OMAP54XX_CM_DSP_DSP_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_DSP_INST, 0x0020) | |
179 | ||
180 | /* CM_CORE_AON.ABE_CM_CORE_AON register offsets */ | |
181 | #define OMAP54XX_CM_ABE_CLKSTCTRL_OFFSET 0x0000 | |
182 | #define OMAP54XX_CM_ABE_L4_ABE_CLKCTRL_OFFSET 0x0020 | |
183 | #define OMAP54XX_CM_ABE_L4_ABE_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0020) | |
184 | #define OMAP54XX_CM_ABE_AESS_CLKCTRL_OFFSET 0x0028 | |
185 | #define OMAP54XX_CM_ABE_AESS_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0028) | |
186 | #define OMAP54XX_CM_ABE_MCPDM_CLKCTRL_OFFSET 0x0030 | |
187 | #define OMAP54XX_CM_ABE_MCPDM_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0030) | |
188 | #define OMAP54XX_CM_ABE_DMIC_CLKCTRL_OFFSET 0x0038 | |
189 | #define OMAP54XX_CM_ABE_DMIC_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0038) | |
190 | #define OMAP54XX_CM_ABE_MCASP_CLKCTRL_OFFSET 0x0040 | |
191 | #define OMAP54XX_CM_ABE_MCASP_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0040) | |
192 | #define OMAP54XX_CM_ABE_MCBSP1_CLKCTRL_OFFSET 0x0048 | |
193 | #define OMAP54XX_CM_ABE_MCBSP1_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0048) | |
194 | #define OMAP54XX_CM_ABE_MCBSP2_CLKCTRL_OFFSET 0x0050 | |
195 | #define OMAP54XX_CM_ABE_MCBSP2_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0050) | |
196 | #define OMAP54XX_CM_ABE_MCBSP3_CLKCTRL_OFFSET 0x0058 | |
197 | #define OMAP54XX_CM_ABE_MCBSP3_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0058) | |
198 | #define OMAP54XX_CM_ABE_SLIMBUS1_CLKCTRL_OFFSET 0x0060 | |
199 | #define OMAP54XX_CM_ABE_SLIMBUS1_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0060) | |
200 | #define OMAP54XX_CM_ABE_TIMER5_CLKCTRL_OFFSET 0x0068 | |
201 | #define OMAP54XX_CM_ABE_TIMER5_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0068) | |
202 | #define OMAP54XX_CM_ABE_TIMER6_CLKCTRL_OFFSET 0x0070 | |
203 | #define OMAP54XX_CM_ABE_TIMER6_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0070) | |
204 | #define OMAP54XX_CM_ABE_TIMER7_CLKCTRL_OFFSET 0x0078 | |
205 | #define OMAP54XX_CM_ABE_TIMER7_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0078) | |
206 | #define OMAP54XX_CM_ABE_TIMER8_CLKCTRL_OFFSET 0x0080 | |
207 | #define OMAP54XX_CM_ABE_TIMER8_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0080) | |
208 | #define OMAP54XX_CM_ABE_WD_TIMER3_CLKCTRL_OFFSET 0x0088 | |
209 | #define OMAP54XX_CM_ABE_WD_TIMER3_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0088) | |
210 | ||
211 | #endif |