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1 | /* |
2 | * DRA7xx CM1 instance offset macros | |
3 | * | |
4 | * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com | |
5 | * | |
6 | * Generated by code originally written by: | |
7 | * Paul Walmsley (paul@pwsan.com) | |
8 | * Rajendra Nayak (rnayak@ti.com) | |
9 | * Benoit Cousson (b-cousson@ti.com) | |
10 | * | |
11 | * This file is automatically generated from the OMAP hardware databases. | |
12 | * We respectfully ask that any modifications to this file be coordinated | |
13 | * with the public linux-omap@vger.kernel.org mailing list and the | |
14 | * authors above to ensure that the autogeneration scripts are kept | |
15 | * up-to-date with the file contents. | |
16 | * | |
17 | * This program is free software; you can redistribute it and/or modify | |
18 | * it under the terms of the GNU General Public License version 2 as | |
19 | * published by the Free Software Foundation. | |
20 | * | |
21 | */ | |
22 | ||
23 | #ifndef __ARCH_ARM_MACH_OMAP2_CM1_7XX_H | |
24 | #define __ARCH_ARM_MACH_OMAP2_CM1_7XX_H | |
25 | ||
26 | #include "cm_44xx_54xx.h" | |
27 | ||
28 | /* CM1 base address */ | |
29 | #define DRA7XX_CM_CORE_AON_BASE 0x4a005000 | |
30 | ||
31 | #define DRA7XX_CM_CORE_AON_REGADDR(inst, reg) \ | |
32 | OMAP2_L4_IO_ADDRESS(DRA7XX_CM_CORE_AON_BASE + (inst) + (reg)) | |
33 | ||
34 | /* CM_CORE_AON instances */ | |
35 | #define DRA7XX_CM_CORE_AON_OCP_SOCKET_INST 0x0000 | |
36 | #define DRA7XX_CM_CORE_AON_CKGEN_INST 0x0100 | |
37 | #define DRA7XX_CM_CORE_AON_MPU_INST 0x0300 | |
38 | #define DRA7XX_CM_CORE_AON_DSP1_INST 0x0400 | |
39 | #define DRA7XX_CM_CORE_AON_IPU_INST 0x0500 | |
40 | #define DRA7XX_CM_CORE_AON_DSP2_INST 0x0600 | |
41 | #define DRA7XX_CM_CORE_AON_EVE1_INST 0x0640 | |
42 | #define DRA7XX_CM_CORE_AON_EVE2_INST 0x0680 | |
43 | #define DRA7XX_CM_CORE_AON_EVE3_INST 0x06c0 | |
44 | #define DRA7XX_CM_CORE_AON_EVE4_INST 0x0700 | |
45 | #define DRA7XX_CM_CORE_AON_RTC_INST 0x0740 | |
46 | #define DRA7XX_CM_CORE_AON_VPE_INST 0x0760 | |
47 | #define DRA7XX_CM_CORE_AON_RESTORE_INST 0x0e00 | |
48 | #define DRA7XX_CM_CORE_AON_INSTR_INST 0x0f00 | |
49 | ||
50 | /* CM_CORE_AON clockdomain register offsets (from instance start) */ | |
51 | #define DRA7XX_CM_CORE_AON_MPU_MPU_CDOFFS 0x0000 | |
52 | #define DRA7XX_CM_CORE_AON_DSP1_DSP1_CDOFFS 0x0000 | |
53 | #define DRA7XX_CM_CORE_AON_IPU_IPU1_CDOFFS 0x0000 | |
54 | #define DRA7XX_CM_CORE_AON_IPU_IPU_CDOFFS 0x0040 | |
55 | #define DRA7XX_CM_CORE_AON_DSP2_DSP2_CDOFFS 0x0000 | |
56 | #define DRA7XX_CM_CORE_AON_EVE1_EVE1_CDOFFS 0x0000 | |
57 | #define DRA7XX_CM_CORE_AON_EVE2_EVE2_CDOFFS 0x0000 | |
58 | #define DRA7XX_CM_CORE_AON_EVE3_EVE3_CDOFFS 0x0000 | |
59 | #define DRA7XX_CM_CORE_AON_EVE4_EVE4_CDOFFS 0x0000 | |
60 | #define DRA7XX_CM_CORE_AON_RTC_RTC_CDOFFS 0x0000 | |
61 | #define DRA7XX_CM_CORE_AON_VPE_VPE_CDOFFS 0x0000 | |
62 | ||
63 | /* CM_CORE_AON */ | |
64 | ||
65 | /* CM_CORE_AON.OCP_SOCKET_CM_CORE_AON register offsets */ | |
66 | #define DRA7XX_REVISION_CM_CORE_AON_OFFSET 0x0000 | |
67 | #define DRA7XX_CM_CM_CORE_AON_PROFILING_CLKCTRL_OFFSET 0x0040 | |
68 | #define DRA7XX_CM_CM_CORE_AON_PROFILING_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_OCP_SOCKET_INST, 0x0040) | |
69 | #define DRA7XX_CM_CORE_AON_DEBUG_OUT_OFFSET 0x00ec | |
70 | #define DRA7XX_CM_CORE_AON_DEBUG_CFG0_OFFSET 0x00f0 | |
71 | #define DRA7XX_CM_CORE_AON_DEBUG_CFG1_OFFSET 0x00f4 | |
72 | #define DRA7XX_CM_CORE_AON_DEBUG_CFG2_OFFSET 0x00f8 | |
73 | #define DRA7XX_CM_CORE_AON_DEBUG_CFG3_OFFSET 0x00fc | |
74 | ||
75 | /* CM_CORE_AON.CKGEN_CM_CORE_AON register offsets */ | |
76 | #define DRA7XX_CM_CLKSEL_CORE_OFFSET 0x0000 | |
77 | #define DRA7XX_CM_CLKSEL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0000) | |
78 | #define DRA7XX_CM_CLKSEL_ABE_OFFSET 0x0008 | |
79 | #define DRA7XX_CM_CLKSEL_ABE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0008) | |
80 | #define DRA7XX_CM_DLL_CTRL_OFFSET 0x0010 | |
81 | #define DRA7XX_CM_CLKMODE_DPLL_CORE_OFFSET 0x0020 | |
82 | #define DRA7XX_CM_CLKMODE_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0020) | |
83 | #define DRA7XX_CM_IDLEST_DPLL_CORE_OFFSET 0x0024 | |
84 | #define DRA7XX_CM_IDLEST_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0024) | |
85 | #define DRA7XX_CM_AUTOIDLE_DPLL_CORE_OFFSET 0x0028 | |
86 | #define DRA7XX_CM_AUTOIDLE_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0028) | |
87 | #define DRA7XX_CM_CLKSEL_DPLL_CORE_OFFSET 0x002c | |
88 | #define DRA7XX_CM_CLKSEL_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x002c) | |
89 | #define DRA7XX_CM_DIV_M2_DPLL_CORE_OFFSET 0x0030 | |
90 | #define DRA7XX_CM_DIV_M2_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0030) | |
91 | #define DRA7XX_CM_DIV_M3_DPLL_CORE_OFFSET 0x0034 | |
92 | #define DRA7XX_CM_DIV_M3_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0034) | |
93 | #define DRA7XX_CM_DIV_H11_DPLL_CORE_OFFSET 0x0038 | |
94 | #define DRA7XX_CM_DIV_H11_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0038) | |
95 | #define DRA7XX_CM_DIV_H12_DPLL_CORE_OFFSET 0x003c | |
96 | #define DRA7XX_CM_DIV_H12_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x003c) | |
97 | #define DRA7XX_CM_DIV_H13_DPLL_CORE_OFFSET 0x0040 | |
98 | #define DRA7XX_CM_DIV_H13_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0040) | |
99 | #define DRA7XX_CM_DIV_H14_DPLL_CORE_OFFSET 0x0044 | |
100 | #define DRA7XX_CM_DIV_H14_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0044) | |
101 | #define DRA7XX_CM_SSC_DELTAMSTEP_DPLL_CORE_OFFSET 0x0048 | |
102 | #define DRA7XX_CM_SSC_MODFREQDIV_DPLL_CORE_OFFSET 0x004c | |
103 | #define DRA7XX_CM_DIV_H21_DPLL_CORE_OFFSET 0x0050 | |
104 | #define DRA7XX_CM_DIV_H21_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0050) | |
105 | #define DRA7XX_CM_DIV_H22_DPLL_CORE_OFFSET 0x0054 | |
106 | #define DRA7XX_CM_DIV_H22_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0054) | |
107 | #define DRA7XX_CM_DIV_H23_DPLL_CORE_OFFSET 0x0058 | |
108 | #define DRA7XX_CM_DIV_H23_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0058) | |
109 | #define DRA7XX_CM_DIV_H24_DPLL_CORE_OFFSET 0x005c | |
110 | #define DRA7XX_CM_DIV_H24_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x005c) | |
111 | #define DRA7XX_CM_CLKMODE_DPLL_MPU_OFFSET 0x0060 | |
112 | #define DRA7XX_CM_CLKMODE_DPLL_MPU DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0060) | |
113 | #define DRA7XX_CM_IDLEST_DPLL_MPU_OFFSET 0x0064 | |
114 | #define DRA7XX_CM_IDLEST_DPLL_MPU DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0064) | |
115 | #define DRA7XX_CM_AUTOIDLE_DPLL_MPU_OFFSET 0x0068 | |
116 | #define DRA7XX_CM_AUTOIDLE_DPLL_MPU DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0068) | |
117 | #define DRA7XX_CM_CLKSEL_DPLL_MPU_OFFSET 0x006c | |
118 | #define DRA7XX_CM_CLKSEL_DPLL_MPU DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x006c) | |
119 | #define DRA7XX_CM_DIV_M2_DPLL_MPU_OFFSET 0x0070 | |
120 | #define DRA7XX_CM_DIV_M2_DPLL_MPU DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0070) | |
121 | #define DRA7XX_CM_SSC_DELTAMSTEP_DPLL_MPU_OFFSET 0x0088 | |
122 | #define DRA7XX_CM_SSC_MODFREQDIV_DPLL_MPU_OFFSET 0x008c | |
123 | #define DRA7XX_CM_BYPCLK_DPLL_MPU_OFFSET 0x009c | |
124 | #define DRA7XX_CM_BYPCLK_DPLL_MPU DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x009c) | |
125 | #define DRA7XX_CM_CLKMODE_DPLL_IVA_OFFSET 0x00a0 | |
126 | #define DRA7XX_CM_CLKMODE_DPLL_IVA DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00a0) | |
127 | #define DRA7XX_CM_IDLEST_DPLL_IVA_OFFSET 0x00a4 | |
128 | #define DRA7XX_CM_IDLEST_DPLL_IVA DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00a4) | |
129 | #define DRA7XX_CM_AUTOIDLE_DPLL_IVA_OFFSET 0x00a8 | |
130 | #define DRA7XX_CM_AUTOIDLE_DPLL_IVA DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00a8) | |
131 | #define DRA7XX_CM_CLKSEL_DPLL_IVA_OFFSET 0x00ac | |
132 | #define DRA7XX_CM_CLKSEL_DPLL_IVA DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00ac) | |
133 | #define DRA7XX_CM_DIV_M2_DPLL_IVA_OFFSET 0x00b0 | |
134 | #define DRA7XX_CM_DIV_M2_DPLL_IVA DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00b0) | |
135 | #define DRA7XX_CM_DIV_M3_DPLL_IVA_OFFSET 0x00b4 | |
136 | #define DRA7XX_CM_DIV_M3_DPLL_IVA DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00b4) | |
137 | #define DRA7XX_CM_SSC_DELTAMSTEP_DPLL_IVA_OFFSET 0x00c8 | |
138 | #define DRA7XX_CM_SSC_MODFREQDIV_DPLL_IVA_OFFSET 0x00cc | |
139 | #define DRA7XX_CM_BYPCLK_DPLL_IVA_OFFSET 0x00dc | |
140 | #define DRA7XX_CM_BYPCLK_DPLL_IVA DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00dc) | |
141 | #define DRA7XX_CM_CLKMODE_DPLL_ABE_OFFSET 0x00e0 | |
142 | #define DRA7XX_CM_CLKMODE_DPLL_ABE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00e0) | |
143 | #define DRA7XX_CM_IDLEST_DPLL_ABE_OFFSET 0x00e4 | |
144 | #define DRA7XX_CM_IDLEST_DPLL_ABE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00e4) | |
145 | #define DRA7XX_CM_AUTOIDLE_DPLL_ABE_OFFSET 0x00e8 | |
146 | #define DRA7XX_CM_AUTOIDLE_DPLL_ABE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00e8) | |
147 | #define DRA7XX_CM_CLKSEL_DPLL_ABE_OFFSET 0x00ec | |
148 | #define DRA7XX_CM_CLKSEL_DPLL_ABE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00ec) | |
149 | #define DRA7XX_CM_DIV_M2_DPLL_ABE_OFFSET 0x00f0 | |
150 | #define DRA7XX_CM_DIV_M2_DPLL_ABE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00f0) | |
151 | #define DRA7XX_CM_DIV_M3_DPLL_ABE_OFFSET 0x00f4 | |
152 | #define DRA7XX_CM_DIV_M3_DPLL_ABE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00f4) | |
153 | #define DRA7XX_CM_SSC_DELTAMSTEP_DPLL_ABE_OFFSET 0x0108 | |
154 | #define DRA7XX_CM_SSC_MODFREQDIV_DPLL_ABE_OFFSET 0x010c | |
155 | #define DRA7XX_CM_CLKMODE_DPLL_DDR_OFFSET 0x0110 | |
156 | #define DRA7XX_CM_CLKMODE_DPLL_DDR DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0110) | |
157 | #define DRA7XX_CM_IDLEST_DPLL_DDR_OFFSET 0x0114 | |
158 | #define DRA7XX_CM_IDLEST_DPLL_DDR DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0114) | |
159 | #define DRA7XX_CM_AUTOIDLE_DPLL_DDR_OFFSET 0x0118 | |
160 | #define DRA7XX_CM_AUTOIDLE_DPLL_DDR DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0118) | |
161 | #define DRA7XX_CM_CLKSEL_DPLL_DDR_OFFSET 0x011c | |
162 | #define DRA7XX_CM_CLKSEL_DPLL_DDR DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x011c) | |
163 | #define DRA7XX_CM_DIV_M2_DPLL_DDR_OFFSET 0x0120 | |
164 | #define DRA7XX_CM_DIV_M2_DPLL_DDR DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0120) | |
165 | #define DRA7XX_CM_DIV_M3_DPLL_DDR_OFFSET 0x0124 | |
166 | #define DRA7XX_CM_DIV_M3_DPLL_DDR DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0124) | |
167 | #define DRA7XX_CM_DIV_H11_DPLL_DDR_OFFSET 0x0128 | |
168 | #define DRA7XX_CM_DIV_H11_DPLL_DDR DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0128) | |
169 | #define DRA7XX_CM_SSC_DELTAMSTEP_DPLL_DDR_OFFSET 0x012c | |
170 | #define DRA7XX_CM_SSC_MODFREQDIV_DPLL_DDR_OFFSET 0x0130 | |
171 | #define DRA7XX_CM_CLKMODE_DPLL_DSP_OFFSET 0x0134 | |
172 | #define DRA7XX_CM_CLKMODE_DPLL_DSP DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0134) | |
173 | #define DRA7XX_CM_IDLEST_DPLL_DSP_OFFSET 0x0138 | |
174 | #define DRA7XX_CM_IDLEST_DPLL_DSP DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0138) | |
175 | #define DRA7XX_CM_AUTOIDLE_DPLL_DSP_OFFSET 0x013c | |
176 | #define DRA7XX_CM_AUTOIDLE_DPLL_DSP DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x013c) | |
177 | #define DRA7XX_CM_CLKSEL_DPLL_DSP_OFFSET 0x0140 | |
178 | #define DRA7XX_CM_CLKSEL_DPLL_DSP DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0140) | |
179 | #define DRA7XX_CM_DIV_M2_DPLL_DSP_OFFSET 0x0144 | |
180 | #define DRA7XX_CM_DIV_M2_DPLL_DSP DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0144) | |
181 | #define DRA7XX_CM_DIV_M3_DPLL_DSP_OFFSET 0x0148 | |
182 | #define DRA7XX_CM_DIV_M3_DPLL_DSP DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0148) | |
183 | #define DRA7XX_CM_SSC_DELTAMSTEP_DPLL_DSP_OFFSET 0x014c | |
184 | #define DRA7XX_CM_SSC_MODFREQDIV_DPLL_DSP_OFFSET 0x0150 | |
185 | #define DRA7XX_CM_BYPCLK_DPLL_DSP_OFFSET 0x0154 | |
186 | #define DRA7XX_CM_BYPCLK_DPLL_DSP DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0154) | |
187 | #define DRA7XX_CM_SHADOW_FREQ_CONFIG1_OFFSET 0x0160 | |
188 | #define DRA7XX_CM_SHADOW_FREQ_CONFIG2_OFFSET 0x0164 | |
189 | #define DRA7XX_CM_DYN_DEP_PRESCAL_OFFSET 0x0170 | |
190 | #define DRA7XX_CM_RESTORE_ST_OFFSET 0x0180 | |
191 | #define DRA7XX_CM_CLKMODE_DPLL_EVE_OFFSET 0x0184 | |
192 | #define DRA7XX_CM_CLKMODE_DPLL_EVE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0184) | |
193 | #define DRA7XX_CM_IDLEST_DPLL_EVE_OFFSET 0x0188 | |
194 | #define DRA7XX_CM_IDLEST_DPLL_EVE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0188) | |
195 | #define DRA7XX_CM_AUTOIDLE_DPLL_EVE_OFFSET 0x018c | |
196 | #define DRA7XX_CM_AUTOIDLE_DPLL_EVE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x018c) | |
197 | #define DRA7XX_CM_CLKSEL_DPLL_EVE_OFFSET 0x0190 | |
198 | #define DRA7XX_CM_CLKSEL_DPLL_EVE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0190) | |
199 | #define DRA7XX_CM_DIV_M2_DPLL_EVE_OFFSET 0x0194 | |
200 | #define DRA7XX_CM_DIV_M2_DPLL_EVE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0194) | |
201 | #define DRA7XX_CM_DIV_M3_DPLL_EVE_OFFSET 0x0198 | |
202 | #define DRA7XX_CM_DIV_M3_DPLL_EVE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0198) | |
203 | #define DRA7XX_CM_SSC_DELTAMSTEP_DPLL_EVE_OFFSET 0x019c | |
204 | #define DRA7XX_CM_SSC_MODFREQDIV_DPLL_EVE_OFFSET 0x01a0 | |
205 | #define DRA7XX_CM_BYPCLK_DPLL_EVE_OFFSET 0x01a4 | |
206 | #define DRA7XX_CM_BYPCLK_DPLL_EVE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01a4) | |
207 | #define DRA7XX_CM_CLKMODE_DPLL_GMAC_OFFSET 0x01a8 | |
208 | #define DRA7XX_CM_CLKMODE_DPLL_GMAC DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01a8) | |
209 | #define DRA7XX_CM_IDLEST_DPLL_GMAC_OFFSET 0x01ac | |
210 | #define DRA7XX_CM_IDLEST_DPLL_GMAC DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01ac) | |
211 | #define DRA7XX_CM_AUTOIDLE_DPLL_GMAC_OFFSET 0x01b0 | |
212 | #define DRA7XX_CM_AUTOIDLE_DPLL_GMAC DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01b0) | |
213 | #define DRA7XX_CM_CLKSEL_DPLL_GMAC_OFFSET 0x01b4 | |
214 | #define DRA7XX_CM_CLKSEL_DPLL_GMAC DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01b4) | |
215 | #define DRA7XX_CM_DIV_M2_DPLL_GMAC_OFFSET 0x01b8 | |
216 | #define DRA7XX_CM_DIV_M2_DPLL_GMAC DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01b8) | |
217 | #define DRA7XX_CM_DIV_M3_DPLL_GMAC_OFFSET 0x01bc | |
218 | #define DRA7XX_CM_DIV_M3_DPLL_GMAC DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01bc) | |
219 | #define DRA7XX_CM_DIV_H11_DPLL_GMAC_OFFSET 0x01c0 | |
220 | #define DRA7XX_CM_DIV_H11_DPLL_GMAC DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01c0) | |
221 | #define DRA7XX_CM_DIV_H12_DPLL_GMAC_OFFSET 0x01c4 | |
222 | #define DRA7XX_CM_DIV_H12_DPLL_GMAC DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01c4) | |
223 | #define DRA7XX_CM_DIV_H13_DPLL_GMAC_OFFSET 0x01c8 | |
224 | #define DRA7XX_CM_DIV_H13_DPLL_GMAC DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01c8) | |
225 | #define DRA7XX_CM_DIV_H14_DPLL_GMAC_OFFSET 0x01cc | |
226 | #define DRA7XX_CM_DIV_H14_DPLL_GMAC DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01cc) | |
227 | #define DRA7XX_CM_SSC_DELTAMSTEP_DPLL_GMAC_OFFSET 0x01d0 | |
228 | #define DRA7XX_CM_SSC_MODFREQDIV_DPLL_GMAC_OFFSET 0x01d4 | |
229 | #define DRA7XX_CM_CLKMODE_DPLL_GPU_OFFSET 0x01d8 | |
230 | #define DRA7XX_CM_CLKMODE_DPLL_GPU DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01d8) | |
231 | #define DRA7XX_CM_IDLEST_DPLL_GPU_OFFSET 0x01dc | |
232 | #define DRA7XX_CM_IDLEST_DPLL_GPU DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01dc) | |
233 | #define DRA7XX_CM_AUTOIDLE_DPLL_GPU_OFFSET 0x01e0 | |
234 | #define DRA7XX_CM_AUTOIDLE_DPLL_GPU DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01e0) | |
235 | #define DRA7XX_CM_CLKSEL_DPLL_GPU_OFFSET 0x01e4 | |
236 | #define DRA7XX_CM_CLKSEL_DPLL_GPU DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01e4) | |
237 | #define DRA7XX_CM_DIV_M2_DPLL_GPU_OFFSET 0x01e8 | |
238 | #define DRA7XX_CM_DIV_M2_DPLL_GPU DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01e8) | |
239 | #define DRA7XX_CM_DIV_M3_DPLL_GPU_OFFSET 0x01ec | |
240 | #define DRA7XX_CM_DIV_M3_DPLL_GPU DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01ec) | |
241 | #define DRA7XX_CM_SSC_DELTAMSTEP_DPLL_GPU_OFFSET 0x01f0 | |
242 | #define DRA7XX_CM_SSC_MODFREQDIV_DPLL_GPU_OFFSET 0x01f4 | |
243 | ||
244 | /* CM_CORE_AON.MPU_CM_CORE_AON register offsets */ | |
245 | #define DRA7XX_CM_MPU_CLKSTCTRL_OFFSET 0x0000 | |
246 | #define DRA7XX_CM_MPU_STATICDEP_OFFSET 0x0004 | |
247 | #define DRA7XX_CM_MPU_DYNAMICDEP_OFFSET 0x0008 | |
248 | #define DRA7XX_CM_MPU_MPU_CLKCTRL_OFFSET 0x0020 | |
249 | #define DRA7XX_CM_MPU_MPU_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_MPU_INST, 0x0020) | |
250 | #define DRA7XX_CM_MPU_MPU_MPU_DBG_CLKCTRL_OFFSET 0x0028 | |
251 | #define DRA7XX_CM_MPU_MPU_MPU_DBG_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_MPU_INST, 0x0028) | |
252 | ||
253 | /* CM_CORE_AON.DSP1_CM_CORE_AON register offsets */ | |
254 | #define DRA7XX_CM_DSP1_CLKSTCTRL_OFFSET 0x0000 | |
255 | #define DRA7XX_CM_DSP1_STATICDEP_OFFSET 0x0004 | |
256 | #define DRA7XX_CM_DSP1_DYNAMICDEP_OFFSET 0x0008 | |
257 | #define DRA7XX_CM_DSP1_DSP1_CLKCTRL_OFFSET 0x0020 | |
258 | #define DRA7XX_CM_DSP1_DSP1_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_DSP1_INST, 0x0020) | |
259 | ||
260 | /* CM_CORE_AON.IPU_CM_CORE_AON register offsets */ | |
261 | #define DRA7XX_CM_IPU1_CLKSTCTRL_OFFSET 0x0000 | |
262 | #define DRA7XX_CM_IPU1_STATICDEP_OFFSET 0x0004 | |
263 | #define DRA7XX_CM_IPU1_DYNAMICDEP_OFFSET 0x0008 | |
264 | #define DRA7XX_CM_IPU1_IPU1_CLKCTRL_OFFSET 0x0020 | |
265 | #define DRA7XX_CM_IPU1_IPU1_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_IPU_INST, 0x0020) | |
266 | #define DRA7XX_CM_IPU_CLKSTCTRL_OFFSET 0x0040 | |
267 | #define DRA7XX_CM_IPU_MCASP1_CLKCTRL_OFFSET 0x0050 | |
268 | #define DRA7XX_CM_IPU_MCASP1_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_IPU_INST, 0x0050) | |
269 | #define DRA7XX_CM_IPU_TIMER5_CLKCTRL_OFFSET 0x0058 | |
270 | #define DRA7XX_CM_IPU_TIMER5_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_IPU_INST, 0x0058) | |
271 | #define DRA7XX_CM_IPU_TIMER6_CLKCTRL_OFFSET 0x0060 | |
272 | #define DRA7XX_CM_IPU_TIMER6_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_IPU_INST, 0x0060) | |
273 | #define DRA7XX_CM_IPU_TIMER7_CLKCTRL_OFFSET 0x0068 | |
274 | #define DRA7XX_CM_IPU_TIMER7_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_IPU_INST, 0x0068) | |
275 | #define DRA7XX_CM_IPU_TIMER8_CLKCTRL_OFFSET 0x0070 | |
276 | #define DRA7XX_CM_IPU_TIMER8_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_IPU_INST, 0x0070) | |
277 | #define DRA7XX_CM_IPU_I2C5_CLKCTRL_OFFSET 0x0078 | |
278 | #define DRA7XX_CM_IPU_I2C5_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_IPU_INST, 0x0078) | |
279 | #define DRA7XX_CM_IPU_UART6_CLKCTRL_OFFSET 0x0080 | |
280 | #define DRA7XX_CM_IPU_UART6_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_IPU_INST, 0x0080) | |
281 | ||
282 | /* CM_CORE_AON.DSP2_CM_CORE_AON register offsets */ | |
283 | #define DRA7XX_CM_DSP2_CLKSTCTRL_OFFSET 0x0000 | |
284 | #define DRA7XX_CM_DSP2_STATICDEP_OFFSET 0x0004 | |
285 | #define DRA7XX_CM_DSP2_DYNAMICDEP_OFFSET 0x0008 | |
286 | #define DRA7XX_CM_DSP2_DSP2_CLKCTRL_OFFSET 0x0020 | |
287 | #define DRA7XX_CM_DSP2_DSP2_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_DSP2_INST, 0x0020) | |
288 | ||
289 | /* CM_CORE_AON.EVE1_CM_CORE_AON register offsets */ | |
290 | #define DRA7XX_CM_EVE1_CLKSTCTRL_OFFSET 0x0000 | |
291 | #define DRA7XX_CM_EVE1_STATICDEP_OFFSET 0x0004 | |
292 | #define DRA7XX_CM_EVE1_EVE1_CLKCTRL_OFFSET 0x0020 | |
293 | #define DRA7XX_CM_EVE1_EVE1_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_EVE1_INST, 0x0020) | |
294 | ||
295 | /* CM_CORE_AON.EVE2_CM_CORE_AON register offsets */ | |
296 | #define DRA7XX_CM_EVE2_CLKSTCTRL_OFFSET 0x0000 | |
297 | #define DRA7XX_CM_EVE2_STATICDEP_OFFSET 0x0004 | |
298 | #define DRA7XX_CM_EVE2_EVE2_CLKCTRL_OFFSET 0x0020 | |
299 | #define DRA7XX_CM_EVE2_EVE2_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_EVE2_INST, 0x0020) | |
300 | ||
301 | /* CM_CORE_AON.EVE3_CM_CORE_AON register offsets */ | |
302 | #define DRA7XX_CM_EVE3_CLKSTCTRL_OFFSET 0x0000 | |
303 | #define DRA7XX_CM_EVE3_STATICDEP_OFFSET 0x0004 | |
304 | #define DRA7XX_CM_EVE3_EVE3_CLKCTRL_OFFSET 0x0020 | |
305 | #define DRA7XX_CM_EVE3_EVE3_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_EVE3_INST, 0x0020) | |
306 | ||
307 | /* CM_CORE_AON.EVE4_CM_CORE_AON register offsets */ | |
308 | #define DRA7XX_CM_EVE4_CLKSTCTRL_OFFSET 0x0000 | |
309 | #define DRA7XX_CM_EVE4_STATICDEP_OFFSET 0x0004 | |
310 | #define DRA7XX_CM_EVE4_EVE4_CLKCTRL_OFFSET 0x0020 | |
311 | #define DRA7XX_CM_EVE4_EVE4_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_EVE4_INST, 0x0020) | |
312 | ||
313 | /* CM_CORE_AON.RTC_CM_CORE_AON register offsets */ | |
314 | #define DRA7XX_CM_RTC_CLKSTCTRL_OFFSET 0x0000 | |
315 | #define DRA7XX_CM_RTC_RTCSS_CLKCTRL_OFFSET 0x0004 | |
316 | #define DRA7XX_CM_RTC_RTCSS_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_RTC_INST, 0x0004) | |
317 | ||
318 | /* CM_CORE_AON.VPE_CM_CORE_AON register offsets */ | |
319 | #define DRA7XX_CM_VPE_CLKSTCTRL_OFFSET 0x0000 | |
320 | #define DRA7XX_CM_VPE_VPE_CLKCTRL_OFFSET 0x0004 | |
321 | #define DRA7XX_CM_VPE_VPE_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_VPE_INST, 0x0004) | |
322 | #define DRA7XX_CM_VPE_STATICDEP_OFFSET 0x0008 | |
323 | ||
324 | #endif |