projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 40ca6091 A |
1 | /* |
| 2 | * DRA7xx CM2 instance offset macros | |
| 3 | * | |
| 4 | * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com | |
| 5 | * | |
| 6 | * Generated by code originally written by: | |
| 7 | * Paul Walmsley (paul@pwsan.com) | |
| 8 | * Rajendra Nayak (rnayak@ti.com) | |
| 9 | * Benoit Cousson (b-cousson@ti.com) | |
| 10 | * | |
| 11 | * This file is automatically generated from the OMAP hardware databases. | |
| 12 | * We respectfully ask that any modifications to this file be coordinated | |
| 13 | * with the public linux-omap@vger.kernel.org mailing list and the | |
| 14 | * authors above to ensure that the autogeneration scripts are kept | |
| 15 | * up-to-date with the file contents. | |
| 16 | * | |
| 17 | * This program is free software; you can redistribute it and/or modify | |
| 18 | * it under the terms of the GNU General Public License version 2 as | |
| 19 | * published by the Free Software Foundation. | |
| 20 | */ | |
| 21 | ||
| 22 | #ifndef __ARCH_ARM_MACH_OMAP2_CM2_7XX_H | |
| 23 | #define __ARCH_ARM_MACH_OMAP2_CM2_7XX_H | |
| 24 | ||
| 25 | #include "cm_44xx_54xx.h" | |
| 26 | ||
| 27 | /* CM2 base address */ | |
| 28 | #define DRA7XX_CM_CORE_BASE 0x4a008000 | |
| 29 | ||
| 30 | #define DRA7XX_CM_CORE_REGADDR(inst, reg) \ | |
| 31 | OMAP2_L4_IO_ADDRESS(DRA7XX_CM_CORE_BASE + (inst) + (reg)) | |
| 32 | ||
| 33 | /* CM_CORE instances */ | |
| 34 | #define DRA7XX_CM_CORE_OCP_SOCKET_INST 0x0000 | |
| 35 | #define DRA7XX_CM_CORE_CKGEN_INST 0x0104 | |
| 36 | #define DRA7XX_CM_CORE_COREAON_INST 0x0600 | |
| 37 | #define DRA7XX_CM_CORE_CORE_INST 0x0700 | |
| 38 | #define DRA7XX_CM_CORE_IVA_INST 0x0f00 | |
| 39 | #define DRA7XX_CM_CORE_CAM_INST 0x1000 | |
| 40 | #define DRA7XX_CM_CORE_DSS_INST 0x1100 | |
| 41 | #define DRA7XX_CM_CORE_GPU_INST 0x1200 | |
| 42 | #define DRA7XX_CM_CORE_L3INIT_INST 0x1300 | |
| 43 | #define DRA7XX_CM_CORE_CUSTEFUSE_INST 0x1600 | |
| 44 | #define DRA7XX_CM_CORE_L4PER_INST 0x1700 | |
| 45 | #define DRA7XX_CM_CORE_RESTORE_INST 0x1e18 | |
| 46 | ||
| 47 | /* CM_CORE clockdomain register offsets (from instance start) */ | |
| 48 | #define DRA7XX_CM_CORE_COREAON_COREAON_CDOFFS 0x0000 | |
| 49 | #define DRA7XX_CM_CORE_CORE_L3MAIN1_CDOFFS 0x0000 | |
| 50 | #define DRA7XX_CM_CORE_CORE_IPU2_CDOFFS 0x0200 | |
| 51 | #define DRA7XX_CM_CORE_CORE_DMA_CDOFFS 0x0300 | |
| 52 | #define DRA7XX_CM_CORE_CORE_EMIF_CDOFFS 0x0400 | |
| 53 | #define DRA7XX_CM_CORE_CORE_ATL_CDOFFS 0x0520 | |
| 54 | #define DRA7XX_CM_CORE_CORE_L4CFG_CDOFFS 0x0600 | |
| 55 | #define DRA7XX_CM_CORE_CORE_L3INSTR_CDOFFS 0x0700 | |
| 56 | #define DRA7XX_CM_CORE_IVA_IVA_CDOFFS 0x0000 | |
| 57 | #define DRA7XX_CM_CORE_CAM_CAM_CDOFFS 0x0000 | |
| 58 | #define DRA7XX_CM_CORE_DSS_DSS_CDOFFS 0x0000 | |
| 59 | #define DRA7XX_CM_CORE_GPU_GPU_CDOFFS 0x0000 | |
| 60 | #define DRA7XX_CM_CORE_L3INIT_L3INIT_CDOFFS 0x0000 | |
| 61 | #define DRA7XX_CM_CORE_L3INIT_PCIE_CDOFFS 0x00a0 | |
| 62 | #define DRA7XX_CM_CORE_L3INIT_GMAC_CDOFFS 0x00c0 | |
| 63 | #define DRA7XX_CM_CORE_CUSTEFUSE_CUSTEFUSE_CDOFFS 0x0000 | |
| 64 | #define DRA7XX_CM_CORE_L4PER_L4PER_CDOFFS 0x0000 | |
| 65 | #define DRA7XX_CM_CORE_L4PER_L4SEC_CDOFFS 0x0180 | |
| 66 | #define DRA7XX_CM_CORE_L4PER_L4PER2_CDOFFS 0x01fc | |
| 67 | #define DRA7XX_CM_CORE_L4PER_L4PER3_CDOFFS 0x0210 | |
| 68 | ||
| 69 | /* CM_CORE */ | |
| 70 | ||
| 71 | /* CM_CORE.OCP_SOCKET_CM_CORE register offsets */ | |
| 72 | #define DRA7XX_REVISION_CM_CORE_OFFSET 0x0000 | |
| 73 | #define DRA7XX_CM_CM_CORE_PROFILING_CLKCTRL_OFFSET 0x0040 | |
| 74 | #define DRA7XX_CM_CM_CORE_PROFILING_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_OCP_SOCKET_INST, 0x0040) | |
| 75 | #define DRA7XX_CM_CORE_DEBUG_CFG_OFFSET 0x00f0 | |
| 76 | ||
| 77 | /* CM_CORE.CKGEN_CM_CORE register offsets */ | |
| 78 | #define DRA7XX_CM_CLKSEL_USB_60MHZ_OFFSET 0x0000 | |
| 79 | #define DRA7XX_CM_CLKSEL_USB_60MHZ DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0000) | |
| 80 | #define DRA7XX_CM_CLKMODE_DPLL_PER_OFFSET 0x003c | |
| 81 | #define DRA7XX_CM_CLKMODE_DPLL_PER DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x003c) | |
| 82 | #define DRA7XX_CM_IDLEST_DPLL_PER_OFFSET 0x0040 | |
| 83 | #define DRA7XX_CM_IDLEST_DPLL_PER DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0040) | |
| 84 | #define DRA7XX_CM_AUTOIDLE_DPLL_PER_OFFSET 0x0044 | |
| 85 | #define DRA7XX_CM_AUTOIDLE_DPLL_PER DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0044) | |
| 86 | #define DRA7XX_CM_CLKSEL_DPLL_PER_OFFSET 0x0048 | |
| 87 | #define DRA7XX_CM_CLKSEL_DPLL_PER DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0048) | |
| 88 | #define DRA7XX_CM_DIV_M2_DPLL_PER_OFFSET 0x004c | |
| 89 | #define DRA7XX_CM_DIV_M2_DPLL_PER DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x004c) | |
| 90 | #define DRA7XX_CM_DIV_M3_DPLL_PER_OFFSET 0x0050 | |
| 91 | #define DRA7XX_CM_DIV_M3_DPLL_PER DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0050) | |
| 92 | #define DRA7XX_CM_DIV_H11_DPLL_PER_OFFSET 0x0054 | |
| 93 | #define DRA7XX_CM_DIV_H11_DPLL_PER DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0054) | |
| 94 | #define DRA7XX_CM_DIV_H12_DPLL_PER_OFFSET 0x0058 | |
| 95 | #define DRA7XX_CM_DIV_H12_DPLL_PER DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0058) | |
| 96 | #define DRA7XX_CM_DIV_H13_DPLL_PER_OFFSET 0x005c | |
| 97 | #define DRA7XX_CM_DIV_H13_DPLL_PER DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x005c) | |
| 98 | #define DRA7XX_CM_DIV_H14_DPLL_PER_OFFSET 0x0060 | |
| 99 | #define DRA7XX_CM_DIV_H14_DPLL_PER DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0060) | |
| 100 | #define DRA7XX_CM_SSC_DELTAMSTEP_DPLL_PER_OFFSET 0x0064 | |
| 101 | #define DRA7XX_CM_SSC_MODFREQDIV_DPLL_PER_OFFSET 0x0068 | |
| 102 | #define DRA7XX_CM_CLKMODE_DPLL_USB_OFFSET 0x007c | |
| 103 | #define DRA7XX_CM_CLKMODE_DPLL_USB DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x007c) | |
| 104 | #define DRA7XX_CM_IDLEST_DPLL_USB_OFFSET 0x0080 | |
| 105 | #define DRA7XX_CM_IDLEST_DPLL_USB DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0080) | |
| 106 | #define DRA7XX_CM_AUTOIDLE_DPLL_USB_OFFSET 0x0084 | |
| 107 | #define DRA7XX_CM_AUTOIDLE_DPLL_USB DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0084) | |
| 108 | #define DRA7XX_CM_CLKSEL_DPLL_USB_OFFSET 0x0088 | |
| 109 | #define DRA7XX_CM_CLKSEL_DPLL_USB DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0088) | |
| 110 | #define DRA7XX_CM_DIV_M2_DPLL_USB_OFFSET 0x008c | |
| 111 | #define DRA7XX_CM_DIV_M2_DPLL_USB DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x008c) | |
| 112 | #define DRA7XX_CM_SSC_DELTAMSTEP_DPLL_USB_OFFSET 0x00a4 | |
| 113 | #define DRA7XX_CM_SSC_MODFREQDIV_DPLL_USB_OFFSET 0x00a8 | |
| 114 | #define DRA7XX_CM_CLKDCOLDO_DPLL_USB_OFFSET 0x00b0 | |
| 115 | #define DRA7XX_CM_CLKDCOLDO_DPLL_USB DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x00b0) | |
| 116 | #define DRA7XX_CM_CLKMODE_DPLL_PCIE_REF_OFFSET 0x00fc | |
| 117 | #define DRA7XX_CM_CLKMODE_DPLL_PCIE_REF DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x00fc) | |
| 118 | #define DRA7XX_CM_IDLEST_DPLL_PCIE_REF_OFFSET 0x0100 | |
| 119 | #define DRA7XX_CM_IDLEST_DPLL_PCIE_REF DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0100) | |
| 120 | #define DRA7XX_CM_AUTOIDLE_DPLL_PCIE_REF_OFFSET 0x0104 | |
| 121 | #define DRA7XX_CM_AUTOIDLE_DPLL_PCIE_REF DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0104) | |
| 122 | #define DRA7XX_CM_CLKSEL_DPLL_PCIE_REF_OFFSET 0x0108 | |
| 123 | #define DRA7XX_CM_CLKSEL_DPLL_PCIE_REF DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0108) | |
| 124 | #define DRA7XX_CM_DIV_M2_DPLL_PCIE_REF_OFFSET 0x010c | |
| 125 | #define DRA7XX_CM_DIV_M2_DPLL_PCIE_REF DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x010c) | |
| 126 | #define DRA7XX_CM_SSC_DELTAMSTEP_DPLL_PCIE_REF_OFFSET 0x0110 | |
| 127 | #define DRA7XX_CM_SSC_MODFREQDIV_DPLL_PCIE_REF_OFFSET 0x0114 | |
| 128 | #define DRA7XX_CM_CLKMODE_APLL_PCIE_OFFSET 0x0118 | |
| 129 | #define DRA7XX_CM_CLKMODE_APLL_PCIE DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0118) | |
| 130 | #define DRA7XX_CM_IDLEST_APLL_PCIE_OFFSET 0x011c | |
| 131 | #define DRA7XX_CM_IDLEST_APLL_PCIE DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x011c) | |
| 132 | #define DRA7XX_CM_DIV_M2_APLL_PCIE_OFFSET 0x0120 | |
| 133 | #define DRA7XX_CM_DIV_M2_APLL_PCIE DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0120) | |
| 134 | #define DRA7XX_CM_CLKVCOLDO_APLL_PCIE_OFFSET 0x0124 | |
| 135 | #define DRA7XX_CM_CLKVCOLDO_APLL_PCIE DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0124) | |
| 136 | ||
| 137 | /* CM_CORE.COREAON_CM_CORE register offsets */ | |
| 138 | #define DRA7XX_CM_COREAON_CLKSTCTRL_OFFSET 0x0000 | |
| 139 | #define DRA7XX_CM_COREAON_SMARTREFLEX_MPU_CLKCTRL_OFFSET 0x0028 | |
| 140 | #define DRA7XX_CM_COREAON_SMARTREFLEX_MPU_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x0028) | |
| 141 | #define DRA7XX_CM_COREAON_SMARTREFLEX_CORE_CLKCTRL_OFFSET 0x0038 | |
| 142 | #define DRA7XX_CM_COREAON_SMARTREFLEX_CORE_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x0038) | |
| 143 | #define DRA7XX_CM_COREAON_USB_PHY1_CORE_CLKCTRL_OFFSET 0x0040 | |
| 144 | #define DRA7XX_CM_COREAON_USB_PHY1_CORE_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x0040) | |
| 145 | #define DRA7XX_CM_COREAON_IO_SRCOMP_CLKCTRL_OFFSET 0x0050 | |
| 146 | #define DRA7XX_CM_COREAON_IO_SRCOMP_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x0050) | |
| 147 | #define DRA7XX_CM_COREAON_SMARTREFLEX_GPU_CLKCTRL_OFFSET 0x0058 | |
| 148 | #define DRA7XX_CM_COREAON_SMARTREFLEX_GPU_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x0058) | |
| 149 | #define DRA7XX_CM_COREAON_SMARTREFLEX_DSPEVE_CLKCTRL_OFFSET 0x0068 | |
| 150 | #define DRA7XX_CM_COREAON_SMARTREFLEX_DSPEVE_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x0068) | |
| 151 | #define DRA7XX_CM_COREAON_SMARTREFLEX_IVAHD_CLKCTRL_OFFSET 0x0078 | |
| 152 | #define DRA7XX_CM_COREAON_SMARTREFLEX_IVAHD_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x0078) | |
| 153 | #define DRA7XX_CM_COREAON_USB_PHY2_CORE_CLKCTRL_OFFSET 0x0088 | |
| 154 | #define DRA7XX_CM_COREAON_USB_PHY2_CORE_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x0088) | |
| 155 | #define DRA7XX_CM_COREAON_USB_PHY3_CORE_CLKCTRL_OFFSET 0x0098 | |
| 156 | #define DRA7XX_CM_COREAON_USB_PHY3_CORE_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x0098) | |
| 157 | #define DRA7XX_CM_COREAON_DUMMY_MODULE1_CLKCTRL_OFFSET 0x00a0 | |
| 158 | #define DRA7XX_CM_COREAON_DUMMY_MODULE1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x00a0) | |
| 159 | #define DRA7XX_CM_COREAON_DUMMY_MODULE2_CLKCTRL_OFFSET 0x00b0 | |
| 160 | #define DRA7XX_CM_COREAON_DUMMY_MODULE2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x00b0) | |
| 161 | #define DRA7XX_CM_COREAON_DUMMY_MODULE3_CLKCTRL_OFFSET 0x00c0 | |
| 162 | #define DRA7XX_CM_COREAON_DUMMY_MODULE3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x00c0) | |
| 163 | #define DRA7XX_CM_COREAON_DUMMY_MODULE4_CLKCTRL_OFFSET 0x00d0 | |
| 164 | #define DRA7XX_CM_COREAON_DUMMY_MODULE4_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x00d0) | |
| 165 | ||
| 166 | /* CM_CORE.CORE_CM_CORE register offsets */ | |
| 167 | #define DRA7XX_CM_L3MAIN1_CLKSTCTRL_OFFSET 0x0000 | |
| 168 | #define DRA7XX_CM_L3MAIN1_DYNAMICDEP_OFFSET 0x0008 | |
| 169 | #define DRA7XX_CM_L3MAIN1_L3_MAIN_1_CLKCTRL_OFFSET 0x0020 | |
| 170 | #define DRA7XX_CM_L3MAIN1_L3_MAIN_1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0020) | |
| 171 | #define DRA7XX_CM_L3MAIN1_GPMC_CLKCTRL_OFFSET 0x0028 | |
| 172 | #define DRA7XX_CM_L3MAIN1_GPMC_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0028) | |
| 173 | #define DRA7XX_CM_L3MAIN1_MMU_EDMA_CLKCTRL_OFFSET 0x0030 | |
| 174 | #define DRA7XX_CM_L3MAIN1_MMU_EDMA_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0030) | |
| 175 | #define DRA7XX_CM_L3MAIN1_OCMC_RAM1_CLKCTRL_OFFSET 0x0050 | |
| 176 | #define DRA7XX_CM_L3MAIN1_OCMC_RAM1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0050) | |
| 177 | #define DRA7XX_CM_L3MAIN1_OCMC_RAM2_CLKCTRL_OFFSET 0x0058 | |
| 178 | #define DRA7XX_CM_L3MAIN1_OCMC_RAM2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0058) | |
| 179 | #define DRA7XX_CM_L3MAIN1_OCMC_RAM3_CLKCTRL_OFFSET 0x0060 | |
| 180 | #define DRA7XX_CM_L3MAIN1_OCMC_RAM3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0060) | |
| 181 | #define DRA7XX_CM_L3MAIN1_OCMC_ROM_CLKCTRL_OFFSET 0x0068 | |
| 182 | #define DRA7XX_CM_L3MAIN1_OCMC_ROM_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0068) | |
| 183 | #define DRA7XX_CM_L3MAIN1_TPCC_CLKCTRL_OFFSET 0x0070 | |
| 184 | #define DRA7XX_CM_L3MAIN1_TPCC_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0070) | |
| 185 | #define DRA7XX_CM_L3MAIN1_TPTC1_CLKCTRL_OFFSET 0x0078 | |
| 186 | #define DRA7XX_CM_L3MAIN1_TPTC1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0078) | |
| 187 | #define DRA7XX_CM_L3MAIN1_TPTC2_CLKCTRL_OFFSET 0x0080 | |
| 188 | #define DRA7XX_CM_L3MAIN1_TPTC2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0080) | |
| 189 | #define DRA7XX_CM_L3MAIN1_VCP1_CLKCTRL_OFFSET 0x0088 | |
| 190 | #define DRA7XX_CM_L3MAIN1_VCP1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0088) | |
| 191 | #define DRA7XX_CM_L3MAIN1_VCP2_CLKCTRL_OFFSET 0x0090 | |
| 192 | #define DRA7XX_CM_L3MAIN1_VCP2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0090) | |
| 193 | #define DRA7XX_CM_L3MAIN1_SPARE_CME_CLKCTRL_OFFSET 0x0098 | |
| 194 | #define DRA7XX_CM_L3MAIN1_SPARE_CME_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0098) | |
| 195 | #define DRA7XX_CM_L3MAIN1_SPARE_HDMI_CLKCTRL_OFFSET 0x00a0 | |
| 196 | #define DRA7XX_CM_L3MAIN1_SPARE_HDMI_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x00a0) | |
| 197 | #define DRA7XX_CM_L3MAIN1_SPARE_ICM_CLKCTRL_OFFSET 0x00a8 | |
| 198 | #define DRA7XX_CM_L3MAIN1_SPARE_ICM_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x00a8) | |
| 199 | #define DRA7XX_CM_L3MAIN1_SPARE_IVA2_CLKCTRL_OFFSET 0x00b0 | |
| 200 | #define DRA7XX_CM_L3MAIN1_SPARE_IVA2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x00b0) | |
| 201 | #define DRA7XX_CM_L3MAIN1_SPARE_SATA2_CLKCTRL_OFFSET 0x00b8 | |
| 202 | #define DRA7XX_CM_L3MAIN1_SPARE_SATA2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x00b8) | |
| 203 | #define DRA7XX_CM_L3MAIN1_SPARE_UNKNOWN4_CLKCTRL_OFFSET 0x00c0 | |
| 204 | #define DRA7XX_CM_L3MAIN1_SPARE_UNKNOWN4_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x00c0) | |
| 205 | #define DRA7XX_CM_L3MAIN1_SPARE_UNKNOWN5_CLKCTRL_OFFSET 0x00c8 | |
| 206 | #define DRA7XX_CM_L3MAIN1_SPARE_UNKNOWN5_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x00c8) | |
| 207 | #define DRA7XX_CM_L3MAIN1_SPARE_UNKNOWN6_CLKCTRL_OFFSET 0x00d0 | |
| 208 | #define DRA7XX_CM_L3MAIN1_SPARE_UNKNOWN6_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x00d0) | |
| 209 | #define DRA7XX_CM_L3MAIN1_SPARE_VIDEOPLL1_CLKCTRL_OFFSET 0x00d8 | |
| 210 | #define DRA7XX_CM_L3MAIN1_SPARE_VIDEOPLL1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x00d8) | |
| 211 | #define DRA7XX_CM_L3MAIN1_SPARE_VIDEOPLL2_CLKCTRL_OFFSET 0x00f0 | |
| 212 | #define DRA7XX_CM_L3MAIN1_SPARE_VIDEOPLL2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x00f0) | |
| 213 | #define DRA7XX_CM_L3MAIN1_SPARE_VIDEOPLL3_CLKCTRL_OFFSET 0x00f8 | |
| 214 | #define DRA7XX_CM_L3MAIN1_SPARE_VIDEOPLL3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x00f8) | |
| 215 | #define DRA7XX_CM_IPU2_CLKSTCTRL_OFFSET 0x0200 | |
| 216 | #define DRA7XX_CM_IPU2_STATICDEP_OFFSET 0x0204 | |
| 217 | #define DRA7XX_CM_IPU2_DYNAMICDEP_OFFSET 0x0208 | |
| 218 | #define DRA7XX_CM_IPU2_IPU2_CLKCTRL_OFFSET 0x0220 | |
| 219 | #define DRA7XX_CM_IPU2_IPU2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0220) | |
| 220 | #define DRA7XX_CM_DMA_CLKSTCTRL_OFFSET 0x0300 | |
| 221 | #define DRA7XX_CM_DMA_STATICDEP_OFFSET 0x0304 | |
| 222 | #define DRA7XX_CM_DMA_DYNAMICDEP_OFFSET 0x0308 | |
| 223 | #define DRA7XX_CM_DMA_DMA_SYSTEM_CLKCTRL_OFFSET 0x0320 | |
| 224 | #define DRA7XX_CM_DMA_DMA_SYSTEM_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0320) | |
| 225 | #define DRA7XX_CM_EMIF_CLKSTCTRL_OFFSET 0x0400 | |
| 226 | #define DRA7XX_CM_EMIF_DMM_CLKCTRL_OFFSET 0x0420 | |
| 227 | #define DRA7XX_CM_EMIF_DMM_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0420) | |
| 228 | #define DRA7XX_CM_EMIF_EMIF_OCP_FW_CLKCTRL_OFFSET 0x0428 | |
| 229 | #define DRA7XX_CM_EMIF_EMIF_OCP_FW_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0428) | |
| 230 | #define DRA7XX_CM_EMIF_EMIF1_CLKCTRL_OFFSET 0x0430 | |
| 231 | #define DRA7XX_CM_EMIF_EMIF1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0430) | |
| 232 | #define DRA7XX_CM_EMIF_EMIF2_CLKCTRL_OFFSET 0x0438 | |
| 233 | #define DRA7XX_CM_EMIF_EMIF2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0438) | |
| 234 | #define DRA7XX_CM_EMIF_EMIF_DLL_CLKCTRL_OFFSET 0x0440 | |
| 235 | #define DRA7XX_CM_EMIF_EMIF_DLL_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0440) | |
| 236 | #define DRA7XX_CM_ATL_ATL_CLKCTRL_OFFSET 0x0500 | |
| 237 | #define DRA7XX_CM_ATL_ATL_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0500) | |
| 238 | #define DRA7XX_CM_ATL_CLKSTCTRL_OFFSET 0x0520 | |
| 239 | #define DRA7XX_CM_L4CFG_CLKSTCTRL_OFFSET 0x0600 | |
| 240 | #define DRA7XX_CM_L4CFG_DYNAMICDEP_OFFSET 0x0608 | |
| 241 | #define DRA7XX_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET 0x0620 | |
| 242 | #define DRA7XX_CM_L4CFG_L4_CFG_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0620) | |
| 243 | #define DRA7XX_CM_L4CFG_SPINLOCK_CLKCTRL_OFFSET 0x0628 | |
| 244 | #define DRA7XX_CM_L4CFG_SPINLOCK_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0628) | |
| 245 | #define DRA7XX_CM_L4CFG_MAILBOX1_CLKCTRL_OFFSET 0x0630 | |
| 246 | #define DRA7XX_CM_L4CFG_MAILBOX1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0630) | |
| 247 | #define DRA7XX_CM_L4CFG_SAR_ROM_CLKCTRL_OFFSET 0x0638 | |
| 248 | #define DRA7XX_CM_L4CFG_SAR_ROM_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0638) | |
| 249 | #define DRA7XX_CM_L4CFG_OCP2SCP2_CLKCTRL_OFFSET 0x0640 | |
| 250 | #define DRA7XX_CM_L4CFG_OCP2SCP2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0640) | |
| 251 | #define DRA7XX_CM_L4CFG_MAILBOX2_CLKCTRL_OFFSET 0x0648 | |
| 252 | #define DRA7XX_CM_L4CFG_MAILBOX2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0648) | |
| 253 | #define DRA7XX_CM_L4CFG_MAILBOX3_CLKCTRL_OFFSET 0x0650 | |
| 254 | #define DRA7XX_CM_L4CFG_MAILBOX3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0650) | |
| 255 | #define DRA7XX_CM_L4CFG_MAILBOX4_CLKCTRL_OFFSET 0x0658 | |
| 256 | #define DRA7XX_CM_L4CFG_MAILBOX4_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0658) | |
| 257 | #define DRA7XX_CM_L4CFG_MAILBOX5_CLKCTRL_OFFSET 0x0660 | |
| 258 | #define DRA7XX_CM_L4CFG_MAILBOX5_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0660) | |
| 259 | #define DRA7XX_CM_L4CFG_MAILBOX6_CLKCTRL_OFFSET 0x0668 | |
| 260 | #define DRA7XX_CM_L4CFG_MAILBOX6_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0668) | |
| 261 | #define DRA7XX_CM_L4CFG_MAILBOX7_CLKCTRL_OFFSET 0x0670 | |
| 262 | #define DRA7XX_CM_L4CFG_MAILBOX7_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0670) | |
| 263 | #define DRA7XX_CM_L4CFG_MAILBOX8_CLKCTRL_OFFSET 0x0678 | |
| 264 | #define DRA7XX_CM_L4CFG_MAILBOX8_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0678) | |
| 265 | #define DRA7XX_CM_L4CFG_MAILBOX9_CLKCTRL_OFFSET 0x0680 | |
| 266 | #define DRA7XX_CM_L4CFG_MAILBOX9_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0680) | |
| 267 | #define DRA7XX_CM_L4CFG_MAILBOX10_CLKCTRL_OFFSET 0x0688 | |
| 268 | #define DRA7XX_CM_L4CFG_MAILBOX10_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0688) | |
| 269 | #define DRA7XX_CM_L4CFG_MAILBOX11_CLKCTRL_OFFSET 0x0690 | |
| 270 | #define DRA7XX_CM_L4CFG_MAILBOX11_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0690) | |
| 271 | #define DRA7XX_CM_L4CFG_MAILBOX12_CLKCTRL_OFFSET 0x0698 | |
| 272 | #define DRA7XX_CM_L4CFG_MAILBOX12_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0698) | |
| 273 | #define DRA7XX_CM_L4CFG_MAILBOX13_CLKCTRL_OFFSET 0x06a0 | |
| 274 | #define DRA7XX_CM_L4CFG_MAILBOX13_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x06a0) | |
| 275 | #define DRA7XX_CM_L4CFG_SPARE_SMARTREFLEX_RTC_CLKCTRL_OFFSET 0x06a8 | |
| 276 | #define DRA7XX_CM_L4CFG_SPARE_SMARTREFLEX_RTC_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x06a8) | |
| 277 | #define DRA7XX_CM_L4CFG_SPARE_SMARTREFLEX_SDRAM_CLKCTRL_OFFSET 0x06b0 | |
| 278 | #define DRA7XX_CM_L4CFG_SPARE_SMARTREFLEX_SDRAM_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x06b0) | |
| 279 | #define DRA7XX_CM_L4CFG_SPARE_SMARTREFLEX_WKUP_CLKCTRL_OFFSET 0x06b8 | |
| 280 | #define DRA7XX_CM_L4CFG_SPARE_SMARTREFLEX_WKUP_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x06b8) | |
| 281 | #define DRA7XX_CM_L4CFG_IO_DELAY_BLOCK_CLKCTRL_OFFSET 0x06c0 | |
| 282 | #define DRA7XX_CM_L4CFG_IO_DELAY_BLOCK_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x06c0) | |
| 283 | #define DRA7XX_CM_L3INSTR_CLKSTCTRL_OFFSET 0x0700 | |
| 284 | #define DRA7XX_CM_L3INSTR_L3_MAIN_2_CLKCTRL_OFFSET 0x0720 | |
| 285 | #define DRA7XX_CM_L3INSTR_L3_MAIN_2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0720) | |
| 286 | #define DRA7XX_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET 0x0728 | |
| 287 | #define DRA7XX_CM_L3INSTR_L3_INSTR_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0728) | |
| 288 | #define DRA7XX_CM_L3INSTR_OCP_WP_NOC_CLKCTRL_OFFSET 0x0740 | |
| 289 | #define DRA7XX_CM_L3INSTR_OCP_WP_NOC_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0740) | |
| 290 | #define DRA7XX_CM_L3INSTR_DLL_AGING_CLKCTRL_OFFSET 0x0748 | |
| 291 | #define DRA7XX_CM_L3INSTR_DLL_AGING_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0748) | |
| 292 | #define DRA7XX_CM_L3INSTR_CTRL_MODULE_BANDGAP_CLKCTRL_OFFSET 0x0750 | |
| 293 | #define DRA7XX_CM_L3INSTR_CTRL_MODULE_BANDGAP_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0750) | |
| 294 | ||
| 295 | /* CM_CORE.IVA_CM_CORE register offsets */ | |
| 296 | #define DRA7XX_CM_IVA_CLKSTCTRL_OFFSET 0x0000 | |
| 297 | #define DRA7XX_CM_IVA_STATICDEP_OFFSET 0x0004 | |
| 298 | #define DRA7XX_CM_IVA_DYNAMICDEP_OFFSET 0x0008 | |
| 299 | #define DRA7XX_CM_IVA_IVA_CLKCTRL_OFFSET 0x0020 | |
| 300 | #define DRA7XX_CM_IVA_IVA_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_IVA_INST, 0x0020) | |
| 301 | #define DRA7XX_CM_IVA_SL2_CLKCTRL_OFFSET 0x0028 | |
| 302 | #define DRA7XX_CM_IVA_SL2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_IVA_INST, 0x0028) | |
| 303 | ||
| 304 | /* CM_CORE.CAM_CM_CORE register offsets */ | |
| 305 | #define DRA7XX_CM_CAM_CLKSTCTRL_OFFSET 0x0000 | |
| 306 | #define DRA7XX_CM_CAM_STATICDEP_OFFSET 0x0004 | |
| 307 | #define DRA7XX_CM_CAM_VIP1_CLKCTRL_OFFSET 0x0020 | |
| 308 | #define DRA7XX_CM_CAM_VIP1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CAM_INST, 0x0020) | |
| 309 | #define DRA7XX_CM_CAM_VIP2_CLKCTRL_OFFSET 0x0028 | |
| 310 | #define DRA7XX_CM_CAM_VIP2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CAM_INST, 0x0028) | |
| 311 | #define DRA7XX_CM_CAM_VIP3_CLKCTRL_OFFSET 0x0030 | |
| 312 | #define DRA7XX_CM_CAM_VIP3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CAM_INST, 0x0030) | |
| 313 | #define DRA7XX_CM_CAM_LVDSRX_CLKCTRL_OFFSET 0x0038 | |
| 314 | #define DRA7XX_CM_CAM_LVDSRX_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CAM_INST, 0x0038) | |
| 315 | #define DRA7XX_CM_CAM_CSI1_CLKCTRL_OFFSET 0x0040 | |
| 316 | #define DRA7XX_CM_CAM_CSI1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CAM_INST, 0x0040) | |
| 317 | #define DRA7XX_CM_CAM_CSI2_CLKCTRL_OFFSET 0x0048 | |
| 318 | #define DRA7XX_CM_CAM_CSI2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CAM_INST, 0x0048) | |
| 319 | ||
| 320 | /* CM_CORE.DSS_CM_CORE register offsets */ | |
| 321 | #define DRA7XX_CM_DSS_CLKSTCTRL_OFFSET 0x0000 | |
| 322 | #define DRA7XX_CM_DSS_STATICDEP_OFFSET 0x0004 | |
| 323 | #define DRA7XX_CM_DSS_DYNAMICDEP_OFFSET 0x0008 | |
| 324 | #define DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET 0x0020 | |
| 325 | #define DRA7XX_CM_DSS_DSS_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_DSS_INST, 0x0020) | |
| 326 | #define DRA7XX_CM_DSS_BB2D_CLKCTRL_OFFSET 0x0030 | |
| 327 | #define DRA7XX_CM_DSS_BB2D_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_DSS_INST, 0x0030) | |
| 328 | #define DRA7XX_CM_DSS_SDVENC_CLKCTRL_OFFSET 0x003c | |
| 329 | #define DRA7XX_CM_DSS_SDVENC_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_DSS_INST, 0x003c) | |
| 330 | ||
| 331 | /* CM_CORE.GPU_CM_CORE register offsets */ | |
| 332 | #define DRA7XX_CM_GPU_CLKSTCTRL_OFFSET 0x0000 | |
| 333 | #define DRA7XX_CM_GPU_STATICDEP_OFFSET 0x0004 | |
| 334 | #define DRA7XX_CM_GPU_DYNAMICDEP_OFFSET 0x0008 | |
| 335 | #define DRA7XX_CM_GPU_GPU_CLKCTRL_OFFSET 0x0020 | |
| 336 | #define DRA7XX_CM_GPU_GPU_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_GPU_INST, 0x0020) | |
| 337 | ||
| 338 | /* CM_CORE.L3INIT_CM_CORE register offsets */ | |
| 339 | #define DRA7XX_CM_L3INIT_CLKSTCTRL_OFFSET 0x0000 | |
| 340 | #define DRA7XX_CM_L3INIT_STATICDEP_OFFSET 0x0004 | |
| 341 | #define DRA7XX_CM_L3INIT_DYNAMICDEP_OFFSET 0x0008 | |
| 342 | #define DRA7XX_CM_L3INIT_MMC1_CLKCTRL_OFFSET 0x0028 | |
| 343 | #define DRA7XX_CM_L3INIT_MMC1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x0028) | |
| 344 | #define DRA7XX_CM_L3INIT_MMC2_CLKCTRL_OFFSET 0x0030 | |
| 345 | #define DRA7XX_CM_L3INIT_MMC2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x0030) | |
| 346 | #define DRA7XX_CM_L3INIT_USB_OTG_SS2_CLKCTRL_OFFSET 0x0040 | |
| 347 | #define DRA7XX_CM_L3INIT_USB_OTG_SS2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x0040) | |
| 348 | #define DRA7XX_CM_L3INIT_USB_OTG_SS3_CLKCTRL_OFFSET 0x0048 | |
| 349 | #define DRA7XX_CM_L3INIT_USB_OTG_SS3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x0048) | |
| 350 | #define DRA7XX_CM_L3INIT_USB_OTG_SS4_CLKCTRL_OFFSET 0x0050 | |
| 351 | #define DRA7XX_CM_L3INIT_USB_OTG_SS4_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x0050) | |
| 352 | #define DRA7XX_CM_L3INIT_MLB_SS_CLKCTRL_OFFSET 0x0058 | |
| 353 | #define DRA7XX_CM_L3INIT_MLB_SS_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x0058) | |
| 354 | #define DRA7XX_CM_L3INIT_IEEE1500_2_OCP_CLKCTRL_OFFSET 0x0078 | |
| 355 | #define DRA7XX_CM_L3INIT_IEEE1500_2_OCP_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x0078) | |
| 356 | #define DRA7XX_CM_L3INIT_SATA_CLKCTRL_OFFSET 0x0088 | |
| 357 | #define DRA7XX_CM_L3INIT_SATA_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x0088) | |
| 358 | #define DRA7XX_CM_PCIE_CLKSTCTRL_OFFSET 0x00a0 | |
| 359 | #define DRA7XX_CM_PCIE_STATICDEP_OFFSET 0x00a4 | |
| 360 | #define DRA7XX_CM_GMAC_CLKSTCTRL_OFFSET 0x00c0 | |
| 361 | #define DRA7XX_CM_GMAC_STATICDEP_OFFSET 0x00c4 | |
| 362 | #define DRA7XX_CM_GMAC_DYNAMICDEP_OFFSET 0x00c8 | |
| 363 | #define DRA7XX_CM_GMAC_GMAC_CLKCTRL_OFFSET 0x00d0 | |
| 364 | #define DRA7XX_CM_GMAC_GMAC_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x00d0) | |
| 365 | #define DRA7XX_CM_L3INIT_OCP2SCP1_CLKCTRL_OFFSET 0x00e0 | |
| 366 | #define DRA7XX_CM_L3INIT_OCP2SCP1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x00e0) | |
| 367 | #define DRA7XX_CM_L3INIT_OCP2SCP3_CLKCTRL_OFFSET 0x00e8 | |
| 368 | #define DRA7XX_CM_L3INIT_OCP2SCP3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x00e8) | |
| 369 | #define DRA7XX_CM_L3INIT_USB_OTG_SS1_CLKCTRL_OFFSET 0x00f0 | |
| 370 | #define DRA7XX_CM_L3INIT_USB_OTG_SS1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x00f0) | |
| 371 | ||
| 372 | /* CM_CORE.CUSTEFUSE_CM_CORE register offsets */ | |
| 373 | #define DRA7XX_CM_CUSTEFUSE_CLKSTCTRL_OFFSET 0x0000 | |
| 374 | #define DRA7XX_CM_CUSTEFUSE_EFUSE_CTRL_CUST_CLKCTRL_OFFSET 0x0020 | |
| 375 | #define DRA7XX_CM_CUSTEFUSE_EFUSE_CTRL_CUST_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CUSTEFUSE_INST, 0x0020) | |
| 376 | ||
| 377 | /* CM_CORE.L4PER_CM_CORE register offsets */ | |
| 378 | #define DRA7XX_CM_L4PER_CLKSTCTRL_OFFSET 0x0000 | |
| 379 | #define DRA7XX_CM_L4PER_DYNAMICDEP_OFFSET 0x0008 | |
| 380 | #define DRA7XX_CM_L4PER2_L4_PER2_CLKCTRL_OFFSET 0x000c | |
| 381 | #define DRA7XX_CM_L4PER2_L4_PER2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x000c) | |
| 382 | #define DRA7XX_CM_L4PER3_L4_PER3_CLKCTRL_OFFSET 0x0014 | |
| 383 | #define DRA7XX_CM_L4PER3_L4_PER3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0014) | |
| 384 | #define DRA7XX_CM_L4PER2_PRUSS1_CLKCTRL_OFFSET 0x0018 | |
| 385 | #define DRA7XX_CM_L4PER2_PRUSS1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0018) | |
| 386 | #define DRA7XX_CM_L4PER2_PRUSS2_CLKCTRL_OFFSET 0x0020 | |
| 387 | #define DRA7XX_CM_L4PER2_PRUSS2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0020) | |
| 388 | #define DRA7XX_CM_L4PER_TIMER10_CLKCTRL_OFFSET 0x0028 | |
| 389 | #define DRA7XX_CM_L4PER_TIMER10_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0028) | |
| 390 | #define DRA7XX_CM_L4PER_TIMER11_CLKCTRL_OFFSET 0x0030 | |
| 391 | #define DRA7XX_CM_L4PER_TIMER11_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0030) | |
| 392 | #define DRA7XX_CM_L4PER_TIMER2_CLKCTRL_OFFSET 0x0038 | |
| 393 | #define DRA7XX_CM_L4PER_TIMER2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0038) | |
| 394 | #define DRA7XX_CM_L4PER_TIMER3_CLKCTRL_OFFSET 0x0040 | |
| 395 | #define DRA7XX_CM_L4PER_TIMER3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0040) | |
| 396 | #define DRA7XX_CM_L4PER_TIMER4_CLKCTRL_OFFSET 0x0048 | |
| 397 | #define DRA7XX_CM_L4PER_TIMER4_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0048) | |
| 398 | #define DRA7XX_CM_L4PER_TIMER9_CLKCTRL_OFFSET 0x0050 | |
| 399 | #define DRA7XX_CM_L4PER_TIMER9_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0050) | |
| 400 | #define DRA7XX_CM_L4PER_ELM_CLKCTRL_OFFSET 0x0058 | |
| 401 | #define DRA7XX_CM_L4PER_ELM_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0058) | |
| 402 | #define DRA7XX_CM_L4PER_GPIO2_CLKCTRL_OFFSET 0x0060 | |
| 403 | #define DRA7XX_CM_L4PER_GPIO2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0060) | |
| 404 | #define DRA7XX_CM_L4PER_GPIO3_CLKCTRL_OFFSET 0x0068 | |
| 405 | #define DRA7XX_CM_L4PER_GPIO3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0068) | |
| 406 | #define DRA7XX_CM_L4PER_GPIO4_CLKCTRL_OFFSET 0x0070 | |
| 407 | #define DRA7XX_CM_L4PER_GPIO4_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0070) | |
| 408 | #define DRA7XX_CM_L4PER_GPIO5_CLKCTRL_OFFSET 0x0078 | |
| 409 | #define DRA7XX_CM_L4PER_GPIO5_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0078) | |
| 410 | #define DRA7XX_CM_L4PER_GPIO6_CLKCTRL_OFFSET 0x0080 | |
| 411 | #define DRA7XX_CM_L4PER_GPIO6_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0080) | |
| 412 | #define DRA7XX_CM_L4PER_HDQ1W_CLKCTRL_OFFSET 0x0088 | |
| 413 | #define DRA7XX_CM_L4PER_HDQ1W_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0088) | |
| 414 | #define DRA7XX_CM_L4PER2_PWMSS2_CLKCTRL_OFFSET 0x0090 | |
| 415 | #define DRA7XX_CM_L4PER2_PWMSS2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0090) | |
| 416 | #define DRA7XX_CM_L4PER2_PWMSS3_CLKCTRL_OFFSET 0x0098 | |
| 417 | #define DRA7XX_CM_L4PER2_PWMSS3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0098) | |
| 418 | #define DRA7XX_CM_L4PER_I2C1_CLKCTRL_OFFSET 0x00a0 | |
| 419 | #define DRA7XX_CM_L4PER_I2C1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00a0) | |
| 420 | #define DRA7XX_CM_L4PER_I2C2_CLKCTRL_OFFSET 0x00a8 | |
| 421 | #define DRA7XX_CM_L4PER_I2C2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00a8) | |
| 422 | #define DRA7XX_CM_L4PER_I2C3_CLKCTRL_OFFSET 0x00b0 | |
| 423 | #define DRA7XX_CM_L4PER_I2C3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00b0) | |
| 424 | #define DRA7XX_CM_L4PER_I2C4_CLKCTRL_OFFSET 0x00b8 | |
| 425 | #define DRA7XX_CM_L4PER_I2C4_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00b8) | |
| 426 | #define DRA7XX_CM_L4PER_L4_PER1_CLKCTRL_OFFSET 0x00c0 | |
| 427 | #define DRA7XX_CM_L4PER_L4_PER1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00c0) | |
| 428 | #define DRA7XX_CM_L4PER2_PWMSS1_CLKCTRL_OFFSET 0x00c4 | |
| 429 | #define DRA7XX_CM_L4PER2_PWMSS1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00c4) | |
| 430 | #define DRA7XX_CM_L4PER3_TIMER13_CLKCTRL_OFFSET 0x00c8 | |
| 431 | #define DRA7XX_CM_L4PER3_TIMER13_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00c8) | |
| 432 | #define DRA7XX_CM_L4PER3_TIMER14_CLKCTRL_OFFSET 0x00d0 | |
| 433 | #define DRA7XX_CM_L4PER3_TIMER14_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00d0) | |
| 434 | #define DRA7XX_CM_L4PER3_TIMER15_CLKCTRL_OFFSET 0x00d8 | |
| 435 | #define DRA7XX_CM_L4PER3_TIMER15_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00d8) | |
| 436 | #define DRA7XX_CM_L4PER_MCSPI1_CLKCTRL_OFFSET 0x00f0 | |
| 437 | #define DRA7XX_CM_L4PER_MCSPI1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00f0) | |
| 438 | #define DRA7XX_CM_L4PER_MCSPI2_CLKCTRL_OFFSET 0x00f8 | |
| 439 | #define DRA7XX_CM_L4PER_MCSPI2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00f8) | |
| 440 | #define DRA7XX_CM_L4PER_MCSPI3_CLKCTRL_OFFSET 0x0100 | |
| 441 | #define DRA7XX_CM_L4PER_MCSPI3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0100) | |
| 442 | #define DRA7XX_CM_L4PER_MCSPI4_CLKCTRL_OFFSET 0x0108 | |
| 443 | #define DRA7XX_CM_L4PER_MCSPI4_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0108) | |
| 444 | #define DRA7XX_CM_L4PER_GPIO7_CLKCTRL_OFFSET 0x0110 | |
| 445 | #define DRA7XX_CM_L4PER_GPIO7_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0110) | |
| 446 | #define DRA7XX_CM_L4PER_GPIO8_CLKCTRL_OFFSET 0x0118 | |
| 447 | #define DRA7XX_CM_L4PER_GPIO8_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0118) | |
| 448 | #define DRA7XX_CM_L4PER_MMC3_CLKCTRL_OFFSET 0x0120 | |
| 449 | #define DRA7XX_CM_L4PER_MMC3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0120) | |
| 450 | #define DRA7XX_CM_L4PER_MMC4_CLKCTRL_OFFSET 0x0128 | |
| 451 | #define DRA7XX_CM_L4PER_MMC4_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0128) | |
| 452 | #define DRA7XX_CM_L4PER3_TIMER16_CLKCTRL_OFFSET 0x0130 | |
| 453 | #define DRA7XX_CM_L4PER3_TIMER16_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0130) | |
| 454 | #define DRA7XX_CM_L4PER2_QSPI_CLKCTRL_OFFSET 0x0138 | |
| 455 | #define DRA7XX_CM_L4PER2_QSPI_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0138) | |
| 456 | #define DRA7XX_CM_L4PER_UART1_CLKCTRL_OFFSET 0x0140 | |
| 457 | #define DRA7XX_CM_L4PER_UART1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0140) | |
| 458 | #define DRA7XX_CM_L4PER_UART2_CLKCTRL_OFFSET 0x0148 | |
| 459 | #define DRA7XX_CM_L4PER_UART2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0148) | |
| 460 | #define DRA7XX_CM_L4PER_UART3_CLKCTRL_OFFSET 0x0150 | |
| 461 | #define DRA7XX_CM_L4PER_UART3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0150) | |
| 462 | #define DRA7XX_CM_L4PER_UART4_CLKCTRL_OFFSET 0x0158 | |
| 463 | #define DRA7XX_CM_L4PER_UART4_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0158) | |
| 464 | #define DRA7XX_CM_L4PER2_MCASP2_CLKCTRL_OFFSET 0x0160 | |
| 465 | #define DRA7XX_CM_L4PER2_MCASP2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0160) | |
| 466 | #define DRA7XX_CM_L4PER2_MCASP3_CLKCTRL_OFFSET 0x0168 | |
| 467 | #define DRA7XX_CM_L4PER2_MCASP3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0168) | |
| 468 | #define DRA7XX_CM_L4PER_UART5_CLKCTRL_OFFSET 0x0170 | |
| 469 | #define DRA7XX_CM_L4PER_UART5_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0170) | |
| 470 | #define DRA7XX_CM_L4PER2_MCASP5_CLKCTRL_OFFSET 0x0178 | |
| 471 | #define DRA7XX_CM_L4PER2_MCASP5_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0178) | |
| 472 | #define DRA7XX_CM_L4SEC_CLKSTCTRL_OFFSET 0x0180 | |
| 473 | #define DRA7XX_CM_L4SEC_STATICDEP_OFFSET 0x0184 | |
| 474 | #define DRA7XX_CM_L4SEC_DYNAMICDEP_OFFSET 0x0188 | |
| 475 | #define DRA7XX_CM_L4PER2_MCASP8_CLKCTRL_OFFSET 0x0190 | |
| 476 | #define DRA7XX_CM_L4PER2_MCASP8_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0190) | |
| 477 | #define DRA7XX_CM_L4PER2_MCASP4_CLKCTRL_OFFSET 0x0198 | |
| 478 | #define DRA7XX_CM_L4PER2_MCASP4_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0198) | |
| 479 | #define DRA7XX_CM_L4SEC_AES1_CLKCTRL_OFFSET 0x01a0 | |
| 480 | #define DRA7XX_CM_L4SEC_AES1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01a0) | |
| 481 | #define DRA7XX_CM_L4SEC_AES2_CLKCTRL_OFFSET 0x01a8 | |
| 482 | #define DRA7XX_CM_L4SEC_AES2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01a8) | |
| 483 | #define DRA7XX_CM_L4SEC_DES3DES_CLKCTRL_OFFSET 0x01b0 | |
| 484 | #define DRA7XX_CM_L4SEC_DES3DES_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01b0) | |
| 485 | #define DRA7XX_CM_L4SEC_FPKA_CLKCTRL_OFFSET 0x01b8 | |
| 486 | #define DRA7XX_CM_L4SEC_FPKA_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01b8) | |
| 487 | #define DRA7XX_CM_L4SEC_RNG_CLKCTRL_OFFSET 0x01c0 | |
| 488 | #define DRA7XX_CM_L4SEC_RNG_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01c0) | |
| 489 | #define DRA7XX_CM_L4SEC_SHA2MD51_CLKCTRL_OFFSET 0x01c8 | |
| 490 | #define DRA7XX_CM_L4SEC_SHA2MD51_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01c8) | |
| 491 | #define DRA7XX_CM_L4PER2_UART7_CLKCTRL_OFFSET 0x01d0 | |
| 492 | #define DRA7XX_CM_L4PER2_UART7_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01d0) | |
| 493 | #define DRA7XX_CM_L4SEC_DMA_CRYPTO_CLKCTRL_OFFSET 0x01d8 | |
| 494 | #define DRA7XX_CM_L4SEC_DMA_CRYPTO_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01d8) | |
| 495 | #define DRA7XX_CM_L4PER2_UART8_CLKCTRL_OFFSET 0x01e0 | |
| 496 | #define DRA7XX_CM_L4PER2_UART8_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01e0) | |
| 497 | #define DRA7XX_CM_L4PER2_UART9_CLKCTRL_OFFSET 0x01e8 | |
| 498 | #define DRA7XX_CM_L4PER2_UART9_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01e8) | |
| 499 | #define DRA7XX_CM_L4PER2_DCAN2_CLKCTRL_OFFSET 0x01f0 | |
| 500 | #define DRA7XX_CM_L4PER2_DCAN2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01f0) | |
| 501 | #define DRA7XX_CM_L4SEC_SHA2MD52_CLKCTRL_OFFSET 0x01f8 | |
| 502 | #define DRA7XX_CM_L4SEC_SHA2MD52_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01f8) | |
| 503 | #define DRA7XX_CM_L4PER2_CLKSTCTRL_OFFSET 0x01fc | |
| 504 | #define DRA7XX_CM_L4PER2_DYNAMICDEP_OFFSET 0x0200 | |
| 505 | #define DRA7XX_CM_L4PER2_MCASP6_CLKCTRL_OFFSET 0x0204 | |
| 506 | #define DRA7XX_CM_L4PER2_MCASP6_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0204) | |
| 507 | #define DRA7XX_CM_L4PER2_MCASP7_CLKCTRL_OFFSET 0x0208 | |
| 508 | #define DRA7XX_CM_L4PER2_MCASP7_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0208) | |
| 509 | #define DRA7XX_CM_L4PER2_STATICDEP_OFFSET 0x020c | |
| 510 | #define DRA7XX_CM_L4PER3_CLKSTCTRL_OFFSET 0x0210 | |
| 511 | #define DRA7XX_CM_L4PER3_DYNAMICDEP_OFFSET 0x0214 | |
| 512 | ||
| 513 | #endif |