[deliverable/linux.git] / arch / arm / mach-omap2 / cm2xxx_3xxx.c

/*
 * OMAP2/3 CM module functions
 *
 * Copyright (C) 2009 Nokia Corporation
 * Paul Walmsley
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/delay.h>
#include <linux/spinlock.h>
#include <linux/list.h>
#include <linux/errno.h>
#include <linux/err.h>
#include <linux/io.h>

#include <plat/common.h>

#include "cm.h"
#include "cm2xxx_3xxx.h"
#include "cm-regbits-24xx.h"
#include "cm-regbits-34xx.h"

static const u8 cm_idlest_offs[] = {
	CM_IDLEST1, CM_IDLEST2, OMAP2430_CM_IDLEST3
};

u32 omap2_cm_read_mod_reg(s16 module, u16 idx)
{
	return __raw_readl(cm_base + module + idx);
}

void omap2_cm_write_mod_reg(u32 val, s16 module, u16 idx)
{
	__raw_writel(val, cm_base + module + idx);
}

/* Read-modify-write a register in a CM module. Caller must lock */
u32 omap2_cm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx)
{
	u32 v;

	v = omap2_cm_read_mod_reg(module, idx);
	v &= ~mask;
	v |= bits;
	omap2_cm_write_mod_reg(v, module, idx);

	return v;
}

u32 omap2_cm_set_mod_reg_bits(u32 bits, s16 module, s16 idx)
{
	return omap2_cm_rmw_mod_reg_bits(bits, bits, module, idx);
}

u32 omap2_cm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx)
{
	return omap2_cm_rmw_mod_reg_bits(bits, 0x0, module, idx);
}

/*
 *
 */

static void _write_clktrctrl(u8 c, s16 module, u32 mask)
{
	u32 v;

	v = omap2_cm_read_mod_reg(module, OMAP2_CM_CLKSTCTRL);
	v &= ~mask;
	v |= c << __ffs(mask);
	omap2_cm_write_mod_reg(v, module, OMAP2_CM_CLKSTCTRL);
}

bool omap2_cm_is_clkdm_in_hwsup(s16 module, u32 mask)
{
	u32 v;
	bool ret = 0;

	BUG_ON(!cpu_is_omap24xx() && !cpu_is_omap34xx());

	v = omap2_cm_read_mod_reg(module, OMAP2_CM_CLKSTCTRL);
	v &= mask;
	v >>= __ffs(mask);

	if (cpu_is_omap24xx())
		ret = (v == OMAP24XX_CLKSTCTRL_ENABLE_AUTO) ? 1 : 0;
	else
		ret = (v == OMAP34XX_CLKSTCTRL_ENABLE_AUTO) ? 1 : 0;

	return ret;
}

void omap2xxx_cm_clkdm_enable_hwsup(s16 module, u32 mask)
{
	_write_clktrctrl(OMAP24XX_CLKSTCTRL_ENABLE_AUTO, module, mask);
}

void omap2xxx_cm_clkdm_disable_hwsup(s16 module, u32 mask)
{
	_write_clktrctrl(OMAP24XX_CLKSTCTRL_DISABLE_AUTO, module, mask);
}

void omap3xxx_cm_clkdm_enable_hwsup(s16 module, u32 mask)
{
	_write_clktrctrl(OMAP34XX_CLKSTCTRL_ENABLE_AUTO, module, mask);
}

void omap3xxx_cm_clkdm_disable_hwsup(s16 module, u32 mask)
{
	_write_clktrctrl(OMAP34XX_CLKSTCTRL_DISABLE_AUTO, module, mask);
}

void omap3xxx_cm_clkdm_force_sleep(s16 module, u32 mask)
{
	_write_clktrctrl(OMAP34XX_CLKSTCTRL_FORCE_SLEEP, module, mask);
}

void omap3xxx_cm_clkdm_force_wakeup(s16 module, u32 mask)
{
	_write_clktrctrl(OMAP34XX_CLKSTCTRL_FORCE_WAKEUP, module, mask);
}


/*
 *
 */

/**
 * omap2_cm_wait_idlest_ready - wait for a module to leave idle or standby
 * @prcm_mod: PRCM module offset
 * @idlest_id: CM_IDLESTx register ID (i.e., x = 1, 2, 3)
 * @idlest_shift: shift of the bit in the CM_IDLEST* register to check
 *
 * XXX document
 */
int omap2_cm_wait_module_ready(s16 prcm_mod, u8 idlest_id, u8 idlest_shift)
{
	int ena = 0, i = 0;
	u8 cm_idlest_reg;
	u32 mask;

	if (!idlest_id || (idlest_id > ARRAY_SIZE(cm_idlest_offs)))
		return -EINVAL;

	cm_idlest_reg = cm_idlest_offs[idlest_id - 1];

	mask = 1 << idlest_shift;

	if (cpu_is_omap24xx())
		ena = mask;
	else if (cpu_is_omap34xx())
		ena = 0;
	else
		BUG();

	omap_test_timeout(((omap2_cm_read_mod_reg(prcm_mod, cm_idlest_reg) & mask) == ena),
			  MAX_MODULE_READY_TIME, i);

	return (i < MAX_MODULE_READY_TIME) ? 0 : -EBUSY;
}

/*
 * Context save/restore code - OMAP3 only
 */
#ifdef CONFIG_ARCH_OMAP3
struct omap3_cm_regs {
	u32 iva2_cm_clksel1;
	u32 iva2_cm_clksel2;
	u32 cm_sysconfig;
	u32 sgx_cm_clksel;
	u32 dss_cm_clksel;
	u32 cam_cm_clksel;
	u32 per_cm_clksel;
	u32 emu_cm_clksel;
	u32 emu_cm_clkstctrl;
	u32 pll_cm_autoidle2;
	u32 pll_cm_clksel4;
	u32 pll_cm_clksel5;
	u32 pll_cm_clken2;
	u32 cm_polctrl;
	u32 iva2_cm_fclken;
	u32 iva2_cm_clken_pll;
	u32 core_cm_fclken1;
	u32 core_cm_fclken3;
	u32 sgx_cm_fclken;
	u32 wkup_cm_fclken;
	u32 dss_cm_fclken;
	u32 cam_cm_fclken;
	u32 per_cm_fclken;
	u32 usbhost_cm_fclken;
	u32 core_cm_iclken1;
	u32 core_cm_iclken2;
	u32 core_cm_iclken3;
	u32 sgx_cm_iclken;
	u32 wkup_cm_iclken;
	u32 dss_cm_iclken;
	u32 cam_cm_iclken;
	u32 per_cm_iclken;
	u32 usbhost_cm_iclken;
	u32 iva2_cm_autoidle2;
	u32 mpu_cm_autoidle2;
	u32 iva2_cm_clkstctrl;
	u32 mpu_cm_clkstctrl;
	u32 core_cm_clkstctrl;
	u32 sgx_cm_clkstctrl;
	u32 dss_cm_clkstctrl;
	u32 cam_cm_clkstctrl;
	u32 per_cm_clkstctrl;
	u32 neon_cm_clkstctrl;
	u32 usbhost_cm_clkstctrl;
	u32 core_cm_autoidle1;
	u32 core_cm_autoidle2;
	u32 core_cm_autoidle3;
	u32 wkup_cm_autoidle;
	u32 dss_cm_autoidle;
	u32 cam_cm_autoidle;
	u32 per_cm_autoidle;
	u32 usbhost_cm_autoidle;
	u32 sgx_cm_sleepdep;
	u32 dss_cm_sleepdep;
	u32 cam_cm_sleepdep;
	u32 per_cm_sleepdep;
	u32 usbhost_cm_sleepdep;
	u32 cm_clkout_ctrl;
};

static struct omap3_cm_regs cm_context;

void omap3_cm_save_context(void)
{
	cm_context.iva2_cm_clksel1 =
		omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_CLKSEL1);
	cm_context.iva2_cm_clksel2 =
		omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_CLKSEL2);
	cm_context.cm_sysconfig = __raw_readl(OMAP3430_CM_SYSCONFIG);
	cm_context.sgx_cm_clksel =
		omap2_cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_CLKSEL);
	cm_context.dss_cm_clksel =
		omap2_cm_read_mod_reg(OMAP3430_DSS_MOD, CM_CLKSEL);
	cm_context.cam_cm_clksel =
		omap2_cm_read_mod_reg(OMAP3430_CAM_MOD, CM_CLKSEL);
	cm_context.per_cm_clksel =
		omap2_cm_read_mod_reg(OMAP3430_PER_MOD, CM_CLKSEL);
	cm_context.emu_cm_clksel =
		omap2_cm_read_mod_reg(OMAP3430_EMU_MOD, CM_CLKSEL1);
	cm_context.emu_cm_clkstctrl =
		omap2_cm_read_mod_reg(OMAP3430_EMU_MOD, OMAP2_CM_CLKSTCTRL);
	cm_context.pll_cm_autoidle2 =
		omap2_cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE2);
	cm_context.pll_cm_clksel4 =
		omap2_cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKSEL4);
	cm_context.pll_cm_clksel5 =
		omap2_cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKSEL5);
	cm_context.pll_cm_clken2 =
		omap2_cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKEN2);
	cm_context.cm_polctrl = __raw_readl(OMAP3430_CM_POLCTRL);
	cm_context.iva2_cm_fclken =
		omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_FCLKEN);
	cm_context.iva2_cm_clken_pll =
		omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKEN_PLL);
	cm_context.core_cm_fclken1 =
		omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
	cm_context.core_cm_fclken3 =
		omap2_cm_read_mod_reg(CORE_MOD, OMAP3430ES2_CM_FCLKEN3);
	cm_context.sgx_cm_fclken =
		omap2_cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_FCLKEN);
	cm_context.wkup_cm_fclken =
		omap2_cm_read_mod_reg(WKUP_MOD, CM_FCLKEN);
	cm_context.dss_cm_fclken =
		omap2_cm_read_mod_reg(OMAP3430_DSS_MOD, CM_FCLKEN);
	cm_context.cam_cm_fclken =
		omap2_cm_read_mod_reg(OMAP3430_CAM_MOD, CM_FCLKEN);
	cm_context.per_cm_fclken =
		omap2_cm_read_mod_reg(OMAP3430_PER_MOD, CM_FCLKEN);
	cm_context.usbhost_cm_fclken =
		omap2_cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN);
	cm_context.core_cm_iclken1 =
		omap2_cm_read_mod_reg(CORE_MOD, CM_ICLKEN1);
	cm_context.core_cm_iclken2 =
		omap2_cm_read_mod_reg(CORE_MOD, CM_ICLKEN2);
	cm_context.core_cm_iclken3 =
		omap2_cm_read_mod_reg(CORE_MOD, CM_ICLKEN3);
	cm_context.sgx_cm_iclken =
		omap2_cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_ICLKEN);
	cm_context.wkup_cm_iclken =
		omap2_cm_read_mod_reg(WKUP_MOD, CM_ICLKEN);
	cm_context.dss_cm_iclken =
		omap2_cm_read_mod_reg(OMAP3430_DSS_MOD, CM_ICLKEN);
	cm_context.cam_cm_iclken =
		omap2_cm_read_mod_reg(OMAP3430_CAM_MOD, CM_ICLKEN);
	cm_context.per_cm_iclken =
		omap2_cm_read_mod_reg(OMAP3430_PER_MOD, CM_ICLKEN);
	cm_context.usbhost_cm_iclken =
		omap2_cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN);
	cm_context.iva2_cm_autoidle2 =
		omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_AUTOIDLE2);
	cm_context.mpu_cm_autoidle2 =
		omap2_cm_read_mod_reg(MPU_MOD, CM_AUTOIDLE2);
	cm_context.iva2_cm_clkstctrl =
		omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP2_CM_CLKSTCTRL);
	cm_context.mpu_cm_clkstctrl =
		omap2_cm_read_mod_reg(MPU_MOD, OMAP2_CM_CLKSTCTRL);
	cm_context.core_cm_clkstctrl =
		omap2_cm_read_mod_reg(CORE_MOD, OMAP2_CM_CLKSTCTRL);
	cm_context.sgx_cm_clkstctrl =
		omap2_cm_read_mod_reg(OMAP3430ES2_SGX_MOD, OMAP2_CM_CLKSTCTRL);
	cm_context.dss_cm_clkstctrl =
		omap2_cm_read_mod_reg(OMAP3430_DSS_MOD, OMAP2_CM_CLKSTCTRL);
	cm_context.cam_cm_clkstctrl =
		omap2_cm_read_mod_reg(OMAP3430_CAM_MOD, OMAP2_CM_CLKSTCTRL);
	cm_context.per_cm_clkstctrl =
		omap2_cm_read_mod_reg(OMAP3430_PER_MOD, OMAP2_CM_CLKSTCTRL);
	cm_context.neon_cm_clkstctrl =
		omap2_cm_read_mod_reg(OMAP3430_NEON_MOD, OMAP2_CM_CLKSTCTRL);
	cm_context.usbhost_cm_clkstctrl =
		omap2_cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD,
				      OMAP2_CM_CLKSTCTRL);
	cm_context.core_cm_autoidle1 =
		omap2_cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE1);
	cm_context.core_cm_autoidle2 =
		omap2_cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE2);
	cm_context.core_cm_autoidle3 =
		omap2_cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE3);
	cm_context.wkup_cm_autoidle =
		omap2_cm_read_mod_reg(WKUP_MOD, CM_AUTOIDLE);
	cm_context.dss_cm_autoidle =
		omap2_cm_read_mod_reg(OMAP3430_DSS_MOD, CM_AUTOIDLE);
	cm_context.cam_cm_autoidle =
		omap2_cm_read_mod_reg(OMAP3430_CAM_MOD, CM_AUTOIDLE);
	cm_context.per_cm_autoidle =
		omap2_cm_read_mod_reg(OMAP3430_PER_MOD, CM_AUTOIDLE);
	cm_context.usbhost_cm_autoidle =
		omap2_cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_AUTOIDLE);
	cm_context.sgx_cm_sleepdep =
		omap2_cm_read_mod_reg(OMAP3430ES2_SGX_MOD,
				      OMAP3430_CM_SLEEPDEP);
	cm_context.dss_cm_sleepdep =
		omap2_cm_read_mod_reg(OMAP3430_DSS_MOD, OMAP3430_CM_SLEEPDEP);
	cm_context.cam_cm_sleepdep =
		omap2_cm_read_mod_reg(OMAP3430_CAM_MOD, OMAP3430_CM_SLEEPDEP);
	cm_context.per_cm_sleepdep =
		omap2_cm_read_mod_reg(OMAP3430_PER_MOD, OMAP3430_CM_SLEEPDEP);
	cm_context.usbhost_cm_sleepdep =
		omap2_cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD,
				      OMAP3430_CM_SLEEPDEP);
	cm_context.cm_clkout_ctrl =
		omap2_cm_read_mod_reg(OMAP3430_CCR_MOD,
				      OMAP3_CM_CLKOUT_CTRL_OFFSET);
}

void omap3_cm_restore_context(void)
{
	omap2_cm_write_mod_reg(cm_context.iva2_cm_clksel1, OMAP3430_IVA2_MOD,
			       CM_CLKSEL1);
	omap2_cm_write_mod_reg(cm_context.iva2_cm_clksel2, OMAP3430_IVA2_MOD,
			       CM_CLKSEL2);
	__raw_writel(cm_context.cm_sysconfig, OMAP3430_CM_SYSCONFIG);
	omap2_cm_write_mod_reg(cm_context.sgx_cm_clksel, OMAP3430ES2_SGX_MOD,
			       CM_CLKSEL);
	omap2_cm_write_mod_reg(cm_context.dss_cm_clksel, OMAP3430_DSS_MOD,
			       CM_CLKSEL);
	omap2_cm_write_mod_reg(cm_context.cam_cm_clksel, OMAP3430_CAM_MOD,
			       CM_CLKSEL);
	omap2_cm_write_mod_reg(cm_context.per_cm_clksel, OMAP3430_PER_MOD,
			       CM_CLKSEL);
	omap2_cm_write_mod_reg(cm_context.emu_cm_clksel, OMAP3430_EMU_MOD,
			       CM_CLKSEL1);
	omap2_cm_write_mod_reg(cm_context.emu_cm_clkstctrl, OMAP3430_EMU_MOD,
			       OMAP2_CM_CLKSTCTRL);
	omap2_cm_write_mod_reg(cm_context.pll_cm_autoidle2, PLL_MOD,
			       CM_AUTOIDLE2);
	omap2_cm_write_mod_reg(cm_context.pll_cm_clksel4, PLL_MOD,
			       OMAP3430ES2_CM_CLKSEL4);
	omap2_cm_write_mod_reg(cm_context.pll_cm_clksel5, PLL_MOD,
			       OMAP3430ES2_CM_CLKSEL5);
	omap2_cm_write_mod_reg(cm_context.pll_cm_clken2, PLL_MOD,
			       OMAP3430ES2_CM_CLKEN2);
	__raw_writel(cm_context.cm_polctrl, OMAP3430_CM_POLCTRL);
	omap2_cm_write_mod_reg(cm_context.iva2_cm_fclken, OMAP3430_IVA2_MOD,
			       CM_FCLKEN);
	omap2_cm_write_mod_reg(cm_context.iva2_cm_clken_pll, OMAP3430_IVA2_MOD,
			       OMAP3430_CM_CLKEN_PLL);
	omap2_cm_write_mod_reg(cm_context.core_cm_fclken1, CORE_MOD,
			       CM_FCLKEN1);
	omap2_cm_write_mod_reg(cm_context.core_cm_fclken3, CORE_MOD,
			       OMAP3430ES2_CM_FCLKEN3);
	omap2_cm_write_mod_reg(cm_context.sgx_cm_fclken, OMAP3430ES2_SGX_MOD,
			       CM_FCLKEN);
	omap2_cm_write_mod_reg(cm_context.wkup_cm_fclken, WKUP_MOD, CM_FCLKEN);
	omap2_cm_write_mod_reg(cm_context.dss_cm_fclken, OMAP3430_DSS_MOD,
			       CM_FCLKEN);
	omap2_cm_write_mod_reg(cm_context.cam_cm_fclken, OMAP3430_CAM_MOD,
			       CM_FCLKEN);
	omap2_cm_write_mod_reg(cm_context.per_cm_fclken, OMAP3430_PER_MOD,
			       CM_FCLKEN);
	omap2_cm_write_mod_reg(cm_context.usbhost_cm_fclken,
			       OMAP3430ES2_USBHOST_MOD, CM_FCLKEN);
	omap2_cm_write_mod_reg(cm_context.core_cm_iclken1, CORE_MOD,
			       CM_ICLKEN1);
	omap2_cm_write_mod_reg(cm_context.core_cm_iclken2, CORE_MOD,
			       CM_ICLKEN2);
	omap2_cm_write_mod_reg(cm_context.core_cm_iclken3, CORE_MOD,
			       CM_ICLKEN3);
	omap2_cm_write_mod_reg(cm_context.sgx_cm_iclken, OMAP3430ES2_SGX_MOD,
			       CM_ICLKEN);
	omap2_cm_write_mod_reg(cm_context.wkup_cm_iclken, WKUP_MOD, CM_ICLKEN);
	omap2_cm_write_mod_reg(cm_context.dss_cm_iclken, OMAP3430_DSS_MOD,
			       CM_ICLKEN);
	omap2_cm_write_mod_reg(cm_context.cam_cm_iclken, OMAP3430_CAM_MOD,
			       CM_ICLKEN);
	omap2_cm_write_mod_reg(cm_context.per_cm_iclken, OMAP3430_PER_MOD,
			       CM_ICLKEN);
	omap2_cm_write_mod_reg(cm_context.usbhost_cm_iclken,
			       OMAP3430ES2_USBHOST_MOD, CM_ICLKEN);
	omap2_cm_write_mod_reg(cm_context.iva2_cm_autoidle2, OMAP3430_IVA2_MOD,
			       CM_AUTOIDLE2);
	omap2_cm_write_mod_reg(cm_context.mpu_cm_autoidle2, MPU_MOD,
			       CM_AUTOIDLE2);
	omap2_cm_write_mod_reg(cm_context.iva2_cm_clkstctrl, OMAP3430_IVA2_MOD,
			       OMAP2_CM_CLKSTCTRL);
	omap2_cm_write_mod_reg(cm_context.mpu_cm_clkstctrl, MPU_MOD,
			       OMAP2_CM_CLKSTCTRL);
	omap2_cm_write_mod_reg(cm_context.core_cm_clkstctrl, CORE_MOD,
			       OMAP2_CM_CLKSTCTRL);
	omap2_cm_write_mod_reg(cm_context.sgx_cm_clkstctrl, OMAP3430ES2_SGX_MOD,
			       OMAP2_CM_CLKSTCTRL);
	omap2_cm_write_mod_reg(cm_context.dss_cm_clkstctrl, OMAP3430_DSS_MOD,
			       OMAP2_CM_CLKSTCTRL);
	omap2_cm_write_mod_reg(cm_context.cam_cm_clkstctrl, OMAP3430_CAM_MOD,
			       OMAP2_CM_CLKSTCTRL);
	omap2_cm_write_mod_reg(cm_context.per_cm_clkstctrl, OMAP3430_PER_MOD,
			       OMAP2_CM_CLKSTCTRL);
	omap2_cm_write_mod_reg(cm_context.neon_cm_clkstctrl, OMAP3430_NEON_MOD,
			       OMAP2_CM_CLKSTCTRL);
	omap2_cm_write_mod_reg(cm_context.usbhost_cm_clkstctrl,
			       OMAP3430ES2_USBHOST_MOD, OMAP2_CM_CLKSTCTRL);
	omap2_cm_write_mod_reg(cm_context.core_cm_autoidle1, CORE_MOD,
			       CM_AUTOIDLE1);
	omap2_cm_write_mod_reg(cm_context.core_cm_autoidle2, CORE_MOD,
			       CM_AUTOIDLE2);
	omap2_cm_write_mod_reg(cm_context.core_cm_autoidle3, CORE_MOD,
			       CM_AUTOIDLE3);
	omap2_cm_write_mod_reg(cm_context.wkup_cm_autoidle, WKUP_MOD,
			       CM_AUTOIDLE);
	omap2_cm_write_mod_reg(cm_context.dss_cm_autoidle, OMAP3430_DSS_MOD,
			       CM_AUTOIDLE);
	omap2_cm_write_mod_reg(cm_context.cam_cm_autoidle, OMAP3430_CAM_MOD,
			       CM_AUTOIDLE);
	omap2_cm_write_mod_reg(cm_context.per_cm_autoidle, OMAP3430_PER_MOD,
			       CM_AUTOIDLE);
	omap2_cm_write_mod_reg(cm_context.usbhost_cm_autoidle,
			       OMAP3430ES2_USBHOST_MOD, CM_AUTOIDLE);
	omap2_cm_write_mod_reg(cm_context.sgx_cm_sleepdep, OMAP3430ES2_SGX_MOD,
			       OMAP3430_CM_SLEEPDEP);
	omap2_cm_write_mod_reg(cm_context.dss_cm_sleepdep, OMAP3430_DSS_MOD,
			       OMAP3430_CM_SLEEPDEP);
	omap2_cm_write_mod_reg(cm_context.cam_cm_sleepdep, OMAP3430_CAM_MOD,
			       OMAP3430_CM_SLEEPDEP);
	omap2_cm_write_mod_reg(cm_context.per_cm_sleepdep, OMAP3430_PER_MOD,
			       OMAP3430_CM_SLEEPDEP);
	omap2_cm_write_mod_reg(cm_context.usbhost_cm_sleepdep,
			       OMAP3430ES2_USBHOST_MOD, OMAP3430_CM_SLEEPDEP);
	omap2_cm_write_mod_reg(cm_context.cm_clkout_ctrl, OMAP3430_CCR_MOD,
			       OMAP3_CM_CLKOUT_CTRL_OFFSET);
}
#endif
Commit	Line	Data
71348bca PW	1	/*
	2	* OMAP2/3 CM module functions
	3	*
	4	* Copyright (C) 2009 Nokia Corporation
	5	* Paul Walmsley
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License version 2 as
	9	* published by the Free Software Foundation.
	10	*/
	11
	12	#include <linux/kernel.h>
71348bca PW	13	#include <linux/types.h>
	14	#include <linux/delay.h>
	15	#include <linux/spinlock.h>
	16	#include <linux/list.h>
	17	#include <linux/errno.h>
	18	#include <linux/err.h>
	19	#include <linux/io.h>
	20
6f8b7ff5 PW	21	#include <plat/common.h>
6f8b7ff5 PW	22
71348bca	23	#include "cm.h"
59fb659b	24	#include "cm2xxx_3xxx.h"
71348bca PW	25	#include "cm-regbits-24xx.h"
	26	#include "cm-regbits-34xx.h"
	27
71348bca PW	28	static const u8 cm_idlest_offs[] = {
	29	CM_IDLEST1, CM_IDLEST2, OMAP2430_CM_IDLEST3
	30	};
	31
c4d7e58f	32	u32 omap2_cm_read_mod_reg(s16 module, u16 idx)
59fb659b PW	33	{
	34	return __raw_readl(cm_base + module + idx);
	35	}
	36
c4d7e58f	37	void omap2_cm_write_mod_reg(u32 val, s16 module, u16 idx)
59fb659b PW	38	{
	39	__raw_writel(val, cm_base + module + idx);
	40	}
	41
	42	/* Read-modify-write a register in a CM module. Caller must lock */
c4d7e58f	43	u32 omap2_cm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx)
59fb659b PW	44	{
	45	u32 v;
	46
c4d7e58f	47	v = omap2_cm_read_mod_reg(module, idx);
59fb659b PW	48	v &= ~mask;
59fb659b PW	49	v \|= bits;
c4d7e58f	50	omap2_cm_write_mod_reg(v, module, idx);
59fb659b PW	51
	52	return v;
	53	}
	54
c4d7e58f	55	u32 omap2_cm_set_mod_reg_bits(u32 bits, s16 module, s16 idx)
59fb659b	56	{
c4d7e58f	57	return omap2_cm_rmw_mod_reg_bits(bits, bits, module, idx);
59fb659b PW	58	}
59fb659b PW	59
c4d7e58f	60	u32 omap2_cm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx)
59fb659b	61	{
c4d7e58f	62	return omap2_cm_rmw_mod_reg_bits(bits, 0x0, module, idx);
59fb659b PW	63	}
59fb659b PW	64
55ae3507 PW	65	/*
	66	*
	67	*/
	68
	69	static void _write_clktrctrl(u8 c, s16 module, u32 mask)
	70	{
	71	u32 v;
	72
	73	v = omap2_cm_read_mod_reg(module, OMAP2_CM_CLKSTCTRL);
	74	v &= ~mask;
	75	v \|= c << __ffs(mask);
	76	omap2_cm_write_mod_reg(v, module, OMAP2_CM_CLKSTCTRL);
	77	}
	78
	79	bool omap2_cm_is_clkdm_in_hwsup(s16 module, u32 mask)
	80	{
	81	u32 v;
	82	bool ret = 0;
	83
	84	BUG_ON(!cpu_is_omap24xx() && !cpu_is_omap34xx());
	85
	86	v = omap2_cm_read_mod_reg(module, OMAP2_CM_CLKSTCTRL);
	87	v &= mask;
	88	v >>= __ffs(mask);
	89
	90	if (cpu_is_omap24xx())
	91	ret = (v == OMAP24XX_CLKSTCTRL_ENABLE_AUTO) ? 1 : 0;
	92	else
	93	ret = (v == OMAP34XX_CLKSTCTRL_ENABLE_AUTO) ? 1 : 0;
	94
	95	return ret;
	96	}
	97
	98	void omap2xxx_cm_clkdm_enable_hwsup(s16 module, u32 mask)
	99	{
	100	_write_clktrctrl(OMAP24XX_CLKSTCTRL_ENABLE_AUTO, module, mask);
	101	}
	102
	103	void omap2xxx_cm_clkdm_disable_hwsup(s16 module, u32 mask)
	104	{
	105	_write_clktrctrl(OMAP24XX_CLKSTCTRL_DISABLE_AUTO, module, mask);
	106	}
	107
	108	void omap3xxx_cm_clkdm_enable_hwsup(s16 module, u32 mask)
	109	{
	110	_write_clktrctrl(OMAP34XX_CLKSTCTRL_ENABLE_AUTO, module, mask);
	111	}
	112
	113	void omap3xxx_cm_clkdm_disable_hwsup(s16 module, u32 mask)
	114	{
	115	_write_clktrctrl(OMAP34XX_CLKSTCTRL_DISABLE_AUTO, module, mask);
	116	}
	117
	118	void omap3xxx_cm_clkdm_force_sleep(s16 module, u32 mask)
	119	{
	120	_write_clktrctrl(OMAP34XX_CLKSTCTRL_FORCE_SLEEP, module, mask);
	121	}
	122
	123	void omap3xxx_cm_clkdm_force_wakeup(s16 module, u32 mask)
	124	{
	125	_write_clktrctrl(OMAP34XX_CLKSTCTRL_FORCE_WAKEUP, module, mask);
	126	}
	127
	128
129	/*
130	*
131	*/
132
71348bca PW	133	/**
	134	* omap2_cm_wait_idlest_ready - wait for a module to leave idle or standby
	135	* @prcm_mod: PRCM module offset
	136	* @idlest_id: CM_IDLESTx register ID (i.e., x = 1, 2, 3)
	137	* @idlest_shift: shift of the bit in the CM_IDLEST* register to check
	138	*
	139	* XXX document
	140	*/
	141	int omap2_cm_wait_module_ready(s16 prcm_mod, u8 idlest_id, u8 idlest_shift)
	142	{
	143	int ena = 0, i = 0;
	144	u8 cm_idlest_reg;
	145	u32 mask;
	146
	147	if (!idlest_id \|\| (idlest_id > ARRAY_SIZE(cm_idlest_offs)))
	148	return -EINVAL;
	149
	150	cm_idlest_reg = cm_idlest_offs[idlest_id - 1];
	151
64056167 KH	152	mask = 1 << idlest_shift;
64056167 KH	153
71348bca	154	if (cpu_is_omap24xx())
64056167	155	ena = mask;
71348bca PW	156	else if (cpu_is_omap34xx())
	157	ena = 0;
	158	else
	159	BUG();
	160
c4d7e58f	161	omap_test_timeout(((omap2_cm_read_mod_reg(prcm_mod, cm_idlest_reg) & mask) == ena),
6f8b7ff5	162	MAX_MODULE_READY_TIME, i);
71348bca PW	163
	164	return (i < MAX_MODULE_READY_TIME) ? 0 : -EBUSY;
	165	}
	166
f0611a5c PW	167	/*
	168	* Context save/restore code - OMAP3 only
	169	*/
	170	#ifdef CONFIG_ARCH_OMAP3
	171	struct omap3_cm_regs {
	172	u32 iva2_cm_clksel1;
	173	u32 iva2_cm_clksel2;
	174	u32 cm_sysconfig;
	175	u32 sgx_cm_clksel;
	176	u32 dss_cm_clksel;
	177	u32 cam_cm_clksel;
	178	u32 per_cm_clksel;
	179	u32 emu_cm_clksel;
	180	u32 emu_cm_clkstctrl;
	181	u32 pll_cm_autoidle2;
	182	u32 pll_cm_clksel4;
	183	u32 pll_cm_clksel5;
	184	u32 pll_cm_clken2;
	185	u32 cm_polctrl;
	186	u32 iva2_cm_fclken;
	187	u32 iva2_cm_clken_pll;
	188	u32 core_cm_fclken1;
	189	u32 core_cm_fclken3;
	190	u32 sgx_cm_fclken;
	191	u32 wkup_cm_fclken;
	192	u32 dss_cm_fclken;
	193	u32 cam_cm_fclken;
	194	u32 per_cm_fclken;
	195	u32 usbhost_cm_fclken;
	196	u32 core_cm_iclken1;
	197	u32 core_cm_iclken2;
	198	u32 core_cm_iclken3;
	199	u32 sgx_cm_iclken;
	200	u32 wkup_cm_iclken;
	201	u32 dss_cm_iclken;
	202	u32 cam_cm_iclken;
	203	u32 per_cm_iclken;
	204	u32 usbhost_cm_iclken;
	205	u32 iva2_cm_autoidle2;
	206	u32 mpu_cm_autoidle2;
	207	u32 iva2_cm_clkstctrl;
	208	u32 mpu_cm_clkstctrl;
	209	u32 core_cm_clkstctrl;
	210	u32 sgx_cm_clkstctrl;
	211	u32 dss_cm_clkstctrl;
	212	u32 cam_cm_clkstctrl;
	213	u32 per_cm_clkstctrl;
	214	u32 neon_cm_clkstctrl;
	215	u32 usbhost_cm_clkstctrl;
	216	u32 core_cm_autoidle1;
	217	u32 core_cm_autoidle2;
	218	u32 core_cm_autoidle3;
	219	u32 wkup_cm_autoidle;
	220	u32 dss_cm_autoidle;
	221	u32 cam_cm_autoidle;
	222	u32 per_cm_autoidle;
	223	u32 usbhost_cm_autoidle;
	224	u32 sgx_cm_sleepdep;
	225	u32 dss_cm_sleepdep;
	226	u32 cam_cm_sleepdep;
	227	u32 per_cm_sleepdep;
	228	u32 usbhost_cm_sleepdep;
	229	u32 cm_clkout_ctrl;
	230	};
231
232	static struct omap3_cm_regs cm_context;
233
234	void omap3_cm_save_context(void)
235	{
236	cm_context.iva2_cm_clksel1 =
c4d7e58f	237	omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_CLKSEL1);
f0611a5c	238	cm_context.iva2_cm_clksel2 =
c4d7e58f	239	omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_CLKSEL2);
f0611a5c PW	240	cm_context.cm_sysconfig = __raw_readl(OMAP3430_CM_SYSCONFIG);
f0611a5c PW	241	cm_context.sgx_cm_clksel =
c4d7e58f	242	omap2_cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_CLKSEL);
f0611a5c	243	cm_context.dss_cm_clksel =
c4d7e58f	244	omap2_cm_read_mod_reg(OMAP3430_DSS_MOD, CM_CLKSEL);
f0611a5c	245	cm_context.cam_cm_clksel =
c4d7e58f	246	omap2_cm_read_mod_reg(OMAP3430_CAM_MOD, CM_CLKSEL);
f0611a5c	247	cm_context.per_cm_clksel =
c4d7e58f	248	omap2_cm_read_mod_reg(OMAP3430_PER_MOD, CM_CLKSEL);
f0611a5c	249	cm_context.emu_cm_clksel =
c4d7e58f	250	omap2_cm_read_mod_reg(OMAP3430_EMU_MOD, CM_CLKSEL1);
f0611a5c	251	cm_context.emu_cm_clkstctrl =
c4d7e58f	252	omap2_cm_read_mod_reg(OMAP3430_EMU_MOD, OMAP2_CM_CLKSTCTRL);
f0611a5c	253	cm_context.pll_cm_autoidle2 =
c4d7e58f	254	omap2_cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE2);
f0611a5c	255	cm_context.pll_cm_clksel4 =
c4d7e58f	256	omap2_cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKSEL4);
f0611a5c	257	cm_context.pll_cm_clksel5 =
c4d7e58f	258	omap2_cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKSEL5);
f0611a5c	259	cm_context.pll_cm_clken2 =
c4d7e58f	260	omap2_cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKEN2);
f0611a5c PW	261	cm_context.cm_polctrl = __raw_readl(OMAP3430_CM_POLCTRL);
f0611a5c PW	262	cm_context.iva2_cm_fclken =
c4d7e58f PW	263	omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_FCLKEN);
	264	cm_context.iva2_cm_clken_pll =
	265	omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKEN_PLL);
f0611a5c	266	cm_context.core_cm_fclken1 =
c4d7e58f	267	omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
f0611a5c	268	cm_context.core_cm_fclken3 =
c4d7e58f	269	omap2_cm_read_mod_reg(CORE_MOD, OMAP3430ES2_CM_FCLKEN3);
f0611a5c	270	cm_context.sgx_cm_fclken =
c4d7e58f	271	omap2_cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_FCLKEN);
f0611a5c	272	cm_context.wkup_cm_fclken =
c4d7e58f	273	omap2_cm_read_mod_reg(WKUP_MOD, CM_FCLKEN);
f0611a5c	274	cm_context.dss_cm_fclken =
c4d7e58f	275	omap2_cm_read_mod_reg(OMAP3430_DSS_MOD, CM_FCLKEN);
f0611a5c	276	cm_context.cam_cm_fclken =
c4d7e58f	277	omap2_cm_read_mod_reg(OMAP3430_CAM_MOD, CM_FCLKEN);
f0611a5c	278	cm_context.per_cm_fclken =
c4d7e58f	279	omap2_cm_read_mod_reg(OMAP3430_PER_MOD, CM_FCLKEN);
f0611a5c	280	cm_context.usbhost_cm_fclken =
c4d7e58f	281	omap2_cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN);
f0611a5c	282	cm_context.core_cm_iclken1 =
c4d7e58f	283	omap2_cm_read_mod_reg(CORE_MOD, CM_ICLKEN1);
f0611a5c	284	cm_context.core_cm_iclken2 =
c4d7e58f	285	omap2_cm_read_mod_reg(CORE_MOD, CM_ICLKEN2);
f0611a5c	286	cm_context.core_cm_iclken3 =
c4d7e58f	287	omap2_cm_read_mod_reg(CORE_MOD, CM_ICLKEN3);
f0611a5c	288	cm_context.sgx_cm_iclken =
c4d7e58f	289	omap2_cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_ICLKEN);
f0611a5c	290	cm_context.wkup_cm_iclken =
c4d7e58f	291	omap2_cm_read_mod_reg(WKUP_MOD, CM_ICLKEN);
f0611a5c	292	cm_context.dss_cm_iclken =
c4d7e58f	293	omap2_cm_read_mod_reg(OMAP3430_DSS_MOD, CM_ICLKEN);
f0611a5c	294	cm_context.cam_cm_iclken =
c4d7e58f	295	omap2_cm_read_mod_reg(OMAP3430_CAM_MOD, CM_ICLKEN);
f0611a5c	296	cm_context.per_cm_iclken =
c4d7e58f	297	omap2_cm_read_mod_reg(OMAP3430_PER_MOD, CM_ICLKEN);
f0611a5c	298	cm_context.usbhost_cm_iclken =
c4d7e58f	299	omap2_cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN);
f0611a5c	300	cm_context.iva2_cm_autoidle2 =
c4d7e58f	301	omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_AUTOIDLE2);
f0611a5c	302	cm_context.mpu_cm_autoidle2 =
c4d7e58f	303	omap2_cm_read_mod_reg(MPU_MOD, CM_AUTOIDLE2);
f0611a5c	304	cm_context.iva2_cm_clkstctrl =
c4d7e58f	305	omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP2_CM_CLKSTCTRL);
f0611a5c	306	cm_context.mpu_cm_clkstctrl =
c4d7e58f	307	omap2_cm_read_mod_reg(MPU_MOD, OMAP2_CM_CLKSTCTRL);
f0611a5c	308	cm_context.core_cm_clkstctrl =
c4d7e58f	309	omap2_cm_read_mod_reg(CORE_MOD, OMAP2_CM_CLKSTCTRL);
f0611a5c	310	cm_context.sgx_cm_clkstctrl =
c4d7e58f	311	omap2_cm_read_mod_reg(OMAP3430ES2_SGX_MOD, OMAP2_CM_CLKSTCTRL);
f0611a5c	312	cm_context.dss_cm_clkstctrl =
c4d7e58f	313	omap2_cm_read_mod_reg(OMAP3430_DSS_MOD, OMAP2_CM_CLKSTCTRL);
f0611a5c	314	cm_context.cam_cm_clkstctrl =
c4d7e58f	315	omap2_cm_read_mod_reg(OMAP3430_CAM_MOD, OMAP2_CM_CLKSTCTRL);
f0611a5c	316	cm_context.per_cm_clkstctrl =
c4d7e58f	317	omap2_cm_read_mod_reg(OMAP3430_PER_MOD, OMAP2_CM_CLKSTCTRL);
f0611a5c	318	cm_context.neon_cm_clkstctrl =
c4d7e58f	319	omap2_cm_read_mod_reg(OMAP3430_NEON_MOD, OMAP2_CM_CLKSTCTRL);
f0611a5c	320	cm_context.usbhost_cm_clkstctrl =
c4d7e58f PW	321	omap2_cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD,
c4d7e58f PW	322	OMAP2_CM_CLKSTCTRL);
f0611a5c	323	cm_context.core_cm_autoidle1 =
c4d7e58f	324	omap2_cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE1);
f0611a5c	325	cm_context.core_cm_autoidle2 =
c4d7e58f	326	omap2_cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE2);
f0611a5c	327	cm_context.core_cm_autoidle3 =
c4d7e58f	328	omap2_cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE3);
f0611a5c	329	cm_context.wkup_cm_autoidle =
c4d7e58f	330	omap2_cm_read_mod_reg(WKUP_MOD, CM_AUTOIDLE);
f0611a5c	331	cm_context.dss_cm_autoidle =
c4d7e58f	332	omap2_cm_read_mod_reg(OMAP3430_DSS_MOD, CM_AUTOIDLE);
f0611a5c	333	cm_context.cam_cm_autoidle =
c4d7e58f	334	omap2_cm_read_mod_reg(OMAP3430_CAM_MOD, CM_AUTOIDLE);
f0611a5c	335	cm_context.per_cm_autoidle =
c4d7e58f	336	omap2_cm_read_mod_reg(OMAP3430_PER_MOD, CM_AUTOIDLE);
f0611a5c	337	cm_context.usbhost_cm_autoidle =
c4d7e58f	338	omap2_cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_AUTOIDLE);
f0611a5c	339	cm_context.sgx_cm_sleepdep =
c4d7e58f PW	340	omap2_cm_read_mod_reg(OMAP3430ES2_SGX_MOD,
c4d7e58f PW	341	OMAP3430_CM_SLEEPDEP);
f0611a5c	342	cm_context.dss_cm_sleepdep =
c4d7e58f	343	omap2_cm_read_mod_reg(OMAP3430_DSS_MOD, OMAP3430_CM_SLEEPDEP);
f0611a5c	344	cm_context.cam_cm_sleepdep =
c4d7e58f	345	omap2_cm_read_mod_reg(OMAP3430_CAM_MOD, OMAP3430_CM_SLEEPDEP);
f0611a5c	346	cm_context.per_cm_sleepdep =
c4d7e58f	347	omap2_cm_read_mod_reg(OMAP3430_PER_MOD, OMAP3430_CM_SLEEPDEP);
f0611a5c	348	cm_context.usbhost_cm_sleepdep =
c4d7e58f PW	349	omap2_cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD,
c4d7e58f PW	350	OMAP3430_CM_SLEEPDEP);
f0611a5c	351	cm_context.cm_clkout_ctrl =
c4d7e58f PW	352	omap2_cm_read_mod_reg(OMAP3430_CCR_MOD,
c4d7e58f PW	353	OMAP3_CM_CLKOUT_CTRL_OFFSET);
f0611a5c PW	354	}
	355
	356	void omap3_cm_restore_context(void)
	357	{
c4d7e58f PW	358	omap2_cm_write_mod_reg(cm_context.iva2_cm_clksel1, OMAP3430_IVA2_MOD,
	359	CM_CLKSEL1);
	360	omap2_cm_write_mod_reg(cm_context.iva2_cm_clksel2, OMAP3430_IVA2_MOD,
	361	CM_CLKSEL2);
f0611a5c	362	__raw_writel(cm_context.cm_sysconfig, OMAP3430_CM_SYSCONFIG);
c4d7e58f PW	363	omap2_cm_write_mod_reg(cm_context.sgx_cm_clksel, OMAP3430ES2_SGX_MOD,
	364	CM_CLKSEL);
	365	omap2_cm_write_mod_reg(cm_context.dss_cm_clksel, OMAP3430_DSS_MOD,
	366	CM_CLKSEL);
	367	omap2_cm_write_mod_reg(cm_context.cam_cm_clksel, OMAP3430_CAM_MOD,
	368	CM_CLKSEL);
	369	omap2_cm_write_mod_reg(cm_context.per_cm_clksel, OMAP3430_PER_MOD,
	370	CM_CLKSEL);
	371	omap2_cm_write_mod_reg(cm_context.emu_cm_clksel, OMAP3430_EMU_MOD,
	372	CM_CLKSEL1);
	373	omap2_cm_write_mod_reg(cm_context.emu_cm_clkstctrl, OMAP3430_EMU_MOD,
	374	OMAP2_CM_CLKSTCTRL);
	375	omap2_cm_write_mod_reg(cm_context.pll_cm_autoidle2, PLL_MOD,
	376	CM_AUTOIDLE2);
	377	omap2_cm_write_mod_reg(cm_context.pll_cm_clksel4, PLL_MOD,
	378	OMAP3430ES2_CM_CLKSEL4);
	379	omap2_cm_write_mod_reg(cm_context.pll_cm_clksel5, PLL_MOD,
	380	OMAP3430ES2_CM_CLKSEL5);
	381	omap2_cm_write_mod_reg(cm_context.pll_cm_clken2, PLL_MOD,
	382	OMAP3430ES2_CM_CLKEN2);
f0611a5c	383	__raw_writel(cm_context.cm_polctrl, OMAP3430_CM_POLCTRL);
c4d7e58f PW	384	omap2_cm_write_mod_reg(cm_context.iva2_cm_fclken, OMAP3430_IVA2_MOD,
	385	CM_FCLKEN);
	386	omap2_cm_write_mod_reg(cm_context.iva2_cm_clken_pll, OMAP3430_IVA2_MOD,
	387	OMAP3430_CM_CLKEN_PLL);
	388	omap2_cm_write_mod_reg(cm_context.core_cm_fclken1, CORE_MOD,
	389	CM_FCLKEN1);
	390	omap2_cm_write_mod_reg(cm_context.core_cm_fclken3, CORE_MOD,
	391	OMAP3430ES2_CM_FCLKEN3);
	392	omap2_cm_write_mod_reg(cm_context.sgx_cm_fclken, OMAP3430ES2_SGX_MOD,
	393	CM_FCLKEN);
	394	omap2_cm_write_mod_reg(cm_context.wkup_cm_fclken, WKUP_MOD, CM_FCLKEN);
	395	omap2_cm_write_mod_reg(cm_context.dss_cm_fclken, OMAP3430_DSS_MOD,
	396	CM_FCLKEN);
	397	omap2_cm_write_mod_reg(cm_context.cam_cm_fclken, OMAP3430_CAM_MOD,
	398	CM_FCLKEN);
	399	omap2_cm_write_mod_reg(cm_context.per_cm_fclken, OMAP3430_PER_MOD,
	400	CM_FCLKEN);
	401	omap2_cm_write_mod_reg(cm_context.usbhost_cm_fclken,
	402	OMAP3430ES2_USBHOST_MOD, CM_FCLKEN);
	403	omap2_cm_write_mod_reg(cm_context.core_cm_iclken1, CORE_MOD,
	404	CM_ICLKEN1);
	405	omap2_cm_write_mod_reg(cm_context.core_cm_iclken2, CORE_MOD,
	406	CM_ICLKEN2);
	407	omap2_cm_write_mod_reg(cm_context.core_cm_iclken3, CORE_MOD,
	408	CM_ICLKEN3);
	409	omap2_cm_write_mod_reg(cm_context.sgx_cm_iclken, OMAP3430ES2_SGX_MOD,
	410	CM_ICLKEN);
	411	omap2_cm_write_mod_reg(cm_context.wkup_cm_iclken, WKUP_MOD, CM_ICLKEN);
	412	omap2_cm_write_mod_reg(cm_context.dss_cm_iclken, OMAP3430_DSS_MOD,
	413	CM_ICLKEN);
	414	omap2_cm_write_mod_reg(cm_context.cam_cm_iclken, OMAP3430_CAM_MOD,
	415	CM_ICLKEN);
	416	omap2_cm_write_mod_reg(cm_context.per_cm_iclken, OMAP3430_PER_MOD,
	417	CM_ICLKEN);
	418	omap2_cm_write_mod_reg(cm_context.usbhost_cm_iclken,
	419	OMAP3430ES2_USBHOST_MOD, CM_ICLKEN);
	420	omap2_cm_write_mod_reg(cm_context.iva2_cm_autoidle2, OMAP3430_IVA2_MOD,
	421	CM_AUTOIDLE2);
	422	omap2_cm_write_mod_reg(cm_context.mpu_cm_autoidle2, MPU_MOD,
	423	CM_AUTOIDLE2);
	424	omap2_cm_write_mod_reg(cm_context.iva2_cm_clkstctrl, OMAP3430_IVA2_MOD,
	425	OMAP2_CM_CLKSTCTRL);
	426	omap2_cm_write_mod_reg(cm_context.mpu_cm_clkstctrl, MPU_MOD,
	427	OMAP2_CM_CLKSTCTRL);
	428	omap2_cm_write_mod_reg(cm_context.core_cm_clkstctrl, CORE_MOD,
	429	OMAP2_CM_CLKSTCTRL);
	430	omap2_cm_write_mod_reg(cm_context.sgx_cm_clkstctrl, OMAP3430ES2_SGX_MOD,
	431	OMAP2_CM_CLKSTCTRL);
	432	omap2_cm_write_mod_reg(cm_context.dss_cm_clkstctrl, OMAP3430_DSS_MOD,
	433	OMAP2_CM_CLKSTCTRL);
	434	omap2_cm_write_mod_reg(cm_context.cam_cm_clkstctrl, OMAP3430_CAM_MOD,
	435	OMAP2_CM_CLKSTCTRL);
	436	omap2_cm_write_mod_reg(cm_context.per_cm_clkstctrl, OMAP3430_PER_MOD,
	437	OMAP2_CM_CLKSTCTRL);
	438	omap2_cm_write_mod_reg(cm_context.neon_cm_clkstctrl, OMAP3430_NEON_MOD,
	439	OMAP2_CM_CLKSTCTRL);
	440	omap2_cm_write_mod_reg(cm_context.usbhost_cm_clkstctrl,
	441	OMAP3430ES2_USBHOST_MOD, OMAP2_CM_CLKSTCTRL);
	442	omap2_cm_write_mod_reg(cm_context.core_cm_autoidle1, CORE_MOD,
	443	CM_AUTOIDLE1);
	444	omap2_cm_write_mod_reg(cm_context.core_cm_autoidle2, CORE_MOD,
	445	CM_AUTOIDLE2);
	446	omap2_cm_write_mod_reg(cm_context.core_cm_autoidle3, CORE_MOD,
	447	CM_AUTOIDLE3);
448	omap2_cm_write_mod_reg(cm_context.wkup_cm_autoidle, WKUP_MOD,
449	CM_AUTOIDLE);
450	omap2_cm_write_mod_reg(cm_context.dss_cm_autoidle, OMAP3430_DSS_MOD,
451	CM_AUTOIDLE);
452	omap2_cm_write_mod_reg(cm_context.cam_cm_autoidle, OMAP3430_CAM_MOD,
453	CM_AUTOIDLE);
454	omap2_cm_write_mod_reg(cm_context.per_cm_autoidle, OMAP3430_PER_MOD,
455	CM_AUTOIDLE);
456	omap2_cm_write_mod_reg(cm_context.usbhost_cm_autoidle,
457	OMAP3430ES2_USBHOST_MOD, CM_AUTOIDLE);
458	omap2_cm_write_mod_reg(cm_context.sgx_cm_sleepdep, OMAP3430ES2_SGX_MOD,
459	OMAP3430_CM_SLEEPDEP);
460	omap2_cm_write_mod_reg(cm_context.dss_cm_sleepdep, OMAP3430_DSS_MOD,
461	OMAP3430_CM_SLEEPDEP);
462	omap2_cm_write_mod_reg(cm_context.cam_cm_sleepdep, OMAP3430_CAM_MOD,
463	OMAP3430_CM_SLEEPDEP);
464	omap2_cm_write_mod_reg(cm_context.per_cm_sleepdep, OMAP3430_PER_MOD,
465	OMAP3430_CM_SLEEPDEP);
466	omap2_cm_write_mod_reg(cm_context.usbhost_cm_sleepdep,
467	OMAP3430ES2_USBHOST_MOD, OMAP3430_CM_SLEEPDEP);
468	omap2_cm_write_mod_reg(cm_context.cm_clkout_ctrl, OMAP3430_CCR_MOD,
469	OMAP3_CM_CLKOUT_CTRL_OFFSET);
f0611a5c PW	470	}
f0611a5c PW	471	#endif