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1 | /* |
2 | * OMAP2/3 Clock Management (CM) register definitions | |
3 | * | |
4 | * Copyright (C) 2007-2009 Texas Instruments, Inc. | |
5 | * Copyright (C) 2007-2010 Nokia Corporation | |
6 | * Paul Walmsley | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | * | |
12 | * The CM hardware modules on the OMAP2/3 are quite similar to each | |
13 | * other. The CM modules/instances on OMAP4 are quite different, so | |
14 | * they are handled in a separate file. | |
15 | */ | |
16 | #ifndef __ARCH_ASM_MACH_OMAP2_CM2XXX_3XXX_H | |
17 | #define __ARCH_ASM_MACH_OMAP2_CM2XXX_3XXX_H | |
18 | ||
d9a16f9a | 19 | #include "cm.h" |
59fb659b | 20 | |
59fb659b PW |
21 | /* |
22 | * Module specific CM register offsets from CM_BASE + domain offset | |
23 | * Use cm_{read,write}_mod_reg() with these registers. | |
24 | * These register offsets generally appear in more than one PRCM submodule. | |
25 | */ | |
26 | ||
27 | /* Common between OMAP2 and OMAP3 */ | |
28 | ||
29 | #define CM_FCLKEN 0x0000 | |
30 | #define CM_FCLKEN1 CM_FCLKEN | |
31 | #define CM_CLKEN CM_FCLKEN | |
32 | #define CM_ICLKEN 0x0010 | |
33 | #define CM_ICLKEN1 CM_ICLKEN | |
34 | #define CM_ICLKEN2 0x0014 | |
35 | #define CM_ICLKEN3 0x0018 | |
36 | #define CM_IDLEST 0x0020 | |
37 | #define CM_IDLEST1 CM_IDLEST | |
38 | #define CM_IDLEST2 0x0024 | |
ff4ae5d9 | 39 | #define OMAP2430_CM_IDLEST3 0x0028 |
59fb659b PW |
40 | #define CM_AUTOIDLE 0x0030 |
41 | #define CM_AUTOIDLE1 CM_AUTOIDLE | |
42 | #define CM_AUTOIDLE2 0x0034 | |
43 | #define CM_AUTOIDLE3 0x0038 | |
44 | #define CM_CLKSEL 0x0040 | |
45 | #define CM_CLKSEL1 CM_CLKSEL | |
46 | #define CM_CLKSEL2 0x0044 | |
47 | #define OMAP2_CM_CLKSTCTRL 0x0048 | |
48 | ||
ff4ae5d9 | 49 | #ifndef __ASSEMBLER__ |
59fb659b | 50 | |
ff4ae5d9 | 51 | #include <linux/io.h> |
59fb659b | 52 | |
ff4ae5d9 PW |
53 | static inline u32 omap2_cm_read_mod_reg(s16 module, u16 idx) |
54 | { | |
55 | return __raw_readl(cm_base + module + idx); | |
56 | } | |
59fb659b | 57 | |
ff4ae5d9 PW |
58 | static inline void omap2_cm_write_mod_reg(u32 val, s16 module, u16 idx) |
59 | { | |
60 | __raw_writel(val, cm_base + module + idx); | |
61 | } | |
59fb659b | 62 | |
ff4ae5d9 PW |
63 | /* Read-modify-write a register in a CM module. Caller must lock */ |
64 | static inline u32 omap2_cm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, | |
65 | s16 idx) | |
66 | { | |
67 | u32 v; | |
59fb659b | 68 | |
ff4ae5d9 PW |
69 | v = omap2_cm_read_mod_reg(module, idx); |
70 | v &= ~mask; | |
71 | v |= bits; | |
72 | omap2_cm_write_mod_reg(v, module, idx); | |
59fb659b | 73 | |
ff4ae5d9 PW |
74 | return v; |
75 | } | |
55ae3507 | 76 | |
4bd5259e PW |
77 | /* Read a CM register, AND it, and shift the result down to bit 0 */ |
78 | static inline u32 omap2_cm_read_mod_bits_shift(s16 domain, s16 idx, u32 mask) | |
79 | { | |
80 | u32 v; | |
81 | ||
82 | v = omap2_cm_read_mod_reg(domain, idx); | |
83 | v &= mask; | |
84 | v >>= __ffs(mask); | |
85 | ||
86 | return v; | |
87 | } | |
88 | ||
ff4ae5d9 PW |
89 | static inline u32 omap2_cm_set_mod_reg_bits(u32 bits, s16 module, s16 idx) |
90 | { | |
91 | return omap2_cm_rmw_mod_reg_bits(bits, bits, module, idx); | |
92 | } | |
55ae3507 | 93 | |
ff4ae5d9 PW |
94 | static inline u32 omap2_cm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx) |
95 | { | |
96 | return omap2_cm_rmw_mod_reg_bits(bits, 0x0, module, idx); | |
97 | } | |
92618ff8 | 98 | |
b6ffa050 PW |
99 | extern int omap2xxx_cm_apll54_enable(void); |
100 | extern void omap2xxx_cm_apll54_disable(void); | |
101 | extern int omap2xxx_cm_apll96_enable(void); | |
102 | extern void omap2xxx_cm_apll96_disable(void); | |
103 | ||
59fb659b PW |
104 | #endif |
105 | ||
106 | /* CM register bits shared between 24XX and 3430 */ | |
107 | ||
108 | /* CM_CLKSEL_GFX */ | |
109 | #define OMAP_CLKSEL_GFX_SHIFT 0 | |
110 | #define OMAP_CLKSEL_GFX_MASK (0x7 << 0) | |
99e7938d | 111 | #define OMAP_CLKSEL_GFX_WIDTH 3 |
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112 | |
113 | /* CM_ICLKEN_GFX */ | |
114 | #define OMAP_EN_GFX_SHIFT 0 | |
115 | #define OMAP_EN_GFX_MASK (1 << 0) | |
116 | ||
117 | /* CM_IDLEST_GFX */ | |
118 | #define OMAP_ST_GFX_MASK (1 << 0) | |
119 | ||
120 | #endif |