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f969a6dc VH |
1 | /* |
2 | * AM33XX CM offset macros | |
3 | * | |
4 | * Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/ | |
5 | * Vaibhav Hiremath <hvaibhav@ti.com> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU General Public License as | |
9 | * published by the Free Software Foundation version 2. | |
10 | * | |
11 | * This program is distributed "as is" WITHOUT ANY WARRANTY of any | |
12 | * kind, whether express or implied; without even the implied warranty | |
13 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | */ | |
16 | ||
17 | #ifndef __ARCH_ARM_MACH_OMAP2_CM_33XX_H | |
18 | #define __ARCH_ARM_MACH_OMAP2_CM_33XX_H | |
19 | ||
f969a6dc VH |
20 | #include "cm.h" |
21 | #include "cm-regbits-33xx.h" | |
425dc8b2 | 22 | #include "prcm-common.h" |
f969a6dc VH |
23 | |
24 | /* CM base address */ | |
25 | #define AM33XX_CM_BASE 0x44e00000 | |
26 | ||
27 | #define AM33XX_CM_REGADDR(inst, reg) \ | |
28 | AM33XX_L4_WK_IO_ADDRESS(AM33XX_CM_BASE + (inst) + (reg)) | |
29 | ||
30 | /* CM instances */ | |
31 | #define AM33XX_CM_PER_MOD 0x0000 | |
32 | #define AM33XX_CM_WKUP_MOD 0x0400 | |
33 | #define AM33XX_CM_DPLL_MOD 0x0500 | |
34 | #define AM33XX_CM_MPU_MOD 0x0600 | |
35 | #define AM33XX_CM_DEVICE_MOD 0x0700 | |
36 | #define AM33XX_CM_RTC_MOD 0x0800 | |
37 | #define AM33XX_CM_GFX_MOD 0x0900 | |
38 | #define AM33XX_CM_CEFUSE_MOD 0x0A00 | |
39 | ||
40 | /* CM */ | |
41 | ||
42 | /* CM.PER_CM register offsets */ | |
43 | #define AM33XX_CM_PER_L4LS_CLKSTCTRL_OFFSET 0x0000 | |
44 | #define AM33XX_CM_PER_L4LS_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0000) | |
45 | #define AM33XX_CM_PER_L3S_CLKSTCTRL_OFFSET 0x0004 | |
46 | #define AM33XX_CM_PER_L3S_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0004) | |
47 | #define AM33XX_CM_PER_L4FW_CLKSTCTRL_OFFSET 0x0008 | |
48 | #define AM33XX_CM_PER_L4FW_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0008) | |
49 | #define AM33XX_CM_PER_L3_CLKSTCTRL_OFFSET 0x000c | |
50 | #define AM33XX_CM_PER_L3_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x000c) | |
51 | #define AM33XX_CM_PER_CPGMAC0_CLKCTRL_OFFSET 0x0014 | |
52 | #define AM33XX_CM_PER_CPGMAC0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0014) | |
53 | #define AM33XX_CM_PER_LCDC_CLKCTRL_OFFSET 0x0018 | |
54 | #define AM33XX_CM_PER_LCDC_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0018) | |
55 | #define AM33XX_CM_PER_USB0_CLKCTRL_OFFSET 0x001c | |
56 | #define AM33XX_CM_PER_USB0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x001c) | |
57 | #define AM33XX_CM_PER_MLB_CLKCTRL_OFFSET 0x0020 | |
58 | #define AM33XX_CM_PER_MLB_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0020) | |
59 | #define AM33XX_CM_PER_TPTC0_CLKCTRL_OFFSET 0x0024 | |
60 | #define AM33XX_CM_PER_TPTC0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0024) | |
61 | #define AM33XX_CM_PER_EMIF_CLKCTRL_OFFSET 0x0028 | |
62 | #define AM33XX_CM_PER_EMIF_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0028) | |
63 | #define AM33XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET 0x002c | |
64 | #define AM33XX_CM_PER_OCMCRAM_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x002c) | |
65 | #define AM33XX_CM_PER_GPMC_CLKCTRL_OFFSET 0x0030 | |
66 | #define AM33XX_CM_PER_GPMC_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0030) | |
67 | #define AM33XX_CM_PER_MCASP0_CLKCTRL_OFFSET 0x0034 | |
68 | #define AM33XX_CM_PER_MCASP0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0034) | |
69 | #define AM33XX_CM_PER_UART5_CLKCTRL_OFFSET 0x0038 | |
70 | #define AM33XX_CM_PER_UART5_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0038) | |
71 | #define AM33XX_CM_PER_MMC0_CLKCTRL_OFFSET 0x003c | |
72 | #define AM33XX_CM_PER_MMC0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x003c) | |
73 | #define AM33XX_CM_PER_ELM_CLKCTRL_OFFSET 0x0040 | |
74 | #define AM33XX_CM_PER_ELM_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0040) | |
75 | #define AM33XX_CM_PER_I2C2_CLKCTRL_OFFSET 0x0044 | |
76 | #define AM33XX_CM_PER_I2C2_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0044) | |
77 | #define AM33XX_CM_PER_I2C1_CLKCTRL_OFFSET 0x0048 | |
78 | #define AM33XX_CM_PER_I2C1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0048) | |
79 | #define AM33XX_CM_PER_SPI0_CLKCTRL_OFFSET 0x004c | |
80 | #define AM33XX_CM_PER_SPI0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x004c) | |
81 | #define AM33XX_CM_PER_SPI1_CLKCTRL_OFFSET 0x0050 | |
82 | #define AM33XX_CM_PER_SPI1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0050) | |
83 | #define AM33XX_CM_PER_SPI2_CLKCTRL_OFFSET 0x0054 | |
84 | #define AM33XX_CM_PER_SPI2_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0054) | |
85 | #define AM33XX_CM_PER_SPI3_CLKCTRL_OFFSET 0x0058 | |
86 | #define AM33XX_CM_PER_SPI3_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0058) | |
87 | #define AM33XX_CM_PER_L4LS_CLKCTRL_OFFSET 0x0060 | |
88 | #define AM33XX_CM_PER_L4LS_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0060) | |
89 | #define AM33XX_CM_PER_L4FW_CLKCTRL_OFFSET 0x0064 | |
90 | #define AM33XX_CM_PER_L4FW_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0064) | |
91 | #define AM33XX_CM_PER_MCASP1_CLKCTRL_OFFSET 0x0068 | |
92 | #define AM33XX_CM_PER_MCASP1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0068) | |
93 | #define AM33XX_CM_PER_UART1_CLKCTRL_OFFSET 0x006c | |
94 | #define AM33XX_CM_PER_UART1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x006c) | |
95 | #define AM33XX_CM_PER_UART2_CLKCTRL_OFFSET 0x0070 | |
96 | #define AM33XX_CM_PER_UART2_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0070) | |
97 | #define AM33XX_CM_PER_UART3_CLKCTRL_OFFSET 0x0074 | |
98 | #define AM33XX_CM_PER_UART3_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0074) | |
99 | #define AM33XX_CM_PER_UART4_CLKCTRL_OFFSET 0x0078 | |
100 | #define AM33XX_CM_PER_UART4_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0078) | |
101 | #define AM33XX_CM_PER_TIMER7_CLKCTRL_OFFSET 0x007c | |
102 | #define AM33XX_CM_PER_TIMER7_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x007c) | |
103 | #define AM33XX_CM_PER_TIMER2_CLKCTRL_OFFSET 0x0080 | |
104 | #define AM33XX_CM_PER_TIMER2_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0080) | |
105 | #define AM33XX_CM_PER_TIMER3_CLKCTRL_OFFSET 0x0084 | |
106 | #define AM33XX_CM_PER_TIMER3_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0084) | |
107 | #define AM33XX_CM_PER_TIMER4_CLKCTRL_OFFSET 0x0088 | |
108 | #define AM33XX_CM_PER_TIMER4_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0088) | |
109 | #define AM33XX_CM_PER_MCASP2_CLKCTRL_OFFSET 0x008c | |
110 | #define AM33XX_CM_PER_MCASP2_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x008c) | |
111 | #define AM33XX_CM_PER_RNG_CLKCTRL_OFFSET 0x0090 | |
112 | #define AM33XX_CM_PER_RNG_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0090) | |
113 | #define AM33XX_CM_PER_AES0_CLKCTRL_OFFSET 0x0094 | |
114 | #define AM33XX_CM_PER_AES0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0094) | |
115 | #define AM33XX_CM_PER_AES1_CLKCTRL_OFFSET 0x0098 | |
116 | #define AM33XX_CM_PER_AES1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0098) | |
117 | #define AM33XX_CM_PER_DES_CLKCTRL_OFFSET 0x009c | |
118 | #define AM33XX_CM_PER_DES_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x009c) | |
119 | #define AM33XX_CM_PER_SHA0_CLKCTRL_OFFSET 0x00a0 | |
120 | #define AM33XX_CM_PER_SHA0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00a0) | |
121 | #define AM33XX_CM_PER_PKA_CLKCTRL_OFFSET 0x00a4 | |
122 | #define AM33XX_CM_PER_PKA_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00a4) | |
123 | #define AM33XX_CM_PER_GPIO6_CLKCTRL_OFFSET 0x00a8 | |
124 | #define AM33XX_CM_PER_GPIO6_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00a8) | |
125 | #define AM33XX_CM_PER_GPIO1_CLKCTRL_OFFSET 0x00ac | |
126 | #define AM33XX_CM_PER_GPIO1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00ac) | |
127 | #define AM33XX_CM_PER_GPIO2_CLKCTRL_OFFSET 0x00b0 | |
128 | #define AM33XX_CM_PER_GPIO2_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00b0) | |
129 | #define AM33XX_CM_PER_GPIO3_CLKCTRL_OFFSET 0x00b4 | |
130 | #define AM33XX_CM_PER_GPIO3_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00b4) | |
131 | #define AM33XX_CM_PER_GPIO4_CLKCTRL_OFFSET 0x00b8 | |
132 | #define AM33XX_CM_PER_GPIO4_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00b8) | |
133 | #define AM33XX_CM_PER_TPCC_CLKCTRL_OFFSET 0x00bc | |
134 | #define AM33XX_CM_PER_TPCC_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00bc) | |
135 | #define AM33XX_CM_PER_DCAN0_CLKCTRL_OFFSET 0x00c0 | |
136 | #define AM33XX_CM_PER_DCAN0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00c0) | |
137 | #define AM33XX_CM_PER_DCAN1_CLKCTRL_OFFSET 0x00c4 | |
138 | #define AM33XX_CM_PER_DCAN1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00c4) | |
139 | #define AM33XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET 0x00cc | |
140 | #define AM33XX_CM_PER_EPWMSS1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00cc) | |
141 | #define AM33XX_CM_PER_EMIF_FW_CLKCTRL_OFFSET 0x00d0 | |
142 | #define AM33XX_CM_PER_EMIF_FW_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00d0) | |
143 | #define AM33XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET 0x00d4 | |
144 | #define AM33XX_CM_PER_EPWMSS0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00d4) | |
145 | #define AM33XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET 0x00d8 | |
146 | #define AM33XX_CM_PER_EPWMSS2_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00d8) | |
147 | #define AM33XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET 0x00dc | |
148 | #define AM33XX_CM_PER_L3_INSTR_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00dc) | |
149 | #define AM33XX_CM_PER_L3_CLKCTRL_OFFSET 0x00e0 | |
150 | #define AM33XX_CM_PER_L3_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00e0) | |
151 | #define AM33XX_CM_PER_IEEE5000_CLKCTRL_OFFSET 0x00e4 | |
152 | #define AM33XX_CM_PER_IEEE5000_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00e4) | |
153 | #define AM33XX_CM_PER_PRUSS_CLKCTRL_OFFSET 0x00e8 | |
154 | #define AM33XX_CM_PER_PRUSS_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00e8) | |
155 | #define AM33XX_CM_PER_TIMER5_CLKCTRL_OFFSET 0x00ec | |
156 | #define AM33XX_CM_PER_TIMER5_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00ec) | |
157 | #define AM33XX_CM_PER_TIMER6_CLKCTRL_OFFSET 0x00f0 | |
158 | #define AM33XX_CM_PER_TIMER6_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00f0) | |
159 | #define AM33XX_CM_PER_MMC1_CLKCTRL_OFFSET 0x00f4 | |
160 | #define AM33XX_CM_PER_MMC1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00f4) | |
161 | #define AM33XX_CM_PER_MMC2_CLKCTRL_OFFSET 0x00f8 | |
162 | #define AM33XX_CM_PER_MMC2_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00f8) | |
163 | #define AM33XX_CM_PER_TPTC1_CLKCTRL_OFFSET 0x00fc | |
164 | #define AM33XX_CM_PER_TPTC1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00fc) | |
165 | #define AM33XX_CM_PER_TPTC2_CLKCTRL_OFFSET 0x0100 | |
166 | #define AM33XX_CM_PER_TPTC2_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0100) | |
167 | #define AM33XX_CM_PER_GPIO5_CLKCTRL_OFFSET 0x0104 | |
168 | #define AM33XX_CM_PER_GPIO5_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0104) | |
169 | #define AM33XX_CM_PER_SPINLOCK_CLKCTRL_OFFSET 0x010c | |
170 | #define AM33XX_CM_PER_SPINLOCK_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x010c) | |
171 | #define AM33XX_CM_PER_MAILBOX0_CLKCTRL_OFFSET 0x0110 | |
172 | #define AM33XX_CM_PER_MAILBOX0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0110) | |
173 | #define AM33XX_CM_PER_L4HS_CLKSTCTRL_OFFSET 0x011c | |
174 | #define AM33XX_CM_PER_L4HS_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x011c) | |
175 | #define AM33XX_CM_PER_L4HS_CLKCTRL_OFFSET 0x0120 | |
176 | #define AM33XX_CM_PER_L4HS_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0120) | |
177 | #define AM33XX_CM_PER_MSTR_EXPS_CLKCTRL_OFFSET 0x0124 | |
178 | #define AM33XX_CM_PER_MSTR_EXPS_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0124) | |
179 | #define AM33XX_CM_PER_SLV_EXPS_CLKCTRL_OFFSET 0x0128 | |
180 | #define AM33XX_CM_PER_SLV_EXPS_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0128) | |
181 | #define AM33XX_CM_PER_OCPWP_L3_CLKSTCTRL_OFFSET 0x012c | |
182 | #define AM33XX_CM_PER_OCPWP_L3_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x012c) | |
183 | #define AM33XX_CM_PER_OCPWP_CLKCTRL_OFFSET 0x0130 | |
184 | #define AM33XX_CM_PER_OCPWP_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0130) | |
185 | #define AM33XX_CM_PER_MAILBOX1_CLKCTRL_OFFSET 0x0134 | |
186 | #define AM33XX_CM_PER_MAILBOX1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0134) | |
187 | #define AM33XX_CM_PER_PRUSS_CLKSTCTRL_OFFSET 0x0140 | |
188 | #define AM33XX_CM_PER_PRUSS_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0140) | |
189 | #define AM33XX_CM_PER_CPSW_CLKSTCTRL_OFFSET 0x0144 | |
190 | #define AM33XX_CM_PER_CPSW_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0144) | |
191 | #define AM33XX_CM_PER_LCDC_CLKSTCTRL_OFFSET 0x0148 | |
192 | #define AM33XX_CM_PER_LCDC_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0148) | |
193 | #define AM33XX_CM_PER_CLKDIV32K_CLKCTRL_OFFSET 0x014c | |
194 | #define AM33XX_CM_PER_CLKDIV32K_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x014c) | |
195 | #define AM33XX_CM_PER_CLK_24MHZ_CLKSTCTRL_OFFSET 0x0150 | |
196 | #define AM33XX_CM_PER_CLK_24MHZ_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0150) | |
197 | ||
198 | /* CM.WKUP_CM register offsets */ | |
199 | #define AM33XX_CM_WKUP_CLKSTCTRL_OFFSET 0x0000 | |
200 | #define AM33XX_CM_WKUP_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0000) | |
201 | #define AM33XX_CM_WKUP_CONTROL_CLKCTRL_OFFSET 0x0004 | |
202 | #define AM33XX_CM_WKUP_CONTROL_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0004) | |
203 | #define AM33XX_CM_WKUP_GPIO0_CLKCTRL_OFFSET 0x0008 | |
204 | #define AM33XX_CM_WKUP_GPIO0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0008) | |
205 | #define AM33XX_CM_WKUP_L4WKUP_CLKCTRL_OFFSET 0x000c | |
206 | #define AM33XX_CM_WKUP_L4WKUP_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x000c) | |
207 | #define AM33XX_CM_WKUP_TIMER0_CLKCTRL_OFFSET 0x0010 | |
208 | #define AM33XX_CM_WKUP_TIMER0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0010) | |
209 | #define AM33XX_CM_WKUP_DEBUGSS_CLKCTRL_OFFSET 0x0014 | |
210 | #define AM33XX_CM_WKUP_DEBUGSS_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0014) | |
211 | #define AM33XX_CM_L3_AON_CLKSTCTRL_OFFSET 0x0018 | |
212 | #define AM33XX_CM_L3_AON_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0018) | |
213 | #define AM33XX_CM_AUTOIDLE_DPLL_MPU_OFFSET 0x001c | |
214 | #define AM33XX_CM_AUTOIDLE_DPLL_MPU AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x001c) | |
215 | #define AM33XX_CM_IDLEST_DPLL_MPU_OFFSET 0x0020 | |
216 | #define AM33XX_CM_IDLEST_DPLL_MPU AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0020) | |
217 | #define AM33XX_CM_SSC_DELTAMSTEP_DPLL_MPU_OFFSET 0x0024 | |
218 | #define AM33XX_CM_SSC_DELTAMSTEP_DPLL_MPU AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0024) | |
219 | #define AM33XX_CM_SSC_MODFREQDIV_DPLL_MPU_OFFSET 0x0028 | |
220 | #define AM33XX_CM_SSC_MODFREQDIV_DPLL_MPU AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0028) | |
221 | #define AM33XX_CM_CLKSEL_DPLL_MPU_OFFSET 0x002c | |
222 | #define AM33XX_CM_CLKSEL_DPLL_MPU AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x002c) | |
223 | #define AM33XX_CM_AUTOIDLE_DPLL_DDR_OFFSET 0x0030 | |
224 | #define AM33XX_CM_AUTOIDLE_DPLL_DDR AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0030) | |
225 | #define AM33XX_CM_IDLEST_DPLL_DDR_OFFSET 0x0034 | |
226 | #define AM33XX_CM_IDLEST_DPLL_DDR AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0034) | |
227 | #define AM33XX_CM_SSC_DELTAMSTEP_DPLL_DDR_OFFSET 0x0038 | |
228 | #define AM33XX_CM_SSC_DELTAMSTEP_DPLL_DDR AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0038) | |
229 | #define AM33XX_CM_SSC_MODFREQDIV_DPLL_DDR_OFFSET 0x003c | |
230 | #define AM33XX_CM_SSC_MODFREQDIV_DPLL_DDR AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x003c) | |
231 | #define AM33XX_CM_CLKSEL_DPLL_DDR_OFFSET 0x0040 | |
232 | #define AM33XX_CM_CLKSEL_DPLL_DDR AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0040) | |
233 | #define AM33XX_CM_AUTOIDLE_DPLL_DISP_OFFSET 0x0044 | |
234 | #define AM33XX_CM_AUTOIDLE_DPLL_DISP AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0044) | |
235 | #define AM33XX_CM_IDLEST_DPLL_DISP_OFFSET 0x0048 | |
236 | #define AM33XX_CM_IDLEST_DPLL_DISP AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0048) | |
237 | #define AM33XX_CM_SSC_DELTAMSTEP_DPLL_DISP_OFFSET 0x004c | |
238 | #define AM33XX_CM_SSC_DELTAMSTEP_DPLL_DISP AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x004c) | |
239 | #define AM33XX_CM_SSC_MODFREQDIV_DPLL_DISP_OFFSET 0x0050 | |
240 | #define AM33XX_CM_SSC_MODFREQDIV_DPLL_DISP AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0050) | |
241 | #define AM33XX_CM_CLKSEL_DPLL_DISP_OFFSET 0x0054 | |
242 | #define AM33XX_CM_CLKSEL_DPLL_DISP AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0054) | |
243 | #define AM33XX_CM_AUTOIDLE_DPLL_CORE_OFFSET 0x0058 | |
244 | #define AM33XX_CM_AUTOIDLE_DPLL_CORE AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0058) | |
245 | #define AM33XX_CM_IDLEST_DPLL_CORE_OFFSET 0x005c | |
246 | #define AM33XX_CM_IDLEST_DPLL_CORE AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x005c) | |
247 | #define AM33XX_CM_SSC_DELTAMSTEP_DPLL_CORE_OFFSET 0x0060 | |
248 | #define AM33XX_CM_SSC_DELTAMSTEP_DPLL_CORE AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0060) | |
249 | #define AM33XX_CM_SSC_MODFREQDIV_DPLL_CORE_OFFSET 0x0064 | |
250 | #define AM33XX_CM_SSC_MODFREQDIV_DPLL_CORE AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0064) | |
251 | #define AM33XX_CM_CLKSEL_DPLL_CORE_OFFSET 0x0068 | |
252 | #define AM33XX_CM_CLKSEL_DPLL_CORE AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0068) | |
253 | #define AM33XX_CM_AUTOIDLE_DPLL_PER_OFFSET 0x006c | |
254 | #define AM33XX_CM_AUTOIDLE_DPLL_PER AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x006c) | |
255 | #define AM33XX_CM_IDLEST_DPLL_PER_OFFSET 0x0070 | |
256 | #define AM33XX_CM_IDLEST_DPLL_PER AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0070) | |
257 | #define AM33XX_CM_SSC_DELTAMSTEP_DPLL_PER_OFFSET 0x0074 | |
258 | #define AM33XX_CM_SSC_DELTAMSTEP_DPLL_PER AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0074) | |
259 | #define AM33XX_CM_SSC_MODFREQDIV_DPLL_PER_OFFSET 0x0078 | |
260 | #define AM33XX_CM_SSC_MODFREQDIV_DPLL_PER AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0078) | |
261 | #define AM33XX_CM_CLKDCOLDO_DPLL_PER_OFFSET 0x007c | |
262 | #define AM33XX_CM_CLKDCOLDO_DPLL_PER AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x007c) | |
263 | #define AM33XX_CM_DIV_M4_DPLL_CORE_OFFSET 0x0080 | |
264 | #define AM33XX_CM_DIV_M4_DPLL_CORE AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0080) | |
265 | #define AM33XX_CM_DIV_M5_DPLL_CORE_OFFSET 0x0084 | |
266 | #define AM33XX_CM_DIV_M5_DPLL_CORE AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0084) | |
267 | #define AM33XX_CM_CLKMODE_DPLL_MPU_OFFSET 0x0088 | |
268 | #define AM33XX_CM_CLKMODE_DPLL_MPU AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0088) | |
269 | #define AM33XX_CM_CLKMODE_DPLL_PER_OFFSET 0x008c | |
270 | #define AM33XX_CM_CLKMODE_DPLL_PER AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x008c) | |
271 | #define AM33XX_CM_CLKMODE_DPLL_CORE_OFFSET 0x0090 | |
272 | #define AM33XX_CM_CLKMODE_DPLL_CORE AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0090) | |
273 | #define AM33XX_CM_CLKMODE_DPLL_DDR_OFFSET 0x0094 | |
274 | #define AM33XX_CM_CLKMODE_DPLL_DDR AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0094) | |
275 | #define AM33XX_CM_CLKMODE_DPLL_DISP_OFFSET 0x0098 | |
276 | #define AM33XX_CM_CLKMODE_DPLL_DISP AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0098) | |
277 | #define AM33XX_CM_CLKSEL_DPLL_PERIPH_OFFSET 0x009c | |
278 | #define AM33XX_CM_CLKSEL_DPLL_PERIPH AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x009c) | |
279 | #define AM33XX_CM_DIV_M2_DPLL_DDR_OFFSET 0x00a0 | |
280 | #define AM33XX_CM_DIV_M2_DPLL_DDR AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00a0) | |
281 | #define AM33XX_CM_DIV_M2_DPLL_DISP_OFFSET 0x00a4 | |
282 | #define AM33XX_CM_DIV_M2_DPLL_DISP AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00a4) | |
283 | #define AM33XX_CM_DIV_M2_DPLL_MPU_OFFSET 0x00a8 | |
284 | #define AM33XX_CM_DIV_M2_DPLL_MPU AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00a8) | |
285 | #define AM33XX_CM_DIV_M2_DPLL_PER_OFFSET 0x00ac | |
286 | #define AM33XX_CM_DIV_M2_DPLL_PER AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00ac) | |
287 | #define AM33XX_CM_WKUP_WKUP_M3_CLKCTRL_OFFSET 0x00b0 | |
288 | #define AM33XX_CM_WKUP_WKUP_M3_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00b0) | |
289 | #define AM33XX_CM_WKUP_UART0_CLKCTRL_OFFSET 0x00b4 | |
290 | #define AM33XX_CM_WKUP_UART0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00b4) | |
291 | #define AM33XX_CM_WKUP_I2C0_CLKCTRL_OFFSET 0x00b8 | |
292 | #define AM33XX_CM_WKUP_I2C0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00b8) | |
293 | #define AM33XX_CM_WKUP_ADC_TSC_CLKCTRL_OFFSET 0x00bc | |
294 | #define AM33XX_CM_WKUP_ADC_TSC_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00bc) | |
295 | #define AM33XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET 0x00c0 | |
296 | #define AM33XX_CM_WKUP_SMARTREFLEX0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00c0) | |
297 | #define AM33XX_CM_WKUP_TIMER1_CLKCTRL_OFFSET 0x00c4 | |
298 | #define AM33XX_CM_WKUP_TIMER1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00c4) | |
299 | #define AM33XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET 0x00c8 | |
300 | #define AM33XX_CM_WKUP_SMARTREFLEX1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00c8) | |
301 | #define AM33XX_CM_L4_WKUP_AON_CLKSTCTRL_OFFSET 0x00cc | |
302 | #define AM33XX_CM_L4_WKUP_AON_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00cc) | |
303 | #define AM33XX_CM_WKUP_WDT0_CLKCTRL_OFFSET 0x00d0 | |
304 | #define AM33XX_CM_WKUP_WDT0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00d0) | |
305 | #define AM33XX_CM_WKUP_WDT1_CLKCTRL_OFFSET 0x00d4 | |
306 | #define AM33XX_CM_WKUP_WDT1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00d4) | |
307 | #define AM33XX_CM_DIV_M6_DPLL_CORE_OFFSET 0x00d8 | |
308 | #define AM33XX_CM_DIV_M6_DPLL_CORE AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00d8) | |
309 | ||
310 | /* CM.DPLL_CM register offsets */ | |
311 | #define AM33XX_CLKSEL_TIMER7_CLK_OFFSET 0x0004 | |
312 | #define AM33XX_CLKSEL_TIMER7_CLK AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0004) | |
313 | #define AM33XX_CLKSEL_TIMER2_CLK_OFFSET 0x0008 | |
314 | #define AM33XX_CLKSEL_TIMER2_CLK AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0008) | |
315 | #define AM33XX_CLKSEL_TIMER3_CLK_OFFSET 0x000c | |
316 | #define AM33XX_CLKSEL_TIMER3_CLK AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x000c) | |
317 | #define AM33XX_CLKSEL_TIMER4_CLK_OFFSET 0x0010 | |
318 | #define AM33XX_CLKSEL_TIMER4_CLK AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0010) | |
319 | #define AM33XX_CM_MAC_CLKSEL_OFFSET 0x0014 | |
320 | #define AM33XX_CM_MAC_CLKSEL AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0014) | |
321 | #define AM33XX_CLKSEL_TIMER5_CLK_OFFSET 0x0018 | |
322 | #define AM33XX_CLKSEL_TIMER5_CLK AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0018) | |
323 | #define AM33XX_CLKSEL_TIMER6_CLK_OFFSET 0x001c | |
324 | #define AM33XX_CLKSEL_TIMER6_CLK AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x001c) | |
325 | #define AM33XX_CM_CPTS_RFT_CLKSEL_OFFSET 0x0020 | |
326 | #define AM33XX_CM_CPTS_RFT_CLKSEL AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0020) | |
327 | #define AM33XX_CLKSEL_TIMER1MS_CLK_OFFSET 0x0028 | |
328 | #define AM33XX_CLKSEL_TIMER1MS_CLK AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0028) | |
329 | #define AM33XX_CLKSEL_GFX_FCLK_OFFSET 0x002c | |
330 | #define AM33XX_CLKSEL_GFX_FCLK AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x002c) | |
331 | #define AM33XX_CLKSEL_PRUSS_OCP_CLK_OFFSET 0x0030 | |
332 | #define AM33XX_CLKSEL_PRUSS_OCP_CLK AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0030) | |
333 | #define AM33XX_CLKSEL_LCDC_PIXEL_CLK_OFFSET 0x0034 | |
334 | #define AM33XX_CLKSEL_LCDC_PIXEL_CLK AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0034) | |
335 | #define AM33XX_CLKSEL_WDT1_CLK_OFFSET 0x0038 | |
336 | #define AM33XX_CLKSEL_WDT1_CLK AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0038) | |
337 | #define AM33XX_CLKSEL_GPIO0_DBCLK_OFFSET 0x003c | |
338 | #define AM33XX_CLKSEL_GPIO0_DBCLK AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x003c) | |
339 | ||
340 | /* CM.MPU_CM register offsets */ | |
341 | #define AM33XX_CM_MPU_CLKSTCTRL_OFFSET 0x0000 | |
342 | #define AM33XX_CM_MPU_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_MPU_MOD, 0x0000) | |
343 | #define AM33XX_CM_MPU_MPU_CLKCTRL_OFFSET 0x0004 | |
344 | #define AM33XX_CM_MPU_MPU_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_MPU_MOD, 0x0004) | |
345 | ||
346 | /* CM.DEVICE_CM register offsets */ | |
347 | #define AM33XX_CM_CLKOUT_CTRL_OFFSET 0x0000 | |
348 | #define AM33XX_CM_CLKOUT_CTRL AM33XX_CM_REGADDR(AM33XX_CM_DEVICE_MOD, 0x0000) | |
349 | ||
350 | /* CM.RTC_CM register offsets */ | |
351 | #define AM33XX_CM_RTC_RTC_CLKCTRL_OFFSET 0x0000 | |
352 | #define AM33XX_CM_RTC_RTC_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_RTC_MOD, 0x0000) | |
353 | #define AM33XX_CM_RTC_CLKSTCTRL_OFFSET 0x0004 | |
354 | #define AM33XX_CM_RTC_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_RTC_MOD, 0x0004) | |
355 | ||
356 | /* CM.GFX_CM register offsets */ | |
357 | #define AM33XX_CM_GFX_L3_CLKSTCTRL_OFFSET 0x0000 | |
358 | #define AM33XX_CM_GFX_L3_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_GFX_MOD, 0x0000) | |
359 | #define AM33XX_CM_GFX_GFX_CLKCTRL_OFFSET 0x0004 | |
360 | #define AM33XX_CM_GFX_GFX_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_GFX_MOD, 0x0004) | |
361 | #define AM33XX_CM_GFX_BITBLT_CLKCTRL_OFFSET 0x0008 | |
362 | #define AM33XX_CM_GFX_BITBLT_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_GFX_MOD, 0x0008) | |
363 | #define AM33XX_CM_GFX_L4LS_GFX_CLKSTCTRL__1_OFFSET 0x000c | |
364 | #define AM33XX_CM_GFX_L4LS_GFX_CLKSTCTRL__1 AM33XX_CM_REGADDR(AM33XX_CM_GFX_MOD, 0x000c) | |
365 | #define AM33XX_CM_GFX_MMUCFG_CLKCTRL_OFFSET 0x0010 | |
366 | #define AM33XX_CM_GFX_MMUCFG_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_GFX_MOD, 0x0010) | |
367 | #define AM33XX_CM_GFX_MMUDATA_CLKCTRL_OFFSET 0x0014 | |
368 | #define AM33XX_CM_GFX_MMUDATA_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_GFX_MOD, 0x0014) | |
369 | ||
370 | /* CM.CEFUSE_CM register offsets */ | |
371 | #define AM33XX_CM_CEFUSE_CLKSTCTRL_OFFSET 0x0000 | |
372 | #define AM33XX_CM_CEFUSE_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_CEFUSE_MOD, 0x0000) | |
373 | #define AM33XX_CM_CEFUSE_CEFUSE_CLKCTRL_OFFSET 0x0020 | |
374 | #define AM33XX_CM_CEFUSE_CEFUSE_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_CEFUSE_MOD, 0x0020) | |
375 | ||
376 | ||
1a7cb4d9 | 377 | #ifndef __ASSEMBLER__ |
425dc8b2 | 378 | int am33xx_cm_init(const struct omap_prcm_init_data *data); |
1a7cb4d9 | 379 | #endif /* ASSEMBLER */ |
f969a6dc | 380 | #endif |