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ARM: OMAP4+/AM33xx: CM: add common API for cm_wait_module_idle
[deliverable/linux.git] / arch / arm / mach-omap2 / cm3xxx.c
CommitLineData
71348bca 1/*
4bd5259e 2 * OMAP3xxx CM module functions
71348bca
PW		 3 *
4 * Copyright (C) 2009 Nokia Corporation
4bd5259e 5 * Copyright (C) 2008-2010, 2012 Texas Instruments, Inc.
71348bca 6 * Paul Walmsley
4bd5259e 7 * Rajendra Nayak <rnayak@ti.com>
71348bca
PW		 8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#include <linux/kernel.h>
71348bca
PW		 15#include <linux/types.h>
16#include <linux/delay.h>
71348bca
PW		 17#include <linux/errno.h>
18#include <linux/err.h>
19#include <linux/io.h>
20
4bd5259e 21#include "prm2xxx_3xxx.h"
71348bca 22#include "cm.h"
ff4ae5d9 23#include "cm3xxx.h"
71348bca 24#include "cm-regbits-34xx.h"
4bd5259e 25#include "clockdomain.h"
71348bca 26
ff4ae5d9
PW		 27static const u8 omap3xxx_cm_idlest_offs[] = {
28 CM_IDLEST1, CM_IDLEST2, OMAP2430_CM_IDLEST3
71348bca
PW		 29};
30
55ae3507
PW		 31/*
32 *
33 */
34
35static void _write_clktrctrl(u8 c, s16 module, u32 mask)
36{
37 u32 v;
38
39 v = omap2_cm_read_mod_reg(module, OMAP2_CM_CLKSTCTRL);
40 v &= ~mask;
41 v |= c << __ffs(mask);
42 omap2_cm_write_mod_reg(v, module, OMAP2_CM_CLKSTCTRL);
43}
44
ff4ae5d9 45bool omap3xxx_cm_is_clkdm_in_hwsup(s16 module, u32 mask)
55ae3507
PW		 46{
47 u32 v;
55ae3507
PW		 48
49 v = omap2_cm_read_mod_reg(module, OMAP2_CM_CLKSTCTRL);
50 v &= mask;
51 v >>= __ffs(mask);
52
ff4ae5d9 53 return (v == OMAP34XX_CLKSTCTRL_ENABLE_AUTO) ? 1 : 0;
55ae3507
PW		 54}
55
56void omap3xxx_cm_clkdm_enable_hwsup(s16 module, u32 mask)
57{
58 _write_clktrctrl(OMAP34XX_CLKSTCTRL_ENABLE_AUTO, module, mask);
59}
60
61void omap3xxx_cm_clkdm_disable_hwsup(s16 module, u32 mask)
62{
63 _write_clktrctrl(OMAP34XX_CLKSTCTRL_DISABLE_AUTO, module, mask);
64}
65
66void omap3xxx_cm_clkdm_force_sleep(s16 module, u32 mask)
67{
68 _write_clktrctrl(OMAP34XX_CLKSTCTRL_FORCE_SLEEP, module, mask);
69}
70
71void omap3xxx_cm_clkdm_force_wakeup(s16 module, u32 mask)
72{
73 _write_clktrctrl(OMAP34XX_CLKSTCTRL_FORCE_WAKEUP, module, mask);
74}
75
55ae3507
PW		 76/*
77 *
78 */
79
71348bca 80/**
ff4ae5d9 81 * omap3xxx_cm_wait_module_ready - wait for a module to leave idle or standby
021b6ff0 82 * @part: PRCM partition, ignored for OMAP3
71348bca
PW		 83 * @prcm_mod: PRCM module offset
84 * @idlest_id: CM_IDLESTx register ID (i.e., x = 1, 2, 3)
85 * @idlest_shift: shift of the bit in the CM_IDLEST* register to check
86 *
ff4ae5d9
PW		 87 * Wait for the PRCM to indicate that the module identified by
88 * (@prcm_mod, @idlest_id, @idlest_shift) is clocked. Return 0 upon
89 * success or -EBUSY if the module doesn't enable in time.
71348bca 90 */
021b6ff0
TK		 91static int omap3xxx_cm_wait_module_ready(u8 part, s16 prcm_mod, u16 idlest_id,
92 u8 idlest_shift)
71348bca
PW		 93{
94 int ena = 0, i = 0;
95 u8 cm_idlest_reg;
96 u32 mask;
97
ff4ae5d9 98 if (!idlest_id || (idlest_id > ARRAY_SIZE(omap3xxx_cm_idlest_offs)))
71348bca
PW		 99 return -EINVAL;
100
ff4ae5d9 101 cm_idlest_reg = omap3xxx_cm_idlest_offs[idlest_id - 1];
71348bca 102
64056167 103 mask = 1 << idlest_shift;
ff4ae5d9 104 ena = 0;
64056167 105
ff4ae5d9
PW		 106 omap_test_timeout(((omap2_cm_read_mod_reg(prcm_mod, cm_idlest_reg) &
107 mask) == ena), MAX_MODULE_READY_TIME, i);
71348bca
PW		 108
109 return (i < MAX_MODULE_READY_TIME) ? 0 : -EBUSY;
110}
111
c4ceedcb
PW		 112/**
113 * omap3xxx_cm_split_idlest_reg - split CM_IDLEST reg addr into its components
114 * @idlest_reg: CM_IDLEST* virtual address
115 * @prcm_inst: pointer to an s16 to return the PRCM instance offset
116 * @idlest_reg_id: pointer to a u8 to return the CM_IDLESTx register ID
117 *
118 * XXX This function is only needed until absolute register addresses are
119 * removed from the OMAP struct clk records.
120 */
121int omap3xxx_cm_split_idlest_reg(void __iomem *idlest_reg, s16 *prcm_inst,
122 u8 *idlest_reg_id)
123{
124 unsigned long offs;
125 u8 idlest_offs;
126 int i;
127
128 if (idlest_reg < (cm_base + OMAP3430_IVA2_MOD) ||
129 idlest_reg > (cm_base + 0x1ffff))
130 return -EINVAL;
131
132 idlest_offs = (unsigned long)idlest_reg & 0xff;
133 for (i = 0; i < ARRAY_SIZE(omap3xxx_cm_idlest_offs); i++) {
134 if (idlest_offs == omap3xxx_cm_idlest_offs[i]) {
135 *idlest_reg_id = i + 1;
136 break;
137 }
138 }
139
140 if (i == ARRAY_SIZE(omap3xxx_cm_idlest_offs))
141 return -EINVAL;
142
143 offs = idlest_reg - cm_base;
144 offs &= 0xff00;
145 *prcm_inst = offs;
146
147 return 0;
148}
149
4bd5259e
PW		 150/* Clockdomain low-level operations */
151
152static int omap3xxx_clkdm_add_sleepdep(struct clockdomain *clkdm1,
153 struct clockdomain *clkdm2)
154{
155 omap2_cm_set_mod_reg_bits((1 << clkdm2->dep_bit),
156 clkdm1->pwrdm.ptr->prcm_offs,
157 OMAP3430_CM_SLEEPDEP);
158 return 0;
159}
160
161static int omap3xxx_clkdm_del_sleepdep(struct clockdomain *clkdm1,
162 struct clockdomain *clkdm2)
163{
164 omap2_cm_clear_mod_reg_bits((1 << clkdm2->dep_bit),
165 clkdm1->pwrdm.ptr->prcm_offs,
166 OMAP3430_CM_SLEEPDEP);
167 return 0;
168}
169
170static int omap3xxx_clkdm_read_sleepdep(struct clockdomain *clkdm1,
171 struct clockdomain *clkdm2)
172{
173 return omap2_cm_read_mod_bits_shift(clkdm1->pwrdm.ptr->prcm_offs,
174 OMAP3430_CM_SLEEPDEP,
175 (1 << clkdm2->dep_bit));
176}
177
178static int omap3xxx_clkdm_clear_all_sleepdeps(struct clockdomain *clkdm)
179{
180 struct clkdm_dep *cd;
181 u32 mask = 0;
182
183 for (cd = clkdm->sleepdep_srcs; cd && cd->clkdm_name; cd++) {
184 if (!cd->clkdm)
185 continue; /* only happens if data is erroneous */
186
187 mask |= 1 << cd->clkdm->dep_bit;
92493870 188 cd->sleepdep_usecount = 0;
4bd5259e
PW		 189 }
190 omap2_cm_clear_mod_reg_bits(mask, clkdm->pwrdm.ptr->prcm_offs,
191 OMAP3430_CM_SLEEPDEP);
192 return 0;
193}
194
195static int omap3xxx_clkdm_sleep(struct clockdomain *clkdm)
196{
197 omap3xxx_cm_clkdm_force_sleep(clkdm->pwrdm.ptr->prcm_offs,
198 clkdm->clktrctrl_mask);
199 return 0;
200}
201
202static int omap3xxx_clkdm_wakeup(struct clockdomain *clkdm)
203{
204 omap3xxx_cm_clkdm_force_wakeup(clkdm->pwrdm.ptr->prcm_offs,
205 clkdm->clktrctrl_mask);
206 return 0;
207}
208
209static void omap3xxx_clkdm_allow_idle(struct clockdomain *clkdm)
210{
92493870 211 if (clkdm->usecount > 0)
65958fb6 212 clkdm_add_autodeps(clkdm);
4bd5259e
PW		 213
214 omap3xxx_cm_clkdm_enable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
215 clkdm->clktrctrl_mask);
216}
217
218static void omap3xxx_clkdm_deny_idle(struct clockdomain *clkdm)
219{
220 omap3xxx_cm_clkdm_disable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
221 clkdm->clktrctrl_mask);
222
92493870 223 if (clkdm->usecount > 0)
65958fb6 224 clkdm_del_autodeps(clkdm);
4bd5259e
PW		 225}
226
227static int omap3xxx_clkdm_clk_enable(struct clockdomain *clkdm)
228{
229 bool hwsup = false;
230
231 if (!clkdm->clktrctrl_mask)
232 return 0;
233
234 /*
235 * The CLKDM_MISSING_IDLE_REPORTING flag documentation has
236 * more details on the unpleasant problem this is working
237 * around
238 */
239 if ((clkdm->flags & CLKDM_MISSING_IDLE_REPORTING) &&
240 (clkdm->flags & CLKDM_CAN_FORCE_WAKEUP)) {
241 omap3xxx_clkdm_wakeup(clkdm);
242 return 0;
243 }
244
245 hwsup = omap3xxx_cm_is_clkdm_in_hwsup(clkdm->pwrdm.ptr->prcm_offs,
246 clkdm->clktrctrl_mask);
247
248 if (hwsup) {
249 /* Disable HW transitions when we are changing deps */
250 omap3xxx_cm_clkdm_disable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
251 clkdm->clktrctrl_mask);
65958fb6 252 clkdm_add_autodeps(clkdm);
4bd5259e
PW		 253 omap3xxx_cm_clkdm_enable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
254 clkdm->clktrctrl_mask);
255 } else {
256 if (clkdm->flags & CLKDM_CAN_FORCE_WAKEUP)
257 omap3xxx_clkdm_wakeup(clkdm);
258 }
259
260 return 0;
261}
262
263static int omap3xxx_clkdm_clk_disable(struct clockdomain *clkdm)
264{
265 bool hwsup = false;
266
267 if (!clkdm->clktrctrl_mask)
268 return 0;
269
270 /*
271 * The CLKDM_MISSING_IDLE_REPORTING flag documentation has
272 * more details on the unpleasant problem this is working
273 * around
274 */
275 if (clkdm->flags & CLKDM_MISSING_IDLE_REPORTING &&
276 !(clkdm->flags & CLKDM_CAN_FORCE_SLEEP)) {
277 omap3xxx_cm_clkdm_enable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
278 clkdm->clktrctrl_mask);
279 return 0;
280 }
281
282 hwsup = omap3xxx_cm_is_clkdm_in_hwsup(clkdm->pwrdm.ptr->prcm_offs,
283 clkdm->clktrctrl_mask);
284
285 if (hwsup) {
286 /* Disable HW transitions when we are changing deps */
287 omap3xxx_cm_clkdm_disable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
288 clkdm->clktrctrl_mask);
65958fb6 289 clkdm_del_autodeps(clkdm);
4bd5259e
PW		 290 omap3xxx_cm_clkdm_enable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
291 clkdm->clktrctrl_mask);
292 } else {
293 if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP)
294 omap3xxx_clkdm_sleep(clkdm);
295 }
296
297 return 0;
298}
299
300struct clkdm_ops omap3_clkdm_operations = {
301 .clkdm_add_wkdep = omap2_clkdm_add_wkdep,
302 .clkdm_del_wkdep = omap2_clkdm_del_wkdep,
303 .clkdm_read_wkdep = omap2_clkdm_read_wkdep,
304 .clkdm_clear_all_wkdeps = omap2_clkdm_clear_all_wkdeps,
305 .clkdm_add_sleepdep = omap3xxx_clkdm_add_sleepdep,
306 .clkdm_del_sleepdep = omap3xxx_clkdm_del_sleepdep,
307 .clkdm_read_sleepdep = omap3xxx_clkdm_read_sleepdep,
308 .clkdm_clear_all_sleepdeps = omap3xxx_clkdm_clear_all_sleepdeps,
309 .clkdm_sleep = omap3xxx_clkdm_sleep,
310 .clkdm_wakeup = omap3xxx_clkdm_wakeup,
311 .clkdm_allow_idle = omap3xxx_clkdm_allow_idle,
312 .clkdm_deny_idle = omap3xxx_clkdm_deny_idle,
313 .clkdm_clk_enable = omap3xxx_clkdm_clk_enable,
314 .clkdm_clk_disable = omap3xxx_clkdm_clk_disable,
315};
316
f0611a5c
PW		 317/*
318 * Context save/restore code - OMAP3 only
319 */
f0611a5c
PW		 320struct omap3_cm_regs {
321 u32 iva2_cm_clksel1;
322 u32 iva2_cm_clksel2;
323 u32 cm_sysconfig;
324 u32 sgx_cm_clksel;
325 u32 dss_cm_clksel;
326 u32 cam_cm_clksel;
327 u32 per_cm_clksel;
328 u32 emu_cm_clksel;
329 u32 emu_cm_clkstctrl;
a8ae645c 330 u32 pll_cm_autoidle;
f0611a5c
PW		 331 u32 pll_cm_autoidle2;
332 u32 pll_cm_clksel4;
333 u32 pll_cm_clksel5;
334 u32 pll_cm_clken2;
335 u32 cm_polctrl;
336 u32 iva2_cm_fclken;
337 u32 iva2_cm_clken_pll;
338 u32 core_cm_fclken1;
339 u32 core_cm_fclken3;
340 u32 sgx_cm_fclken;
341 u32 wkup_cm_fclken;
342 u32 dss_cm_fclken;
343 u32 cam_cm_fclken;
344 u32 per_cm_fclken;
345 u32 usbhost_cm_fclken;
346 u32 core_cm_iclken1;
347 u32 core_cm_iclken2;
348 u32 core_cm_iclken3;
349 u32 sgx_cm_iclken;
350 u32 wkup_cm_iclken;
351 u32 dss_cm_iclken;
352 u32 cam_cm_iclken;
353 u32 per_cm_iclken;
354 u32 usbhost_cm_iclken;
355 u32 iva2_cm_autoidle2;
356 u32 mpu_cm_autoidle2;
357 u32 iva2_cm_clkstctrl;
358 u32 mpu_cm_clkstctrl;
359 u32 core_cm_clkstctrl;
360 u32 sgx_cm_clkstctrl;
361 u32 dss_cm_clkstctrl;
362 u32 cam_cm_clkstctrl;
363 u32 per_cm_clkstctrl;
364 u32 neon_cm_clkstctrl;
365 u32 usbhost_cm_clkstctrl;
366 u32 core_cm_autoidle1;
367 u32 core_cm_autoidle2;
368 u32 core_cm_autoidle3;
369 u32 wkup_cm_autoidle;
370 u32 dss_cm_autoidle;
371 u32 cam_cm_autoidle;
372 u32 per_cm_autoidle;
373 u32 usbhost_cm_autoidle;
374 u32 sgx_cm_sleepdep;
375 u32 dss_cm_sleepdep;
376 u32 cam_cm_sleepdep;
377 u32 per_cm_sleepdep;
378 u32 usbhost_cm_sleepdep;
379 u32 cm_clkout_ctrl;
380};
381
382static struct omap3_cm_regs cm_context;
383
384void omap3_cm_save_context(void)
385{
386 cm_context.iva2_cm_clksel1 =
c4d7e58f 387 omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_CLKSEL1);
f0611a5c 388 cm_context.iva2_cm_clksel2 =
c4d7e58f 389 omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_CLKSEL2);
b21be7bc
TK		 390 cm_context.cm_sysconfig =
391 omap2_cm_read_mod_reg(OCP_MOD, OMAP3430_CM_SYSCONFIG);
f0611a5c 392 cm_context.sgx_cm_clksel =
c4d7e58f 393 omap2_cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_CLKSEL);
f0611a5c 394 cm_context.dss_cm_clksel =
c4d7e58f 395 omap2_cm_read_mod_reg(OMAP3430_DSS_MOD, CM_CLKSEL);
f0611a5c 396 cm_context.cam_cm_clksel =
c4d7e58f 397 omap2_cm_read_mod_reg(OMAP3430_CAM_MOD, CM_CLKSEL);
f0611a5c 398 cm_context.per_cm_clksel =
c4d7e58f 399 omap2_cm_read_mod_reg(OMAP3430_PER_MOD, CM_CLKSEL);
f0611a5c 400 cm_context.emu_cm_clksel =
c4d7e58f 401 omap2_cm_read_mod_reg(OMAP3430_EMU_MOD, CM_CLKSEL1);
f0611a5c 402 cm_context.emu_cm_clkstctrl =
c4d7e58f 403 omap2_cm_read_mod_reg(OMAP3430_EMU_MOD, OMAP2_CM_CLKSTCTRL);
a8ae645c
EV		 404 /*
405 * As per erratum i671, ROM code does not respect the PER DPLL
406 * programming scheme if CM_AUTOIDLE_PLL.AUTO_PERIPH_DPLL == 1.
407 * In this case, even though this register has been saved in
408 * scratchpad contents, we need to restore AUTO_PERIPH_DPLL
409 * by ourselves. So, we need to save it anyway.
410 */
411 cm_context.pll_cm_autoidle =
412 omap2_cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE);
f0611a5c 413 cm_context.pll_cm_autoidle2 =
c4d7e58f 414 omap2_cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE2);
f0611a5c 415 cm_context.pll_cm_clksel4 =
c4d7e58f 416 omap2_cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKSEL4);
f0611a5c 417 cm_context.pll_cm_clksel5 =
c4d7e58f 418 omap2_cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKSEL5);
f0611a5c 419 cm_context.pll_cm_clken2 =
c4d7e58f 420 omap2_cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKEN2);
b21be7bc
TK		 421 cm_context.cm_polctrl =
422 omap2_cm_read_mod_reg(OCP_MOD, OMAP3430_CM_POLCTRL);
f0611a5c 423 cm_context.iva2_cm_fclken =
c4d7e58f
PW		 424 omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_FCLKEN);
425 cm_context.iva2_cm_clken_pll =
426 omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKEN_PLL);
f0611a5c 427 cm_context.core_cm_fclken1 =
c4d7e58f 428 omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
f0611a5c 429 cm_context.core_cm_fclken3 =
c4d7e58f 430 omap2_cm_read_mod_reg(CORE_MOD, OMAP3430ES2_CM_FCLKEN3);
f0611a5c 431 cm_context.sgx_cm_fclken =
c4d7e58f 432 omap2_cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_FCLKEN);
f0611a5c 433 cm_context.wkup_cm_fclken =
c4d7e58f 434 omap2_cm_read_mod_reg(WKUP_MOD, CM_FCLKEN);
f0611a5c 435 cm_context.dss_cm_fclken =
c4d7e58f 436 omap2_cm_read_mod_reg(OMAP3430_DSS_MOD, CM_FCLKEN);
f0611a5c 437 cm_context.cam_cm_fclken =
c4d7e58f 438 omap2_cm_read_mod_reg(OMAP3430_CAM_MOD, CM_FCLKEN);
f0611a5c 439 cm_context.per_cm_fclken =
c4d7e58f 440 omap2_cm_read_mod_reg(OMAP3430_PER_MOD, CM_FCLKEN);
f0611a5c 441 cm_context.usbhost_cm_fclken =
c4d7e58f 442 omap2_cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN);
f0611a5c 443 cm_context.core_cm_iclken1 =
c4d7e58f 444 omap2_cm_read_mod_reg(CORE_MOD, CM_ICLKEN1);
f0611a5c 445 cm_context.core_cm_iclken2 =
c4d7e58f 446 omap2_cm_read_mod_reg(CORE_MOD, CM_ICLKEN2);
f0611a5c 447 cm_context.core_cm_iclken3 =
c4d7e58f 448 omap2_cm_read_mod_reg(CORE_MOD, CM_ICLKEN3);
f0611a5c 449 cm_context.sgx_cm_iclken =
c4d7e58f 450 omap2_cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_ICLKEN);
f0611a5c 451 cm_context.wkup_cm_iclken =
c4d7e58f 452 omap2_cm_read_mod_reg(WKUP_MOD, CM_ICLKEN);
f0611a5c 453 cm_context.dss_cm_iclken =
c4d7e58f 454 omap2_cm_read_mod_reg(OMAP3430_DSS_MOD, CM_ICLKEN);
f0611a5c 455 cm_context.cam_cm_iclken =
c4d7e58f 456 omap2_cm_read_mod_reg(OMAP3430_CAM_MOD, CM_ICLKEN);
f0611a5c 457 cm_context.per_cm_iclken =
c4d7e58f 458 omap2_cm_read_mod_reg(OMAP3430_PER_MOD, CM_ICLKEN);
f0611a5c 459 cm_context.usbhost_cm_iclken =
c4d7e58f 460 omap2_cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN);
f0611a5c 461 cm_context.iva2_cm_autoidle2 =
c4d7e58f 462 omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_AUTOIDLE2);
f0611a5c 463 cm_context.mpu_cm_autoidle2 =
c4d7e58f 464 omap2_cm_read_mod_reg(MPU_MOD, CM_AUTOIDLE2);
f0611a5c 465 cm_context.iva2_cm_clkstctrl =
c4d7e58f 466 omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP2_CM_CLKSTCTRL);
f0611a5c 467 cm_context.mpu_cm_clkstctrl =
c4d7e58f 468 omap2_cm_read_mod_reg(MPU_MOD, OMAP2_CM_CLKSTCTRL);
f0611a5c 469 cm_context.core_cm_clkstctrl =
c4d7e58f 470 omap2_cm_read_mod_reg(CORE_MOD, OMAP2_CM_CLKSTCTRL);
f0611a5c 471 cm_context.sgx_cm_clkstctrl =
c4d7e58f 472 omap2_cm_read_mod_reg(OMAP3430ES2_SGX_MOD, OMAP2_CM_CLKSTCTRL);
f0611a5c 473 cm_context.dss_cm_clkstctrl =
c4d7e58f 474 omap2_cm_read_mod_reg(OMAP3430_DSS_MOD, OMAP2_CM_CLKSTCTRL);
f0611a5c 475 cm_context.cam_cm_clkstctrl =
c4d7e58f 476 omap2_cm_read_mod_reg(OMAP3430_CAM_MOD, OMAP2_CM_CLKSTCTRL);
f0611a5c 477 cm_context.per_cm_clkstctrl =
c4d7e58f 478 omap2_cm_read_mod_reg(OMAP3430_PER_MOD, OMAP2_CM_CLKSTCTRL);
f0611a5c 479 cm_context.neon_cm_clkstctrl =
c4d7e58f 480 omap2_cm_read_mod_reg(OMAP3430_NEON_MOD, OMAP2_CM_CLKSTCTRL);
f0611a5c 481 cm_context.usbhost_cm_clkstctrl =
c4d7e58f
PW		 482 omap2_cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD,
483 OMAP2_CM_CLKSTCTRL);
f0611a5c 484 cm_context.core_cm_autoidle1 =
c4d7e58f 485 omap2_cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE1);
f0611a5c 486 cm_context.core_cm_autoidle2 =
c4d7e58f 487 omap2_cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE2);
f0611a5c 488 cm_context.core_cm_autoidle3 =
c4d7e58f 489 omap2_cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE3);
f0611a5c 490 cm_context.wkup_cm_autoidle =
c4d7e58f 491 omap2_cm_read_mod_reg(WKUP_MOD, CM_AUTOIDLE);
f0611a5c 492 cm_context.dss_cm_autoidle =
c4d7e58f 493 omap2_cm_read_mod_reg(OMAP3430_DSS_MOD, CM_AUTOIDLE);
f0611a5c 494 cm_context.cam_cm_autoidle =
c4d7e58f 495 omap2_cm_read_mod_reg(OMAP3430_CAM_MOD, CM_AUTOIDLE);
f0611a5c 496 cm_context.per_cm_autoidle =
c4d7e58f 497 omap2_cm_read_mod_reg(OMAP3430_PER_MOD, CM_AUTOIDLE);
f0611a5c 498 cm_context.usbhost_cm_autoidle =
c4d7e58f 499 omap2_cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_AUTOIDLE);
f0611a5c 500 cm_context.sgx_cm_sleepdep =
c4d7e58f
PW		 501 omap2_cm_read_mod_reg(OMAP3430ES2_SGX_MOD,
502 OMAP3430_CM_SLEEPDEP);
f0611a5c 503 cm_context.dss_cm_sleepdep =
c4d7e58f 504 omap2_cm_read_mod_reg(OMAP3430_DSS_MOD, OMAP3430_CM_SLEEPDEP);
f0611a5c 505 cm_context.cam_cm_sleepdep =
c4d7e58f 506 omap2_cm_read_mod_reg(OMAP3430_CAM_MOD, OMAP3430_CM_SLEEPDEP);
f0611a5c 507 cm_context.per_cm_sleepdep =
c4d7e58f 508 omap2_cm_read_mod_reg(OMAP3430_PER_MOD, OMAP3430_CM_SLEEPDEP);
f0611a5c 509 cm_context.usbhost_cm_sleepdep =
c4d7e58f
PW		 510 omap2_cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD,
511 OMAP3430_CM_SLEEPDEP);
f0611a5c 512 cm_context.cm_clkout_ctrl =
c4d7e58f
PW		 513 omap2_cm_read_mod_reg(OMAP3430_CCR_MOD,
514 OMAP3_CM_CLKOUT_CTRL_OFFSET);
f0611a5c
PW		 515}
516
517void omap3_cm_restore_context(void)
518{
c4d7e58f
PW		 519 omap2_cm_write_mod_reg(cm_context.iva2_cm_clksel1, OMAP3430_IVA2_MOD,
520 CM_CLKSEL1);
521 omap2_cm_write_mod_reg(cm_context.iva2_cm_clksel2, OMAP3430_IVA2_MOD,
522 CM_CLKSEL2);
b21be7bc
TK		 523 omap2_cm_write_mod_reg(cm_context.cm_sysconfig, OCP_MOD,
524 OMAP3430_CM_SYSCONFIG);
c4d7e58f
PW		 525 omap2_cm_write_mod_reg(cm_context.sgx_cm_clksel, OMAP3430ES2_SGX_MOD,
526 CM_CLKSEL);
527 omap2_cm_write_mod_reg(cm_context.dss_cm_clksel, OMAP3430_DSS_MOD,
528 CM_CLKSEL);
529 omap2_cm_write_mod_reg(cm_context.cam_cm_clksel, OMAP3430_CAM_MOD,
530 CM_CLKSEL);
531 omap2_cm_write_mod_reg(cm_context.per_cm_clksel, OMAP3430_PER_MOD,
532 CM_CLKSEL);
533 omap2_cm_write_mod_reg(cm_context.emu_cm_clksel, OMAP3430_EMU_MOD,
534 CM_CLKSEL1);
535 omap2_cm_write_mod_reg(cm_context.emu_cm_clkstctrl, OMAP3430_EMU_MOD,
536 OMAP2_CM_CLKSTCTRL);
a8ae645c
EV		 537 /*
538 * As per erratum i671, ROM code does not respect the PER DPLL
539 * programming scheme if CM_AUTOIDLE_PLL.AUTO_PERIPH_DPLL == 1.
540 * In this case, we need to restore AUTO_PERIPH_DPLL by ourselves.
541 */
542 omap2_cm_write_mod_reg(cm_context.pll_cm_autoidle, PLL_MOD,
543 CM_AUTOIDLE);
c4d7e58f
PW		 544 omap2_cm_write_mod_reg(cm_context.pll_cm_autoidle2, PLL_MOD,
545 CM_AUTOIDLE2);
546 omap2_cm_write_mod_reg(cm_context.pll_cm_clksel4, PLL_MOD,
547 OMAP3430ES2_CM_CLKSEL4);
548 omap2_cm_write_mod_reg(cm_context.pll_cm_clksel5, PLL_MOD,
549 OMAP3430ES2_CM_CLKSEL5);
550 omap2_cm_write_mod_reg(cm_context.pll_cm_clken2, PLL_MOD,
551 OMAP3430ES2_CM_CLKEN2);
b21be7bc
TK		 552 omap2_cm_write_mod_reg(cm_context.cm_polctrl, OCP_MOD,
553 OMAP3430_CM_POLCTRL);
c4d7e58f
PW		 554 omap2_cm_write_mod_reg(cm_context.iva2_cm_fclken, OMAP3430_IVA2_MOD,
555 CM_FCLKEN);
556 omap2_cm_write_mod_reg(cm_context.iva2_cm_clken_pll, OMAP3430_IVA2_MOD,
557 OMAP3430_CM_CLKEN_PLL);
558 omap2_cm_write_mod_reg(cm_context.core_cm_fclken1, CORE_MOD,
559 CM_FCLKEN1);
560 omap2_cm_write_mod_reg(cm_context.core_cm_fclken3, CORE_MOD,
561 OMAP3430ES2_CM_FCLKEN3);
562 omap2_cm_write_mod_reg(cm_context.sgx_cm_fclken, OMAP3430ES2_SGX_MOD,
563 CM_FCLKEN);
564 omap2_cm_write_mod_reg(cm_context.wkup_cm_fclken, WKUP_MOD, CM_FCLKEN);
565 omap2_cm_write_mod_reg(cm_context.dss_cm_fclken, OMAP3430_DSS_MOD,
566 CM_FCLKEN);
567 omap2_cm_write_mod_reg(cm_context.cam_cm_fclken, OMAP3430_CAM_MOD,
568 CM_FCLKEN);
569 omap2_cm_write_mod_reg(cm_context.per_cm_fclken, OMAP3430_PER_MOD,
570 CM_FCLKEN);
571 omap2_cm_write_mod_reg(cm_context.usbhost_cm_fclken,
572 OMAP3430ES2_USBHOST_MOD, CM_FCLKEN);
573 omap2_cm_write_mod_reg(cm_context.core_cm_iclken1, CORE_MOD,
574 CM_ICLKEN1);
575 omap2_cm_write_mod_reg(cm_context.core_cm_iclken2, CORE_MOD,
576 CM_ICLKEN2);
577 omap2_cm_write_mod_reg(cm_context.core_cm_iclken3, CORE_MOD,
578 CM_ICLKEN3);
579 omap2_cm_write_mod_reg(cm_context.sgx_cm_iclken, OMAP3430ES2_SGX_MOD,
580 CM_ICLKEN);
581 omap2_cm_write_mod_reg(cm_context.wkup_cm_iclken, WKUP_MOD, CM_ICLKEN);
582 omap2_cm_write_mod_reg(cm_context.dss_cm_iclken, OMAP3430_DSS_MOD,
583 CM_ICLKEN);
584 omap2_cm_write_mod_reg(cm_context.cam_cm_iclken, OMAP3430_CAM_MOD,
585 CM_ICLKEN);
586 omap2_cm_write_mod_reg(cm_context.per_cm_iclken, OMAP3430_PER_MOD,
587 CM_ICLKEN);
588 omap2_cm_write_mod_reg(cm_context.usbhost_cm_iclken,
589 OMAP3430ES2_USBHOST_MOD, CM_ICLKEN);
590 omap2_cm_write_mod_reg(cm_context.iva2_cm_autoidle2, OMAP3430_IVA2_MOD,
591 CM_AUTOIDLE2);
592 omap2_cm_write_mod_reg(cm_context.mpu_cm_autoidle2, MPU_MOD,
593 CM_AUTOIDLE2);
594 omap2_cm_write_mod_reg(cm_context.iva2_cm_clkstctrl, OMAP3430_IVA2_MOD,
595 OMAP2_CM_CLKSTCTRL);
596 omap2_cm_write_mod_reg(cm_context.mpu_cm_clkstctrl, MPU_MOD,
597 OMAP2_CM_CLKSTCTRL);
598 omap2_cm_write_mod_reg(cm_context.core_cm_clkstctrl, CORE_MOD,
599 OMAP2_CM_CLKSTCTRL);
600 omap2_cm_write_mod_reg(cm_context.sgx_cm_clkstctrl, OMAP3430ES2_SGX_MOD,
601 OMAP2_CM_CLKSTCTRL);
602 omap2_cm_write_mod_reg(cm_context.dss_cm_clkstctrl, OMAP3430_DSS_MOD,
603 OMAP2_CM_CLKSTCTRL);
604 omap2_cm_write_mod_reg(cm_context.cam_cm_clkstctrl, OMAP3430_CAM_MOD,
605 OMAP2_CM_CLKSTCTRL);
606 omap2_cm_write_mod_reg(cm_context.per_cm_clkstctrl, OMAP3430_PER_MOD,
607 OMAP2_CM_CLKSTCTRL);
608 omap2_cm_write_mod_reg(cm_context.neon_cm_clkstctrl, OMAP3430_NEON_MOD,
609 OMAP2_CM_CLKSTCTRL);
610 omap2_cm_write_mod_reg(cm_context.usbhost_cm_clkstctrl,
611 OMAP3430ES2_USBHOST_MOD, OMAP2_CM_CLKSTCTRL);
612 omap2_cm_write_mod_reg(cm_context.core_cm_autoidle1, CORE_MOD,
613 CM_AUTOIDLE1);
614 omap2_cm_write_mod_reg(cm_context.core_cm_autoidle2, CORE_MOD,
615 CM_AUTOIDLE2);
616 omap2_cm_write_mod_reg(cm_context.core_cm_autoidle3, CORE_MOD,
617 CM_AUTOIDLE3);
618 omap2_cm_write_mod_reg(cm_context.wkup_cm_autoidle, WKUP_MOD,
619 CM_AUTOIDLE);
620 omap2_cm_write_mod_reg(cm_context.dss_cm_autoidle, OMAP3430_DSS_MOD,
621 CM_AUTOIDLE);
622 omap2_cm_write_mod_reg(cm_context.cam_cm_autoidle, OMAP3430_CAM_MOD,
623 CM_AUTOIDLE);
624 omap2_cm_write_mod_reg(cm_context.per_cm_autoidle, OMAP3430_PER_MOD,
625 CM_AUTOIDLE);
626 omap2_cm_write_mod_reg(cm_context.usbhost_cm_autoidle,
627 OMAP3430ES2_USBHOST_MOD, CM_AUTOIDLE);
628 omap2_cm_write_mod_reg(cm_context.sgx_cm_sleepdep, OMAP3430ES2_SGX_MOD,
629 OMAP3430_CM_SLEEPDEP);
630 omap2_cm_write_mod_reg(cm_context.dss_cm_sleepdep, OMAP3430_DSS_MOD,
631 OMAP3430_CM_SLEEPDEP);
632 omap2_cm_write_mod_reg(cm_context.cam_cm_sleepdep, OMAP3430_CAM_MOD,
633 OMAP3430_CM_SLEEPDEP);
634 omap2_cm_write_mod_reg(cm_context.per_cm_sleepdep, OMAP3430_PER_MOD,
635 OMAP3430_CM_SLEEPDEP);
636 omap2_cm_write_mod_reg(cm_context.usbhost_cm_sleepdep,
637 OMAP3430ES2_USBHOST_MOD, OMAP3430_CM_SLEEPDEP);
638 omap2_cm_write_mod_reg(cm_context.cm_clkout_ctrl, OMAP3430_CCR_MOD,
639 OMAP3_CM_CLKOUT_CTRL_OFFSET);
f0611a5c 640}
c4ceedcb 641
c6a2d839
TK		 642void omap3_cm_save_scratchpad_contents(u32 *ptr)
643{
644 *ptr++ = omap2_cm_read_mod_reg(CORE_MOD, CM_CLKSEL);
645 *ptr++ = omap2_cm_read_mod_reg(WKUP_MOD, CM_CLKSEL);
646 *ptr++ = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKEN);
647
648 /*
649 * As per erratum i671, ROM code does not respect the PER DPLL
650 * programming scheme if CM_AUTOIDLE_PLL..AUTO_PERIPH_DPLL == 1.
651 * Then, in anycase, clear these bits to avoid extra latencies.
652 */
653 *ptr++ = omap2_cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE) &
654 ~OMAP3430_AUTO_PERIPH_DPLL_MASK;
655 *ptr++ = omap2_cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL1_PLL);
656 *ptr++ = omap2_cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL2_PLL);
657 *ptr++ = omap2_cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL3);
658 *ptr++ = omap2_cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKEN_PLL);
659 *ptr++ = omap2_cm_read_mod_reg(MPU_MOD, OMAP3430_CM_AUTOIDLE_PLL);
660 *ptr++ = omap2_cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL);
661 *ptr++ = omap2_cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL);
662}
663
c4ceedcb
PW		 664/*
665 *
666 */
667
668static struct cm_ll_data omap3xxx_cm_ll_data = {
669 .split_idlest_reg = &omap3xxx_cm_split_idlest_reg,
670 .wait_module_ready = &omap3xxx_cm_wait_module_ready,
671};
672
673int __init omap3xxx_cm_init(void)
674{
c4ceedcb
PW		 675 return cm_register(&omap3xxx_cm_ll_data);
676}
677
678static void __exit omap3xxx_cm_exit(void)
679{
7af13637 680 cm_unregister(&omap3xxx_cm_ll_data);
c4ceedcb
PW		 681}
682__exitcall(omap3xxx_cm_exit);
Linux kernel - Deliverables
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