Commit | Line | Data |
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4e65331c TL |
1 | /* |
2 | * Header for code common to all OMAP2+ machines. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify it | |
5 | * under the terms of the GNU General Public License as published by the | |
6 | * Free Software Foundation; either version 2 of the License, or (at your | |
7 | * option) any later version. | |
8 | * | |
9 | * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED | |
10 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF | |
11 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN | |
12 | * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, | |
13 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT | |
14 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF | |
15 | * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON | |
16 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
17 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF | |
18 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
19 | * | |
20 | * You should have received a copy of the GNU General Public License along | |
21 | * with this program; if not, write to the Free Software Foundation, Inc., | |
22 | * 675 Mass Ave, Cambridge, MA 02139, USA. | |
23 | */ | |
24 | ||
25 | #ifndef __ARCH_ARM_MACH_OMAP2PLUS_COMMON_H | |
26 | #define __ARCH_ARM_MACH_OMAP2PLUS_COMMON_H | |
b2b9762f | 27 | #ifndef __ASSEMBLER__ |
4e65331c | 28 | |
ec2c0825 | 29 | #include <linux/irq.h> |
4e65331c | 30 | #include <linux/delay.h> |
3a8761c0 | 31 | #include <linux/i2c.h> |
1ee47b0a | 32 | #include <linux/i2c/twl.h> |
3a8761c0 | 33 | #include <linux/i2c-omap.h> |
7b6d864b | 34 | #include <linux/reboot.h> |
eaacabc0 | 35 | #include <linux/irqchip/irq-omap-intc.h> |
dbc04161 | 36 | |
b2b9762f | 37 | #include <asm/proc-fns.h> |
944e9df1 | 38 | #include <asm/hardware/cache-l2x0.h> |
4e65331c | 39 | |
3a8761c0 | 40 | #include "i2c.h" |
3d82cbbb | 41 | #include "serial.h" |
3a8761c0 | 42 | |
54db6eee | 43 | #include "usb.h" |
dbc04161 | 44 | |
ec2c0825 | 45 | #define OMAP_INTC_START NR_IRQS |
7d7e1eba | 46 | |
bbd707ac SG |
47 | #if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP2) |
48 | int omap2_pm_init(void); | |
49 | #else | |
50 | static inline int omap2_pm_init(void) | |
51 | { | |
52 | return 0; | |
53 | } | |
54 | #endif | |
55 | ||
56 | #if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3) | |
57 | int omap3_pm_init(void); | |
58 | #else | |
59 | static inline int omap3_pm_init(void) | |
60 | { | |
61 | return 0; | |
62 | } | |
63 | #endif | |
64 | ||
6af16a1d | 65 | #if defined(CONFIG_PM) && (defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || defined(CONFIG_SOC_DRA7XX)) |
bbd707ac | 66 | int omap4_pm_init(void); |
de70af49 | 67 | int omap4_pm_init_early(void); |
bbd707ac SG |
68 | #else |
69 | static inline int omap4_pm_init(void) | |
70 | { | |
71 | return 0; | |
72 | } | |
de70af49 NM |
73 | |
74 | static inline int omap4_pm_init_early(void) | |
75 | { | |
76 | return 0; | |
77 | } | |
bbd707ac SG |
78 | #endif |
79 | ||
80 | #ifdef CONFIG_OMAP_MUX | |
81 | int omap_mux_late_init(void); | |
82 | #else | |
83 | static inline int omap_mux_late_init(void) | |
84 | { | |
85 | return 0; | |
86 | } | |
87 | #endif | |
88 | ||
4e65331c TL |
89 | extern void omap2_init_common_infrastructure(void); |
90 | ||
6bb27d73 SW |
91 | extern void omap2_sync32k_timer_init(void); |
92 | extern void omap3_sync32k_timer_init(void); | |
93 | extern void omap3_secure_sync32k_timer_init(void); | |
00ea4d56 | 94 | extern void omap3_gptimer_timer_init(void); |
6bb27d73 | 95 | extern void omap4_local_timer_init(void); |
2ad501cc | 96 | #ifdef CONFIG_CACHE_L2X0 |
b39b14e6 | 97 | int omap_l2_cache_init(void); |
944e9df1 MS |
98 | #define OMAP_L2C_AUX_CTRL (L2C_AUX_CTRL_SHARED_OVERRIDE | \ |
99 | L310_AUX_CTRL_DATA_PREFETCH | \ | |
100 | L310_AUX_CTRL_INSTR_PREFETCH) | |
101 | void omap4_l2c310_write_sec(unsigned long val, unsigned reg); | |
2ad501cc AB |
102 | #else |
103 | static inline int omap_l2_cache_init(void) | |
104 | { | |
105 | return 0; | |
106 | } | |
944e9df1 MS |
107 | |
108 | #define OMAP_L2C_AUX_CTRL 0 | |
109 | #define omap4_l2c310_write_sec NULL | |
2ad501cc | 110 | #endif |
6bb27d73 | 111 | extern void omap5_realtime_timer_init(void); |
4e65331c TL |
112 | |
113 | void omap2420_init_early(void); | |
114 | void omap2430_init_early(void); | |
115 | void omap3430_init_early(void); | |
116 | void omap35xx_init_early(void); | |
117 | void omap3630_init_early(void); | |
118 | void omap3_init_early(void); /* Do not use this one */ | |
ce3fc89a | 119 | void am33xx_init_early(void); |
4e65331c | 120 | void am35xx_init_early(void); |
c27964b5 TL |
121 | void ti814x_init_early(void); |
122 | void ti816x_init_early(void); | |
08f30989 | 123 | void am33xx_init_early(void); |
c5107027 | 124 | void am43xx_init_early(void); |
765e7a06 | 125 | void am43xx_init_late(void); |
4e65331c | 126 | void omap4430_init_early(void); |
05e152c7 | 127 | void omap5_init_early(void); |
bbd707ac SG |
128 | void omap3_init_late(void); /* Do not use this one */ |
129 | void omap4430_init_late(void); | |
130 | void omap2420_init_late(void); | |
131 | void omap2430_init_late(void); | |
132 | void omap3430_init_late(void); | |
133 | void omap35xx_init_late(void); | |
134 | void omap3630_init_late(void); | |
135 | void am35xx_init_late(void); | |
136 | void ti81xx_init_late(void); | |
765e7a06 NM |
137 | void am33xx_init_late(void); |
138 | void omap5_init_late(void); | |
bbd707ac | 139 | int omap2_common_pm_late_init(void); |
a3a9384a | 140 | void dra7xx_init_early(void); |
765e7a06 | 141 | void dra7xx_init_late(void); |
4e65331c | 142 | |
6770b211 RB |
143 | #ifdef CONFIG_SOC_BUS |
144 | void omap_soc_device_init(void); | |
145 | #else | |
146 | static inline void omap_soc_device_init(void) | |
147 | { | |
148 | } | |
149 | #endif | |
150 | ||
2f334a38 | 151 | #if defined(CONFIG_SOC_OMAP2420) || defined(CONFIG_SOC_OMAP2430) |
7b6d864b | 152 | void omap2xxx_restart(enum reboot_mode mode, const char *cmd); |
ecc46cfd | 153 | #else |
7b6d864b | 154 | static inline void omap2xxx_restart(enum reboot_mode mode, const char *cmd) |
2f334a38 PW |
155 | { |
156 | } | |
ecc46cfd | 157 | #endif |
2f334a38 | 158 | |
14e067c1 | 159 | #ifdef CONFIG_SOC_AM33XX |
7b6d864b | 160 | void am33xx_restart(enum reboot_mode mode, const char *cmd); |
14e067c1 | 161 | #else |
7b6d864b | 162 | static inline void am33xx_restart(enum reboot_mode mode, const char *cmd) |
14e067c1 JSB |
163 | { |
164 | } | |
165 | #endif | |
166 | ||
2f334a38 | 167 | #ifdef CONFIG_ARCH_OMAP3 |
7b6d864b | 168 | void omap3xxx_restart(enum reboot_mode mode, const char *cmd); |
2f334a38 | 169 | #else |
7b6d864b | 170 | static inline void omap3xxx_restart(enum reboot_mode mode, const char *cmd) |
2f334a38 PW |
171 | { |
172 | } | |
173 | #endif | |
174 | ||
bc7235c9 TL |
175 | #ifdef CONFIG_SOC_TI81XX |
176 | void ti81xx_restart(enum reboot_mode mode, const char *cmd); | |
177 | #else | |
178 | static inline void ti81xx_restart(enum reboot_mode mode, const char *cmd) | |
179 | { | |
180 | } | |
181 | #endif | |
182 | ||
7abb1a53 NM |
183 | #if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \ |
184 | defined(CONFIG_SOC_DRA7XX) || defined(CONFIG_SOC_AM43XX) | |
7b6d864b | 185 | void omap44xx_restart(enum reboot_mode mode, const char *cmd); |
2f334a38 | 186 | #else |
7b6d864b | 187 | static inline void omap44xx_restart(enum reboot_mode mode, const char *cmd) |
2f334a38 PW |
188 | { |
189 | } | |
190 | #endif | |
191 | ||
3fa60975 RK |
192 | #ifdef CONFIG_OMAP_INTERCONNECT_BARRIER |
193 | void omap_barrier_reserve_memblock(void); | |
194 | void omap_barriers_init(void); | |
195 | #else | |
196 | static inline void omap_barrier_reserve_memblock(void) | |
197 | { | |
198 | } | |
199 | #endif | |
200 | ||
b6a4226c PW |
201 | /* This gets called from mach-omap2/io.c, do not call this */ |
202 | void __init omap2_set_globals_tap(u32 class, void __iomem *tap); | |
203 | ||
204 | void __init omap242x_map_io(void); | |
205 | void __init omap243x_map_io(void); | |
206 | void __init omap3_map_io(void); | |
207 | void __init am33xx_map_io(void); | |
208 | void __init omap4_map_io(void); | |
209 | void __init omap5_map_io(void); | |
ea827ad5 | 210 | void __init dra7xx_map_io(void); |
b6a4226c PW |
211 | void __init ti81xx_map_io(void); |
212 | ||
4e65331c TL |
213 | /** |
214 | * omap_test_timeout - busy-loop, testing a condition | |
215 | * @cond: condition to test until it evaluates to true | |
216 | * @timeout: maximum number of microseconds in the timeout | |
217 | * @index: loop index (integer) | |
218 | * | |
219 | * Loop waiting for @cond to become true or until at least @timeout | |
220 | * microseconds have passed. To use, define some integer @index in the | |
221 | * calling code. After running, if @index == @timeout, then the loop has | |
222 | * timed out. | |
223 | */ | |
224 | #define omap_test_timeout(cond, timeout, index) \ | |
225 | ({ \ | |
226 | for (index = 0; index < timeout; index++) { \ | |
227 | if (cond) \ | |
228 | break; \ | |
229 | udelay(1); \ | |
230 | } \ | |
231 | }) | |
232 | ||
233 | extern struct device *omap2_get_mpuss_device(void); | |
234 | extern struct device *omap2_get_iva_device(void); | |
235 | extern struct device *omap2_get_l3_device(void); | |
236 | extern struct device *omap4_get_dsp_device(void); | |
237 | ||
0fb22a8f | 238 | unsigned int omap4_xlate_irq(unsigned int hwirq); |
c4082d49 | 239 | void omap_gic_of_init(void); |
4e65331c | 240 | |
4e65331c | 241 | #ifdef CONFIG_CACHE_L2X0 |
02afe8a7 | 242 | extern void __iomem *omap4_get_l2cache_base(void); |
4e65331c TL |
243 | #endif |
244 | ||
52fa2120 | 245 | struct device_node; |
52fa2120 | 246 | |
02afe8a7 SS |
247 | #ifdef CONFIG_SMP |
248 | extern void __iomem *omap4_get_scu_base(void); | |
249 | #else | |
250 | static inline void __iomem *omap4_get_scu_base(void) | |
251 | { | |
252 | return NULL; | |
253 | } | |
4e65331c TL |
254 | #endif |
255 | ||
ff999b8a | 256 | extern void gic_dist_disable(void); |
74ed7bdc | 257 | extern void gic_dist_enable(void); |
cd8ce159 CC |
258 | extern bool gic_dist_disabled(void); |
259 | extern void gic_timer_retrigger(void); | |
4e65331c | 260 | extern void omap_smc1(u32 fn, u32 arg); |
501f0c75 | 261 | extern void __iomem *omap4_get_sar_ram_base(void); |
b2b9762f | 262 | extern void omap_do_wfi(void); |
4e65331c TL |
263 | |
264 | #ifdef CONFIG_SMP | |
265 | /* Needed for secondary core boot */ | |
baf4b7d3 SS |
266 | extern void omap4_secondary_startup(void); |
267 | extern void omap4460_secondary_startup(void); | |
4e65331c TL |
268 | extern u32 omap_modify_auxcoreboot0(u32 set_mask, u32 clear_mask); |
269 | extern void omap_auxcoreboot_addr(u32 cpu_addr); | |
270 | extern u32 omap_read_auxcoreboot0(void); | |
06915321 MZ |
271 | |
272 | extern void omap4_cpu_die(unsigned int cpu); | |
273 | ||
274 | extern struct smp_operations omap4_smp_ops; | |
275 | ||
283f708c | 276 | extern void omap5_secondary_startup(void); |
999f934d | 277 | extern void omap5_secondary_hyp_startup(void); |
4e65331c TL |
278 | #endif |
279 | ||
b2b9762f SS |
280 | #if defined(CONFIG_SMP) && defined(CONFIG_PM) |
281 | extern int omap4_mpuss_init(void); | |
282 | extern int omap4_enter_lowpower(unsigned int cpu, unsigned int power_state); | |
283 | extern int omap4_finish_suspend(unsigned long cpu_state); | |
284 | extern void omap4_cpu_resume(void); | |
b5b4f288 | 285 | extern int omap4_hotplug_cpu(unsigned int cpu, unsigned int power_state); |
b2b9762f SS |
286 | #else |
287 | static inline int omap4_enter_lowpower(unsigned int cpu, | |
288 | unsigned int power_state) | |
289 | { | |
290 | cpu_do_idle(); | |
291 | return 0; | |
292 | } | |
293 | ||
b5b4f288 SS |
294 | static inline int omap4_hotplug_cpu(unsigned int cpu, unsigned int power_state) |
295 | { | |
296 | cpu_do_idle(); | |
297 | return 0; | |
298 | } | |
299 | ||
b2b9762f SS |
300 | static inline int omap4_mpuss_init(void) |
301 | { | |
302 | return 0; | |
303 | } | |
304 | ||
305 | static inline int omap4_finish_suspend(unsigned long cpu_state) | |
306 | { | |
307 | return 0; | |
308 | } | |
309 | ||
310 | static inline void omap4_cpu_resume(void) | |
311 | {} | |
3ba2a739 | 312 | |
b2b9762f | 313 | #endif |
258ee922 | 314 | |
31957609 | 315 | void pdata_quirks_init(const struct of_device_id *); |
dad12d11 | 316 | void omap_auxdata_legacy_init(struct device *dev); |
8651bd8c | 317 | void omap_pcs_legacy_init(int irq, void (*rearm)(void)); |
6a08e1e6 | 318 | |
258ee922 TL |
319 | struct omap_sdrc_params; |
320 | extern void omap_sdrc_init(struct omap_sdrc_params *sdrc_cs0, | |
321 | struct omap_sdrc_params *sdrc_cs1); | |
1ee47b0a | 322 | struct omap2_hsmmc_info; |
f583f0f2 | 323 | extern void omap_reserve(void); |
258ee922 | 324 | |
5c2e8852 TL |
325 | struct omap_hwmod; |
326 | extern int omap_dss_reset(struct omap_hwmod *); | |
258ee922 | 327 | |
ff931c82 | 328 | /* SoC specific clock initializer */ |
cfa9667d | 329 | int omap_clk_init(void); |
ff931c82 | 330 | |
dcdf407b | 331 | int __init omapdss_init_of(void); |
6a0e6b38 | 332 | void __init omapdss_early_init_of(void); |
dcdf407b | 333 | |
b2b9762f | 334 | #endif /* __ASSEMBLER__ */ |
4e65331c | 335 | #endif /* __ARCH_ARM_MACH_OMAP2PLUS_COMMON_H */ |