[deliverable/linux.git] / arch / arm / mach-omap2 / common.h

/*
 * Header for code common to all OMAP2+ machines.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License as published by the
 * Free Software Foundation; either version 2 of the License, or (at your
 * option) any later version.
 *
 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 * You should have received a copy of the  GNU General Public License along
 * with this program; if not, write  to the Free Software Foundation, Inc.,
 * 675 Mass Ave, Cambridge, MA 02139, USA.
 */

#ifndef __ARCH_ARM_MACH_OMAP2PLUS_COMMON_H
#define __ARCH_ARM_MACH_OMAP2PLUS_COMMON_H
#ifndef __ASSEMBLER__

#include <linux/irq.h>
#include <linux/delay.h>
#include <linux/i2c.h>
#include <linux/i2c/twl.h>
#include <linux/i2c-omap.h>
#include <linux/reboot.h>

#include <asm/proc-fns.h>

#include "i2c.h"
#include "serial.h"

#include "usb.h"

#define OMAP_INTC_START		NR_IRQS

#if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP2)
int omap2_pm_init(void);
#else
static inline int omap2_pm_init(void)
{
	return 0;
}
#endif

#if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3)
int omap3_pm_init(void);
#else
static inline int omap3_pm_init(void)
{
	return 0;
}
#endif

#if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP4)
int omap4_pm_init(void);
int omap4_pm_init_early(void);
#else
static inline int omap4_pm_init(void)
{
	return 0;
}

static inline int omap4_pm_init_early(void)
{
	return 0;
}
#endif

#ifdef CONFIG_OMAP_MUX
int omap_mux_late_init(void);
#else
static inline int omap_mux_late_init(void)
{
	return 0;
}
#endif

extern void omap2_init_common_infrastructure(void);

extern void omap2_sync32k_timer_init(void);
extern void omap3_sync32k_timer_init(void);
extern void omap3_secure_sync32k_timer_init(void);
extern void omap3_gptimer_timer_init(void);
extern void omap4_local_timer_init(void);
#ifdef CONFIG_CACHE_L2X0
int omap_l2_cache_init(void);
#else
static inline int omap_l2_cache_init(void)
{
	return 0;
}
#endif
extern void omap5_realtime_timer_init(void);

void omap2420_init_early(void);
void omap2430_init_early(void);
void omap3430_init_early(void);
void omap35xx_init_early(void);
void omap3630_init_early(void);
void omap3_init_early(void);	/* Do not use this one */
void am33xx_init_early(void);
void am35xx_init_early(void);
void ti81xx_init_early(void);
void am33xx_init_early(void);
void am43xx_init_early(void);
void am43xx_init_late(void);
void omap4430_init_early(void);
void omap5_init_early(void);
void omap3_init_late(void);	/* Do not use this one */
void omap4430_init_late(void);
void omap2420_init_late(void);
void omap2430_init_late(void);
void omap3430_init_late(void);
void omap35xx_init_late(void);
void omap3630_init_late(void);
void am35xx_init_late(void);
void ti81xx_init_late(void);
void am33xx_init_late(void);
void omap5_init_late(void);
int omap2_common_pm_late_init(void);
void dra7xx_init_early(void);
void dra7xx_init_late(void);

#ifdef CONFIG_SOC_BUS
void omap_soc_device_init(void);
#else
static inline void omap_soc_device_init(void)
{
}
#endif

#if defined(CONFIG_SOC_OMAP2420) || defined(CONFIG_SOC_OMAP2430)
void omap2xxx_restart(enum reboot_mode mode, const char *cmd);
#else
static inline void omap2xxx_restart(enum reboot_mode mode, const char *cmd)
{
}
#endif

#ifdef CONFIG_SOC_AM33XX
void am33xx_restart(enum reboot_mode mode, const char *cmd);
#else
static inline void am33xx_restart(enum reboot_mode mode, const char *cmd)
{
}
#endif

#ifdef CONFIG_ARCH_OMAP3
void omap3xxx_restart(enum reboot_mode mode, const char *cmd);
#else
static inline void omap3xxx_restart(enum reboot_mode mode, const char *cmd)
{
}
#endif

#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \
	defined(CONFIG_SOC_DRA7XX) || defined(CONFIG_SOC_AM43XX)
void omap44xx_restart(enum reboot_mode mode, const char *cmd);
#else
static inline void omap44xx_restart(enum reboot_mode mode, const char *cmd)
{
}
#endif

/* This gets called from mach-omap2/io.c, do not call this */
void __init omap2_set_globals_tap(u32 class, void __iomem *tap);

void __init omap242x_map_io(void);
void __init omap243x_map_io(void);
void __init omap3_map_io(void);
void __init am33xx_map_io(void);
void __init omap4_map_io(void);
void __init omap5_map_io(void);
void __init ti81xx_map_io(void);

/* omap_barriers_init() is OMAP4 only */
void omap_barriers_init(void);

/**
 * omap_test_timeout - busy-loop, testing a condition
 * @cond: condition to test until it evaluates to true
 * @timeout: maximum number of microseconds in the timeout
 * @index: loop index (integer)
 *
 * Loop waiting for @cond to become true or until at least @timeout
 * microseconds have passed.  To use, define some integer @index in the
 * calling code.  After running, if @index == @timeout, then the loop has
 * timed out.
 */
#define omap_test_timeout(cond, timeout, index)			\
({								\
	for (index = 0; index < timeout; index++) {		\
		if (cond)					\
			break;					\
		udelay(1);					\
	}							\
})

extern struct device *omap2_get_mpuss_device(void);
extern struct device *omap2_get_iva_device(void);
extern struct device *omap2_get_l3_device(void);
extern struct device *omap4_get_dsp_device(void);

void omap2_init_irq(void);
void omap3_init_irq(void);
void ti81xx_init_irq(void);
extern int omap_irq_pending(void);
void omap_intc_save_context(void);
void omap_intc_restore_context(void);
void omap3_intc_suspend(void);
void omap3_intc_prepare_idle(void);
void omap3_intc_resume_idle(void);
void omap2_intc_handle_irq(struct pt_regs *regs);
void omap3_intc_handle_irq(struct pt_regs *regs);
void omap_intc_of_init(void);
void omap_gic_of_init(void);

#ifdef CONFIG_CACHE_L2X0
extern void __iomem *omap4_get_l2cache_base(void);
#endif

struct device_node;
#ifdef CONFIG_OF
int __init intc_of_init(struct device_node *node,
			     struct device_node *parent);
#else
int __init intc_of_init(struct device_node *node,
			     struct device_node *parent)
{
	return 0;
}
#endif

#ifdef CONFIG_SMP
extern void __iomem *omap4_get_scu_base(void);
#else
static inline void __iomem *omap4_get_scu_base(void)
{
	return NULL;
}
#endif

extern void gic_dist_disable(void);
extern void gic_dist_enable(void);
extern bool gic_dist_disabled(void);
extern void gic_timer_retrigger(void);
extern void omap_smc1(u32 fn, u32 arg);
extern void __iomem *omap4_get_sar_ram_base(void);
extern void omap_do_wfi(void);

#ifdef CONFIG_SMP
/* Needed for secondary core boot */
extern void omap4_secondary_startup(void);
extern void omap4460_secondary_startup(void);
extern u32 omap_modify_auxcoreboot0(u32 set_mask, u32 clear_mask);
extern void omap_auxcoreboot_addr(u32 cpu_addr);
extern u32 omap_read_auxcoreboot0(void);

extern void omap4_cpu_die(unsigned int cpu);

extern struct smp_operations omap4_smp_ops;

extern void omap5_secondary_startup(void);
#endif

#if defined(CONFIG_SMP) && defined(CONFIG_PM)
extern int omap4_mpuss_init(void);
extern int omap4_enter_lowpower(unsigned int cpu, unsigned int power_state);
extern int omap4_finish_suspend(unsigned long cpu_state);
extern void omap4_cpu_resume(void);
extern int omap4_hotplug_cpu(unsigned int cpu, unsigned int power_state);
#else
static inline int omap4_enter_lowpower(unsigned int cpu,
					unsigned int power_state)
{
	cpu_do_idle();
	return 0;
}

static inline int omap4_hotplug_cpu(unsigned int cpu, unsigned int power_state)
{
	cpu_do_idle();
	return 0;
}

static inline int omap4_mpuss_init(void)
{
	return 0;
}

static inline int omap4_finish_suspend(unsigned long cpu_state)
{
	return 0;
}

static inline void omap4_cpu_resume(void)
{}

#endif

void pdata_quirks_init(struct of_device_id *);
void omap_auxdata_legacy_init(struct device *dev);
void omap_pcs_legacy_init(int irq, void (*rearm)(void));

struct omap_sdrc_params;
extern void omap_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
				      struct omap_sdrc_params *sdrc_cs1);
struct omap2_hsmmc_info;
extern void omap_reserve(void);

struct omap_hwmod;
extern int omap_dss_reset(struct omap_hwmod *);

/* SoC specific clock initializer */
int omap_clk_init(void);

int __init omapdss_init_of(void);
void __init omapdss_early_init_of(void);

#endif /* __ASSEMBLER__ */
#endif /* __ARCH_ARM_MACH_OMAP2PLUS_COMMON_H */
Commit	Line	Data
4e65331c TL	1	/*
	2	* Header for code common to all OMAP2+ machines.
	3	*
	4	* This program is free software; you can redistribute it and/or modify it
	5	* under the terms of the GNU General Public License as published by the
	6	* Free Software Foundation; either version 2 of the License, or (at your
	7	* option) any later version.
	8	*
	9	* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
	10	* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
	11	* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
	12	* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
	13	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
	14	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
	15	* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
	16	* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
	17	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
	18	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
	19	*
	20	* You should have received a copy of the GNU General Public License along
	21	* with this program; if not, write to the Free Software Foundation, Inc.,
	22	* 675 Mass Ave, Cambridge, MA 02139, USA.
	23	*/
	24
	25	#ifndef __ARCH_ARM_MACH_OMAP2PLUS_COMMON_H
	26	#define __ARCH_ARM_MACH_OMAP2PLUS_COMMON_H
b2b9762f	27	#ifndef __ASSEMBLER__
4e65331c	28
ec2c0825	29	#include <linux/irq.h>
4e65331c	30	#include <linux/delay.h>
3a8761c0	31	#include <linux/i2c.h>
1ee47b0a	32	#include <linux/i2c/twl.h>
3a8761c0	33	#include <linux/i2c-omap.h>
7b6d864b	34	#include <linux/reboot.h>
dbc04161	35
b2b9762f	36	#include <asm/proc-fns.h>
4e65331c	37
3a8761c0	38	#include "i2c.h"
3d82cbbb	39	#include "serial.h"
3a8761c0	40
54db6eee	41	#include "usb.h"
dbc04161	42
ec2c0825	43	#define OMAP_INTC_START NR_IRQS
7d7e1eba	44
bbd707ac SG	45	#if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP2)
	46	int omap2_pm_init(void);
	47	#else
	48	static inline int omap2_pm_init(void)
	49	{
	50	return 0;
	51	}
	52	#endif
	53
	54	#if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3)
	55	int omap3_pm_init(void);
	56	#else
	57	static inline int omap3_pm_init(void)
	58	{
	59	return 0;
	60	}
	61	#endif
	62
	63	#if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP4)
	64	int omap4_pm_init(void);
de70af49	65	int omap4_pm_init_early(void);
bbd707ac SG	66	#else
	67	static inline int omap4_pm_init(void)
	68	{
	69	return 0;
	70	}
de70af49 NM	71
	72	static inline int omap4_pm_init_early(void)
	73	{
	74	return 0;
	75	}
bbd707ac SG	76	#endif
	77
	78	#ifdef CONFIG_OMAP_MUX
	79	int omap_mux_late_init(void);
	80	#else
	81	static inline int omap_mux_late_init(void)
	82	{
	83	return 0;
	84	}
	85	#endif
	86
4e65331c TL	87	extern void omap2_init_common_infrastructure(void);
4e65331c TL	88
6bb27d73 SW	89	extern void omap2_sync32k_timer_init(void);
	90	extern void omap3_sync32k_timer_init(void);
	91	extern void omap3_secure_sync32k_timer_init(void);
00ea4d56	92	extern void omap3_gptimer_timer_init(void);
6bb27d73	93	extern void omap4_local_timer_init(void);
2ad501cc	94	#ifdef CONFIG_CACHE_L2X0
b39b14e6	95	int omap_l2_cache_init(void);
2ad501cc AB	96	#else
	97	static inline int omap_l2_cache_init(void)
	98	{
	99	return 0;
	100	}
	101	#endif
6bb27d73	102	extern void omap5_realtime_timer_init(void);
4e65331c TL	103
	104	void omap2420_init_early(void);
	105	void omap2430_init_early(void);
	106	void omap3430_init_early(void);
	107	void omap35xx_init_early(void);
	108	void omap3630_init_early(void);
	109	void omap3_init_early(void); /* Do not use this one */
ce3fc89a	110	void am33xx_init_early(void);
4e65331c	111	void am35xx_init_early(void);
a920360f	112	void ti81xx_init_early(void);
08f30989	113	void am33xx_init_early(void);
c5107027	114	void am43xx_init_early(void);
765e7a06	115	void am43xx_init_late(void);
4e65331c	116	void omap4430_init_early(void);
05e152c7	117	void omap5_init_early(void);
bbd707ac SG	118	void omap3_init_late(void); /* Do not use this one */
	119	void omap4430_init_late(void);
	120	void omap2420_init_late(void);
	121	void omap2430_init_late(void);
	122	void omap3430_init_late(void);
	123	void omap35xx_init_late(void);
	124	void omap3630_init_late(void);
	125	void am35xx_init_late(void);
	126	void ti81xx_init_late(void);
765e7a06 NM	127	void am33xx_init_late(void);
765e7a06 NM	128	void omap5_init_late(void);
bbd707ac	129	int omap2_common_pm_late_init(void);
a3a9384a	130	void dra7xx_init_early(void);
765e7a06	131	void dra7xx_init_late(void);
4e65331c	132
6770b211 RB	133	#ifdef CONFIG_SOC_BUS
	134	void omap_soc_device_init(void);
	135	#else
	136	static inline void omap_soc_device_init(void)
	137	{
	138	}
	139	#endif
	140
2f334a38	141	#if defined(CONFIG_SOC_OMAP2420) \|\| defined(CONFIG_SOC_OMAP2430)
7b6d864b	142	void omap2xxx_restart(enum reboot_mode mode, const char *cmd);
ecc46cfd	143	#else
7b6d864b	144	static inline void omap2xxx_restart(enum reboot_mode mode, const char *cmd)
2f334a38 PW	145	{
2f334a38 PW	146	}
ecc46cfd	147	#endif
2f334a38	148
14e067c1	149	#ifdef CONFIG_SOC_AM33XX
7b6d864b	150	void am33xx_restart(enum reboot_mode mode, const char *cmd);
14e067c1	151	#else
7b6d864b	152	static inline void am33xx_restart(enum reboot_mode mode, const char *cmd)
14e067c1 JSB	153	{
	154	}
	155	#endif
	156
2f334a38	157	#ifdef CONFIG_ARCH_OMAP3
7b6d864b	158	void omap3xxx_restart(enum reboot_mode mode, const char *cmd);
2f334a38	159	#else
7b6d864b	160	static inline void omap3xxx_restart(enum reboot_mode mode, const char *cmd)
2f334a38 PW	161	{
	162	}
	163	#endif
	164
7abb1a53 NM	165	#if defined(CONFIG_ARCH_OMAP4) \|\| defined(CONFIG_SOC_OMAP5) \|\| \
7abb1a53 NM	166	defined(CONFIG_SOC_DRA7XX) \|\| defined(CONFIG_SOC_AM43XX)
7b6d864b	167	void omap44xx_restart(enum reboot_mode mode, const char *cmd);
2f334a38	168	#else
7b6d864b	169	static inline void omap44xx_restart(enum reboot_mode mode, const char *cmd)
2f334a38 PW	170	{
	171	}
	172	#endif
	173
b6a4226c PW	174	/* This gets called from mach-omap2/io.c, do not call this */
	175	void __init omap2_set_globals_tap(u32 class, void __iomem *tap);
	176
	177	void __init omap242x_map_io(void);
	178	void __init omap243x_map_io(void);
	179	void __init omap3_map_io(void);
	180	void __init am33xx_map_io(void);
	181	void __init omap4_map_io(void);
	182	void __init omap5_map_io(void);
	183	void __init ti81xx_map_io(void);
	184
	185	/* omap_barriers_init() is OMAP4 only */
2ec1fc4e	186	void omap_barriers_init(void);
4e65331c TL	187
	188	/**
	189	* omap_test_timeout - busy-loop, testing a condition
	190	* @cond: condition to test until it evaluates to true
	191	* @timeout: maximum number of microseconds in the timeout
	192	* @index: loop index (integer)
	193	*
	194	* Loop waiting for @cond to become true or until at least @timeout
	195	* microseconds have passed. To use, define some integer @index in the
	196	* calling code. After running, if @index == @timeout, then the loop has
	197	* timed out.
	198	*/
	199	#define omap_test_timeout(cond, timeout, index) \
	200	({ \
	201	for (index = 0; index < timeout; index++) { \
	202	if (cond) \
	203	break; \
	204	udelay(1); \
	205	} \
	206	})
	207
	208	extern struct device *omap2_get_mpuss_device(void);
	209	extern struct device *omap2_get_iva_device(void);
	210	extern struct device *omap2_get_l3_device(void);
	211	extern struct device *omap4_get_dsp_device(void);
	212
	213	void omap2_init_irq(void);
	214	void omap3_init_irq(void);
a920360f	215	void ti81xx_init_irq(void);
4e65331c TL	216	extern int omap_irq_pending(void);
	217	void omap_intc_save_context(void);
	218	void omap_intc_restore_context(void);
	219	void omap3_intc_suspend(void);
	220	void omap3_intc_prepare_idle(void);
	221	void omap3_intc_resume_idle(void);
f88f4dd8 SS	222	void omap2_intc_handle_irq(struct pt_regs *regs);
f88f4dd8 SS	223	void omap3_intc_handle_irq(struct pt_regs *regs);
c4082d49 S	224	void omap_intc_of_init(void);
c4082d49 S	225	void omap_gic_of_init(void);
4e65331c	226
4e65331c	227	#ifdef CONFIG_CACHE_L2X0
02afe8a7	228	extern void __iomem *omap4_get_l2cache_base(void);
4e65331c TL	229	#endif
4e65331c TL	230
52fa2120 BC	231	struct device_node;
52fa2120 BC	232	#ifdef CONFIG_OF
c4082d49	233	int __init intc_of_init(struct device_node *node,
52fa2120 BC	234	struct device_node *parent);
52fa2120 BC	235	#else
c4082d49	236	int __init intc_of_init(struct device_node *node,
52fa2120 BC	237	struct device_node *parent)
	238	{
	239	return 0;
	240	}
	241	#endif
	242
02afe8a7 SS	243	#ifdef CONFIG_SMP
	244	extern void __iomem *omap4_get_scu_base(void);
	245	#else
	246	static inline void __iomem *omap4_get_scu_base(void)
	247	{
	248	return NULL;
	249	}
4e65331c TL	250	#endif
4e65331c TL	251
ff999b8a	252	extern void gic_dist_disable(void);
74ed7bdc	253	extern void gic_dist_enable(void);
cd8ce159 CC	254	extern bool gic_dist_disabled(void);
cd8ce159 CC	255	extern void gic_timer_retrigger(void);
4e65331c	256	extern void omap_smc1(u32 fn, u32 arg);
501f0c75	257	extern void __iomem *omap4_get_sar_ram_base(void);
b2b9762f	258	extern void omap_do_wfi(void);
4e65331c TL	259
	260	#ifdef CONFIG_SMP
	261	/* Needed for secondary core boot */
baf4b7d3 SS	262	extern void omap4_secondary_startup(void);
baf4b7d3 SS	263	extern void omap4460_secondary_startup(void);
4e65331c TL	264	extern u32 omap_modify_auxcoreboot0(u32 set_mask, u32 clear_mask);
	265	extern void omap_auxcoreboot_addr(u32 cpu_addr);
	266	extern u32 omap_read_auxcoreboot0(void);
06915321 MZ	267
	268	extern void omap4_cpu_die(unsigned int cpu);
	269
	270	extern struct smp_operations omap4_smp_ops;
	271
283f708c	272	extern void omap5_secondary_startup(void);
4e65331c TL	273	#endif
4e65331c TL	274
b2b9762f SS	275	#if defined(CONFIG_SMP) && defined(CONFIG_PM)
	276	extern int omap4_mpuss_init(void);
	277	extern int omap4_enter_lowpower(unsigned int cpu, unsigned int power_state);
	278	extern int omap4_finish_suspend(unsigned long cpu_state);
	279	extern void omap4_cpu_resume(void);
b5b4f288	280	extern int omap4_hotplug_cpu(unsigned int cpu, unsigned int power_state);
b2b9762f SS	281	#else
	282	static inline int omap4_enter_lowpower(unsigned int cpu,
	283	unsigned int power_state)
	284	{
	285	cpu_do_idle();
	286	return 0;
	287	}
	288
b5b4f288 SS	289	static inline int omap4_hotplug_cpu(unsigned int cpu, unsigned int power_state)
	290	{
	291	cpu_do_idle();
	292	return 0;
	293	}
	294
b2b9762f SS	295	static inline int omap4_mpuss_init(void)
	296	{
	297	return 0;
	298	}
	299
	300	static inline int omap4_finish_suspend(unsigned long cpu_state)
	301	{
	302	return 0;
	303	}
	304
	305	static inline void omap4_cpu_resume(void)
	306	{}
3ba2a739	307
b2b9762f	308	#endif
258ee922	309
8651bd8c	310	void pdata_quirks_init(struct of_device_id *);
dad12d11	311	void omap_auxdata_legacy_init(struct device *dev);
8651bd8c	312	void omap_pcs_legacy_init(int irq, void (*rearm)(void));
6a08e1e6	313
258ee922 TL	314	struct omap_sdrc_params;
	315	extern void omap_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
	316	struct omap_sdrc_params *sdrc_cs1);
1ee47b0a	317	struct omap2_hsmmc_info;
f583f0f2	318	extern void omap_reserve(void);
258ee922	319
5c2e8852 TL	320	struct omap_hwmod;
5c2e8852 TL	321	extern int omap_dss_reset(struct omap_hwmod *);
258ee922	322
ff931c82	323	/* SoC specific clock initializer */
cfa9667d	324	int omap_clk_init(void);
ff931c82	325
dcdf407b	326	int __init omapdss_init_of(void);
6a0e6b38	327	void __init omapdss_early_init_of(void);
dcdf407b	328
b2b9762f	329	#endif /* __ASSEMBLER__ */
4e65331c	330	#endif /* __ARCH_ARM_MACH_OMAP2PLUS_COMMON_H */