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Merge branch 'sched-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel...
[deliverable/linux.git] / arch / arm / mach-omap2 / common.h
CommitLineData
4e65331c
TL		 1/*
2 * Header for code common to all OMAP2+ machines.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the
6 * Free Software Foundation; either version 2 of the License, or (at your
7 * option) any later version.
8 *
9 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
10 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
12 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
13 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
14 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
15 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
16 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
17 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
18 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
19 *
20 * You should have received a copy of the GNU General Public License along
21 * with this program; if not, write to the Free Software Foundation, Inc.,
22 * 675 Mass Ave, Cambridge, MA 02139, USA.
23 */
24
25#ifndef __ARCH_ARM_MACH_OMAP2PLUS_COMMON_H
26#define __ARCH_ARM_MACH_OMAP2PLUS_COMMON_H
b2b9762f 27#ifndef __ASSEMBLER__
4e65331c 28
ec2c0825 29#include <linux/irq.h>
4e65331c 30#include <linux/delay.h>
3a8761c0 31#include <linux/i2c.h>
1ee47b0a 32#include <linux/i2c/twl.h>
3a8761c0 33#include <linux/i2c-omap.h>
dbc04161 34
b2b9762f 35#include <asm/proc-fns.h>
4e65331c 36
3a8761c0 37#include "i2c.h"
3d82cbbb 38#include "serial.h"
3a8761c0 39
54db6eee 40#include "usb.h"
dbc04161 41
ec2c0825 42#define OMAP_INTC_START NR_IRQS
7d7e1eba 43
bbd707ac
SG		 44#if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP2)
45int omap2_pm_init(void);
46#else
47static inline int omap2_pm_init(void)
48{
49 return 0;
50}
51#endif
52
53#if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3)
54int omap3_pm_init(void);
55#else
56static inline int omap3_pm_init(void)
57{
58 return 0;
59}
60#endif
61
62#if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP4)
63int omap4_pm_init(void);
64#else
65static inline int omap4_pm_init(void)
66{
67 return 0;
68}
69#endif
70
71#ifdef CONFIG_OMAP_MUX
72int omap_mux_late_init(void);
73#else
74static inline int omap_mux_late_init(void)
75{
76 return 0;
77}
78#endif
79
4e65331c
TL		 80extern void omap2_init_common_infrastructure(void);
81
6bb27d73
SW		 82extern void omap2_sync32k_timer_init(void);
83extern void omap3_sync32k_timer_init(void);
84extern void omap3_secure_sync32k_timer_init(void);
85extern void omap3_gp_gptimer_timer_init(void);
86extern void omap3_am33xx_gptimer_timer_init(void);
87extern void omap4_local_timer_init(void);
88extern void omap5_realtime_timer_init(void);
4e65331c
TL		 89
90void omap2420_init_early(void);
91void omap2430_init_early(void);
92void omap3430_init_early(void);
93void omap35xx_init_early(void);
94void omap3630_init_early(void);
95void omap3_init_early(void); /* Do not use this one */
ce3fc89a 96void am33xx_init_early(void);
4e65331c 97void am35xx_init_early(void);
a920360f 98void ti81xx_init_early(void);
08f30989 99void am33xx_init_early(void);
4e65331c 100void omap4430_init_early(void);
05e152c7 101void omap5_init_early(void);
bbd707ac
SG		 102void omap3_init_late(void); /* Do not use this one */
103void omap4430_init_late(void);
104void omap2420_init_late(void);
105void omap2430_init_late(void);
106void omap3430_init_late(void);
107void omap35xx_init_late(void);
108void omap3630_init_late(void);
109void am35xx_init_late(void);
110void ti81xx_init_late(void);
bbd707ac 111int omap2_common_pm_late_init(void);
4e65331c 112
6770b211
RB		 113#ifdef CONFIG_SOC_BUS
114void omap_soc_device_init(void);
115#else
116static inline void omap_soc_device_init(void)
117{
118}
119#endif
120
2f334a38
PW		 121#if defined(CONFIG_SOC_OMAP2420) || defined(CONFIG_SOC_OMAP2430)
122void omap2xxx_restart(char mode, const char *cmd);
ecc46cfd 123#else
2f334a38
PW		 124static inline void omap2xxx_restart(char mode, const char *cmd)
125{
126}
ecc46cfd 127#endif
2f334a38 128
14e067c1
JSB		 129#ifdef CONFIG_SOC_AM33XX
130void am33xx_restart(char mode, const char *cmd);
131#else
132static inline void am33xx_restart(char mode, const char *cmd)
133{
134}
135#endif
136
2f334a38
PW		 137#ifdef CONFIG_ARCH_OMAP3
138void omap3xxx_restart(char mode, const char *cmd);
139#else
140static inline void omap3xxx_restart(char mode, const char *cmd)
141{
142}
143#endif
144
145#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5)
146void omap44xx_restart(char mode, const char *cmd);
147#else
148static inline void omap44xx_restart(char mode, const char *cmd)
149{
150}
151#endif
152
b6a4226c
PW		 153/* This gets called from mach-omap2/io.c, do not call this */
154void __init omap2_set_globals_tap(u32 class, void __iomem *tap);
155
156void __init omap242x_map_io(void);
157void __init omap243x_map_io(void);
158void __init omap3_map_io(void);
159void __init am33xx_map_io(void);
160void __init omap4_map_io(void);
161void __init omap5_map_io(void);
162void __init ti81xx_map_io(void);
163
164/* omap_barriers_init() is OMAP4 only */
2ec1fc4e 165void omap_barriers_init(void);
4e65331c
TL		 166
167/**
168 * omap_test_timeout - busy-loop, testing a condition
169 * @cond: condition to test until it evaluates to true
170 * @timeout: maximum number of microseconds in the timeout
171 * @index: loop index (integer)
172 *
173 * Loop waiting for @cond to become true or until at least @timeout
174 * microseconds have passed. To use, define some integer @index in the
175 * calling code. After running, if @index == @timeout, then the loop has
176 * timed out.
177 */
178#define omap_test_timeout(cond, timeout, index) \
179({ \
180 for (index = 0; index < timeout; index++) { \
181 if (cond) \
182 break; \
183 udelay(1); \
184 } \
185})
186
187extern struct device *omap2_get_mpuss_device(void);
188extern struct device *omap2_get_iva_device(void);
189extern struct device *omap2_get_l3_device(void);
190extern struct device *omap4_get_dsp_device(void);
191
192void omap2_init_irq(void);
193void omap3_init_irq(void);
a920360f 194void ti81xx_init_irq(void);
4e65331c
TL		 195extern int omap_irq_pending(void);
196void omap_intc_save_context(void);
197void omap_intc_restore_context(void);
198void omap3_intc_suspend(void);
199void omap3_intc_prepare_idle(void);
200void omap3_intc_resume_idle(void);
f88f4dd8
SS		 201void omap2_intc_handle_irq(struct pt_regs *regs);
202void omap3_intc_handle_irq(struct pt_regs *regs);
c4082d49
S		 203void omap_intc_of_init(void);
204void omap_gic_of_init(void);
4e65331c 205
4e65331c 206#ifdef CONFIG_CACHE_L2X0
02afe8a7 207extern void __iomem *omap4_get_l2cache_base(void);
4e65331c
TL		 208#endif
209
52fa2120
BC		 210struct device_node;
211#ifdef CONFIG_OF
c4082d49 212int __init intc_of_init(struct device_node *node,
52fa2120
BC		 213 struct device_node *parent);
214#else
c4082d49 215int __init intc_of_init(struct device_node *node,
52fa2120
BC		 216 struct device_node *parent)
217{
218 return 0;
219}
220#endif
221
02afe8a7
SS		 222#ifdef CONFIG_SMP
223extern void __iomem *omap4_get_scu_base(void);
224#else
225static inline void __iomem *omap4_get_scu_base(void)
226{
227 return NULL;
228}
4e65331c
TL		 229#endif
230
4e65331c 231extern void __init gic_init_irq(void);
ff999b8a 232extern void gic_dist_disable(void);
cd8ce159
CC		 233extern bool gic_dist_disabled(void);
234extern void gic_timer_retrigger(void);
4e65331c 235extern void omap_smc1(u32 fn, u32 arg);
501f0c75 236extern void __iomem *omap4_get_sar_ram_base(void);
b2b9762f 237extern void omap_do_wfi(void);
4e65331c
TL		 238
239#ifdef CONFIG_SMP
240/* Needed for secondary core boot */
241extern void omap_secondary_startup(void);
ff999b8a 242extern void omap_secondary_startup_4460(void);
4e65331c
TL		 243extern u32 omap_modify_auxcoreboot0(u32 set_mask, u32 clear_mask);
244extern void omap_auxcoreboot_addr(u32 cpu_addr);
245extern u32 omap_read_auxcoreboot0(void);
06915321
MZ		 246
247extern void omap4_cpu_die(unsigned int cpu);
248
249extern struct smp_operations omap4_smp_ops;
250
283f708c 251extern void omap5_secondary_startup(void);
4e65331c
TL		 252#endif
253
b2b9762f
SS		 254#if defined(CONFIG_SMP) && defined(CONFIG_PM)
255extern int omap4_mpuss_init(void);
256extern int omap4_enter_lowpower(unsigned int cpu, unsigned int power_state);
257extern int omap4_finish_suspend(unsigned long cpu_state);
258extern void omap4_cpu_resume(void);
b5b4f288 259extern int omap4_hotplug_cpu(unsigned int cpu, unsigned int power_state);
b2b9762f
SS		 260#else
261static inline int omap4_enter_lowpower(unsigned int cpu,
262 unsigned int power_state)
263{
264 cpu_do_idle();
265 return 0;
266}
267
b5b4f288
SS		 268static inline int omap4_hotplug_cpu(unsigned int cpu, unsigned int power_state)
269{
270 cpu_do_idle();
271 return 0;
272}
273
b2b9762f
SS		 274static inline int omap4_mpuss_init(void)
275{
276 return 0;
277}
278
279static inline int omap4_finish_suspend(unsigned long cpu_state)
280{
281 return 0;
282}
283
284static inline void omap4_cpu_resume(void)
285{}
3ba2a739 286
b2b9762f 287#endif
258ee922
TL		 288
289struct omap_sdrc_params;
290extern void omap_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
291 struct omap_sdrc_params *sdrc_cs1);
1ee47b0a
B		 292struct omap2_hsmmc_info;
293extern int omap4_twl6030_hsmmc_init(struct omap2_hsmmc_info *controllers);
f583f0f2 294extern void omap_reserve(void);
258ee922 295
5c2e8852
TL		 296struct omap_hwmod;
297extern int omap_dss_reset(struct omap_hwmod *);
258ee922 298
ff931c82
RN		 299/* SoC specific clock initializer */
300extern int (*omap_clk_init)(void);
301
b2b9762f 302#endif /* __ASSEMBLER__ */
4e65331c 303#endif /* __ARCH_ARM_MACH_OMAP2PLUS_COMMON_H */
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