arm: omap: irq: drop omap3_intc_handle_irq()
[deliverable/linux.git] / arch / arm / mach-omap2 / common.h
CommitLineData
4e65331c
TL
1/*
2 * Header for code common to all OMAP2+ machines.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the
6 * Free Software Foundation; either version 2 of the License, or (at your
7 * option) any later version.
8 *
9 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
10 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
12 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
13 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
14 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
15 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
16 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
17 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
18 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
19 *
20 * You should have received a copy of the GNU General Public License along
21 * with this program; if not, write to the Free Software Foundation, Inc.,
22 * 675 Mass Ave, Cambridge, MA 02139, USA.
23 */
24
25#ifndef __ARCH_ARM_MACH_OMAP2PLUS_COMMON_H
26#define __ARCH_ARM_MACH_OMAP2PLUS_COMMON_H
b2b9762f 27#ifndef __ASSEMBLER__
4e65331c 28
ec2c0825 29#include <linux/irq.h>
4e65331c 30#include <linux/delay.h>
3a8761c0 31#include <linux/i2c.h>
1ee47b0a 32#include <linux/i2c/twl.h>
3a8761c0 33#include <linux/i2c-omap.h>
7b6d864b 34#include <linux/reboot.h>
dbc04161 35
b2b9762f 36#include <asm/proc-fns.h>
4e65331c 37
3a8761c0 38#include "i2c.h"
3d82cbbb 39#include "serial.h"
3a8761c0 40
54db6eee 41#include "usb.h"
dbc04161 42
ec2c0825 43#define OMAP_INTC_START NR_IRQS
7d7e1eba 44
bbd707ac
SG
45#if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP2)
46int omap2_pm_init(void);
47#else
48static inline int omap2_pm_init(void)
49{
50 return 0;
51}
52#endif
53
54#if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3)
55int omap3_pm_init(void);
56#else
57static inline int omap3_pm_init(void)
58{
59 return 0;
60}
61#endif
62
6af16a1d 63#if defined(CONFIG_PM) && (defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || defined(CONFIG_SOC_DRA7XX))
bbd707ac 64int omap4_pm_init(void);
de70af49 65int omap4_pm_init_early(void);
bbd707ac
SG
66#else
67static inline int omap4_pm_init(void)
68{
69 return 0;
70}
de70af49
NM
71
72static inline int omap4_pm_init_early(void)
73{
74 return 0;
75}
bbd707ac
SG
76#endif
77
78#ifdef CONFIG_OMAP_MUX
79int omap_mux_late_init(void);
80#else
81static inline int omap_mux_late_init(void)
82{
83 return 0;
84}
85#endif
86
4e65331c
TL
87extern void omap2_init_common_infrastructure(void);
88
6bb27d73
SW
89extern void omap2_sync32k_timer_init(void);
90extern void omap3_sync32k_timer_init(void);
91extern void omap3_secure_sync32k_timer_init(void);
00ea4d56 92extern void omap3_gptimer_timer_init(void);
6bb27d73 93extern void omap4_local_timer_init(void);
2ad501cc 94#ifdef CONFIG_CACHE_L2X0
b39b14e6 95int omap_l2_cache_init(void);
2ad501cc
AB
96#else
97static inline int omap_l2_cache_init(void)
98{
99 return 0;
100}
101#endif
6bb27d73 102extern void omap5_realtime_timer_init(void);
4e65331c
TL
103
104void omap2420_init_early(void);
105void omap2430_init_early(void);
106void omap3430_init_early(void);
107void omap35xx_init_early(void);
108void omap3630_init_early(void);
109void omap3_init_early(void); /* Do not use this one */
ce3fc89a 110void am33xx_init_early(void);
4e65331c 111void am35xx_init_early(void);
a920360f 112void ti81xx_init_early(void);
08f30989 113void am33xx_init_early(void);
c5107027 114void am43xx_init_early(void);
765e7a06 115void am43xx_init_late(void);
4e65331c 116void omap4430_init_early(void);
05e152c7 117void omap5_init_early(void);
bbd707ac
SG
118void omap3_init_late(void); /* Do not use this one */
119void omap4430_init_late(void);
120void omap2420_init_late(void);
121void omap2430_init_late(void);
122void omap3430_init_late(void);
123void omap35xx_init_late(void);
124void omap3630_init_late(void);
125void am35xx_init_late(void);
126void ti81xx_init_late(void);
765e7a06
NM
127void am33xx_init_late(void);
128void omap5_init_late(void);
bbd707ac 129int omap2_common_pm_late_init(void);
a3a9384a 130void dra7xx_init_early(void);
765e7a06 131void dra7xx_init_late(void);
4e65331c 132
6770b211
RB
133#ifdef CONFIG_SOC_BUS
134void omap_soc_device_init(void);
135#else
136static inline void omap_soc_device_init(void)
137{
138}
139#endif
140
2f334a38 141#if defined(CONFIG_SOC_OMAP2420) || defined(CONFIG_SOC_OMAP2430)
7b6d864b 142void omap2xxx_restart(enum reboot_mode mode, const char *cmd);
ecc46cfd 143#else
7b6d864b 144static inline void omap2xxx_restart(enum reboot_mode mode, const char *cmd)
2f334a38
PW
145{
146}
ecc46cfd 147#endif
2f334a38 148
14e067c1 149#ifdef CONFIG_SOC_AM33XX
7b6d864b 150void am33xx_restart(enum reboot_mode mode, const char *cmd);
14e067c1 151#else
7b6d864b 152static inline void am33xx_restart(enum reboot_mode mode, const char *cmd)
14e067c1
JSB
153{
154}
155#endif
156
2f334a38 157#ifdef CONFIG_ARCH_OMAP3
7b6d864b 158void omap3xxx_restart(enum reboot_mode mode, const char *cmd);
2f334a38 159#else
7b6d864b 160static inline void omap3xxx_restart(enum reboot_mode mode, const char *cmd)
2f334a38
PW
161{
162}
163#endif
164
7abb1a53
NM
165#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \
166 defined(CONFIG_SOC_DRA7XX) || defined(CONFIG_SOC_AM43XX)
7b6d864b 167void omap44xx_restart(enum reboot_mode mode, const char *cmd);
2f334a38 168#else
7b6d864b 169static inline void omap44xx_restart(enum reboot_mode mode, const char *cmd)
2f334a38
PW
170{
171}
172#endif
173
b6a4226c
PW
174/* This gets called from mach-omap2/io.c, do not call this */
175void __init omap2_set_globals_tap(u32 class, void __iomem *tap);
176
177void __init omap242x_map_io(void);
178void __init omap243x_map_io(void);
179void __init omap3_map_io(void);
180void __init am33xx_map_io(void);
181void __init omap4_map_io(void);
182void __init omap5_map_io(void);
183void __init ti81xx_map_io(void);
184
185/* omap_barriers_init() is OMAP4 only */
2ec1fc4e 186void omap_barriers_init(void);
4e65331c
TL
187
188/**
189 * omap_test_timeout - busy-loop, testing a condition
190 * @cond: condition to test until it evaluates to true
191 * @timeout: maximum number of microseconds in the timeout
192 * @index: loop index (integer)
193 *
194 * Loop waiting for @cond to become true or until at least @timeout
195 * microseconds have passed. To use, define some integer @index in the
196 * calling code. After running, if @index == @timeout, then the loop has
197 * timed out.
198 */
199#define omap_test_timeout(cond, timeout, index) \
200({ \
201 for (index = 0; index < timeout; index++) { \
202 if (cond) \
203 break; \
204 udelay(1); \
205 } \
206})
207
208extern struct device *omap2_get_mpuss_device(void);
209extern struct device *omap2_get_iva_device(void);
210extern struct device *omap2_get_l3_device(void);
211extern struct device *omap4_get_dsp_device(void);
212
213void omap2_init_irq(void);
214void omap3_init_irq(void);
a920360f 215void ti81xx_init_irq(void);
4e65331c
TL
216extern int omap_irq_pending(void);
217void omap_intc_save_context(void);
218void omap_intc_restore_context(void);
219void omap3_intc_suspend(void);
220void omap3_intc_prepare_idle(void);
221void omap3_intc_resume_idle(void);
f88f4dd8 222void omap2_intc_handle_irq(struct pt_regs *regs);
c4082d49 223void omap_gic_of_init(void);
4e65331c 224
4e65331c 225#ifdef CONFIG_CACHE_L2X0
02afe8a7 226extern void __iomem *omap4_get_l2cache_base(void);
4e65331c
TL
227#endif
228
52fa2120 229struct device_node;
52fa2120 230
02afe8a7
SS
231#ifdef CONFIG_SMP
232extern void __iomem *omap4_get_scu_base(void);
233#else
234static inline void __iomem *omap4_get_scu_base(void)
235{
236 return NULL;
237}
4e65331c
TL
238#endif
239
ff999b8a 240extern void gic_dist_disable(void);
74ed7bdc 241extern void gic_dist_enable(void);
cd8ce159
CC
242extern bool gic_dist_disabled(void);
243extern void gic_timer_retrigger(void);
4e65331c 244extern void omap_smc1(u32 fn, u32 arg);
501f0c75 245extern void __iomem *omap4_get_sar_ram_base(void);
b2b9762f 246extern void omap_do_wfi(void);
4e65331c
TL
247
248#ifdef CONFIG_SMP
249/* Needed for secondary core boot */
baf4b7d3
SS
250extern void omap4_secondary_startup(void);
251extern void omap4460_secondary_startup(void);
4e65331c
TL
252extern u32 omap_modify_auxcoreboot0(u32 set_mask, u32 clear_mask);
253extern void omap_auxcoreboot_addr(u32 cpu_addr);
254extern u32 omap_read_auxcoreboot0(void);
06915321
MZ
255
256extern void omap4_cpu_die(unsigned int cpu);
257
258extern struct smp_operations omap4_smp_ops;
259
283f708c 260extern void omap5_secondary_startup(void);
4e65331c
TL
261#endif
262
b2b9762f
SS
263#if defined(CONFIG_SMP) && defined(CONFIG_PM)
264extern int omap4_mpuss_init(void);
265extern int omap4_enter_lowpower(unsigned int cpu, unsigned int power_state);
266extern int omap4_finish_suspend(unsigned long cpu_state);
267extern void omap4_cpu_resume(void);
b5b4f288 268extern int omap4_hotplug_cpu(unsigned int cpu, unsigned int power_state);
b2b9762f
SS
269#else
270static inline int omap4_enter_lowpower(unsigned int cpu,
271 unsigned int power_state)
272{
273 cpu_do_idle();
274 return 0;
275}
276
b5b4f288
SS
277static inline int omap4_hotplug_cpu(unsigned int cpu, unsigned int power_state)
278{
279 cpu_do_idle();
280 return 0;
281}
282
b2b9762f
SS
283static inline int omap4_mpuss_init(void)
284{
285 return 0;
286}
287
288static inline int omap4_finish_suspend(unsigned long cpu_state)
289{
290 return 0;
291}
292
293static inline void omap4_cpu_resume(void)
294{}
3ba2a739 295
b2b9762f 296#endif
258ee922 297
31957609 298void pdata_quirks_init(const struct of_device_id *);
dad12d11 299void omap_auxdata_legacy_init(struct device *dev);
8651bd8c 300void omap_pcs_legacy_init(int irq, void (*rearm)(void));
6a08e1e6 301
258ee922
TL
302struct omap_sdrc_params;
303extern void omap_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
304 struct omap_sdrc_params *sdrc_cs1);
1ee47b0a 305struct omap2_hsmmc_info;
f583f0f2 306extern void omap_reserve(void);
258ee922 307
5c2e8852
TL
308struct omap_hwmod;
309extern int omap_dss_reset(struct omap_hwmod *);
258ee922 310
ff931c82 311/* SoC specific clock initializer */
cfa9667d 312int omap_clk_init(void);
ff931c82 313
dcdf407b 314int __init omapdss_init_of(void);
6a0e6b38 315void __init omapdss_early_init_of(void);
dcdf407b 316
b2b9762f 317#endif /* __ASSEMBLER__ */
4e65331c 318#endif /* __ARCH_ARM_MACH_OMAP2PLUS_COMMON_H */
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