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4e65331c TL |
1 | /* |
2 | * Header for code common to all OMAP2+ machines. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify it | |
5 | * under the terms of the GNU General Public License as published by the | |
6 | * Free Software Foundation; either version 2 of the License, or (at your | |
7 | * option) any later version. | |
8 | * | |
9 | * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED | |
10 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF | |
11 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN | |
12 | * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, | |
13 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT | |
14 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF | |
15 | * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON | |
16 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
17 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF | |
18 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
19 | * | |
20 | * You should have received a copy of the GNU General Public License along | |
21 | * with this program; if not, write to the Free Software Foundation, Inc., | |
22 | * 675 Mass Ave, Cambridge, MA 02139, USA. | |
23 | */ | |
24 | ||
25 | #ifndef __ARCH_ARM_MACH_OMAP2PLUS_COMMON_H | |
26 | #define __ARCH_ARM_MACH_OMAP2PLUS_COMMON_H | |
b2b9762f | 27 | #ifndef __ASSEMBLER__ |
4e65331c TL |
28 | |
29 | #include <linux/delay.h> | |
1ee47b0a | 30 | #include <linux/i2c/twl.h> |
4e65331c | 31 | #include <plat/common.h> |
b2b9762f | 32 | #include <asm/proc-fns.h> |
4e65331c TL |
33 | |
34 | #ifdef CONFIG_SOC_OMAP2420 | |
35 | extern void omap242x_map_common_io(void); | |
36 | #else | |
37 | static inline void omap242x_map_common_io(void) | |
38 | { | |
39 | } | |
40 | #endif | |
41 | ||
42 | #ifdef CONFIG_SOC_OMAP2430 | |
43 | extern void omap243x_map_common_io(void); | |
44 | #else | |
45 | static inline void omap243x_map_common_io(void) | |
46 | { | |
47 | } | |
48 | #endif | |
49 | ||
50 | #ifdef CONFIG_ARCH_OMAP3 | |
51 | extern void omap34xx_map_common_io(void); | |
52 | #else | |
53 | static inline void omap34xx_map_common_io(void) | |
54 | { | |
55 | } | |
56 | #endif | |
57 | ||
33959553 | 58 | #ifdef CONFIG_SOC_TI81XX |
a920360f | 59 | extern void omapti81xx_map_common_io(void); |
4e65331c | 60 | #else |
a920360f | 61 | static inline void omapti81xx_map_common_io(void) |
4e65331c TL |
62 | { |
63 | } | |
64 | #endif | |
65 | ||
bb6abcf4 | 66 | #ifdef CONFIG_SOC_AM33XX |
1e6cb146 AM |
67 | extern void omapam33xx_map_common_io(void); |
68 | #else | |
69 | static inline void omapam33xx_map_common_io(void) | |
70 | { | |
71 | } | |
72 | #endif | |
73 | ||
4e65331c TL |
74 | #ifdef CONFIG_ARCH_OMAP4 |
75 | extern void omap44xx_map_common_io(void); | |
76 | #else | |
77 | static inline void omap44xx_map_common_io(void) | |
78 | { | |
79 | } | |
80 | #endif | |
81 | ||
bbd707ac SG |
82 | #if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP2) |
83 | int omap2_pm_init(void); | |
84 | #else | |
85 | static inline int omap2_pm_init(void) | |
86 | { | |
87 | return 0; | |
88 | } | |
89 | #endif | |
90 | ||
91 | #if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3) | |
92 | int omap3_pm_init(void); | |
93 | #else | |
94 | static inline int omap3_pm_init(void) | |
95 | { | |
96 | return 0; | |
97 | } | |
98 | #endif | |
99 | ||
100 | #if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP4) | |
101 | int omap4_pm_init(void); | |
102 | #else | |
103 | static inline int omap4_pm_init(void) | |
104 | { | |
105 | return 0; | |
106 | } | |
107 | #endif | |
108 | ||
109 | #ifdef CONFIG_OMAP_MUX | |
110 | int omap_mux_late_init(void); | |
111 | #else | |
112 | static inline int omap_mux_late_init(void) | |
113 | { | |
114 | return 0; | |
115 | } | |
116 | #endif | |
117 | ||
4e65331c TL |
118 | extern void omap2_init_common_infrastructure(void); |
119 | ||
120 | extern struct sys_timer omap2_timer; | |
121 | extern struct sys_timer omap3_timer; | |
122 | extern struct sys_timer omap3_secure_timer; | |
08f30989 | 123 | extern struct sys_timer omap3_am33xx_timer; |
4e65331c TL |
124 | extern struct sys_timer omap4_timer; |
125 | ||
126 | void omap2420_init_early(void); | |
127 | void omap2430_init_early(void); | |
128 | void omap3430_init_early(void); | |
129 | void omap35xx_init_early(void); | |
130 | void omap3630_init_early(void); | |
131 | void omap3_init_early(void); /* Do not use this one */ | |
132 | void am35xx_init_early(void); | |
a920360f | 133 | void ti81xx_init_early(void); |
08f30989 | 134 | void am33xx_init_early(void); |
4e65331c | 135 | void omap4430_init_early(void); |
bbd707ac SG |
136 | void omap3_init_late(void); /* Do not use this one */ |
137 | void omap4430_init_late(void); | |
138 | void omap2420_init_late(void); | |
139 | void omap2430_init_late(void); | |
140 | void omap3430_init_late(void); | |
141 | void omap35xx_init_late(void); | |
142 | void omap3630_init_late(void); | |
143 | void am35xx_init_late(void); | |
144 | void ti81xx_init_late(void); | |
145 | void omap4430_init_late(void); | |
146 | int omap2_common_pm_late_init(void); | |
baa95883 | 147 | void omap_prcm_restart(char, const char *); |
4e65331c TL |
148 | |
149 | /* | |
150 | * IO bases for various OMAP processors | |
151 | * Except the tap base, rest all the io bases | |
152 | * listed are physical addresses. | |
153 | */ | |
154 | struct omap_globals { | |
155 | u32 class; /* OMAP class to detect */ | |
156 | void __iomem *tap; /* Control module ID code */ | |
157 | void __iomem *sdrc; /* SDRAM Controller */ | |
158 | void __iomem *sms; /* SDRAM Memory Scheduler */ | |
159 | void __iomem *ctrl; /* System Control Module */ | |
160 | void __iomem *ctrl_pad; /* PAD Control Module */ | |
161 | void __iomem *prm; /* Power and Reset Management */ | |
162 | void __iomem *cm; /* Clock Management */ | |
163 | void __iomem *cm2; | |
610eb8c2 | 164 | void __iomem *prcm_mpu; |
4e65331c TL |
165 | }; |
166 | ||
167 | void omap2_set_globals_242x(void); | |
168 | void omap2_set_globals_243x(void); | |
169 | void omap2_set_globals_3xxx(void); | |
170 | void omap2_set_globals_443x(void); | |
a920360f | 171 | void omap2_set_globals_ti81xx(void); |
1e6cb146 | 172 | void omap2_set_globals_am33xx(void); |
4e65331c TL |
173 | |
174 | /* These get called from omap2_set_globals_xxxx(), do not call these */ | |
175 | void omap2_set_globals_tap(struct omap_globals *); | |
176 | void omap2_set_globals_sdrc(struct omap_globals *); | |
177 | void omap2_set_globals_control(struct omap_globals *); | |
178 | void omap2_set_globals_prcm(struct omap_globals *); | |
179 | ||
180 | void omap242x_map_io(void); | |
181 | void omap243x_map_io(void); | |
182 | void omap3_map_io(void); | |
1e6cb146 | 183 | void am33xx_map_io(void); |
4e65331c | 184 | void omap4_map_io(void); |
a920360f | 185 | void ti81xx_map_io(void); |
2ec1fc4e | 186 | void omap_barriers_init(void); |
4e65331c TL |
187 | |
188 | /** | |
189 | * omap_test_timeout - busy-loop, testing a condition | |
190 | * @cond: condition to test until it evaluates to true | |
191 | * @timeout: maximum number of microseconds in the timeout | |
192 | * @index: loop index (integer) | |
193 | * | |
194 | * Loop waiting for @cond to become true or until at least @timeout | |
195 | * microseconds have passed. To use, define some integer @index in the | |
196 | * calling code. After running, if @index == @timeout, then the loop has | |
197 | * timed out. | |
198 | */ | |
199 | #define omap_test_timeout(cond, timeout, index) \ | |
200 | ({ \ | |
201 | for (index = 0; index < timeout; index++) { \ | |
202 | if (cond) \ | |
203 | break; \ | |
204 | udelay(1); \ | |
205 | } \ | |
206 | }) | |
207 | ||
208 | extern struct device *omap2_get_mpuss_device(void); | |
209 | extern struct device *omap2_get_iva_device(void); | |
210 | extern struct device *omap2_get_l3_device(void); | |
211 | extern struct device *omap4_get_dsp_device(void); | |
212 | ||
213 | void omap2_init_irq(void); | |
214 | void omap3_init_irq(void); | |
a920360f | 215 | void ti81xx_init_irq(void); |
4e65331c TL |
216 | extern int omap_irq_pending(void); |
217 | void omap_intc_save_context(void); | |
218 | void omap_intc_restore_context(void); | |
219 | void omap3_intc_suspend(void); | |
220 | void omap3_intc_prepare_idle(void); | |
221 | void omap3_intc_resume_idle(void); | |
f88f4dd8 SS |
222 | void omap2_intc_handle_irq(struct pt_regs *regs); |
223 | void omap3_intc_handle_irq(struct pt_regs *regs); | |
4e65331c | 224 | |
4e65331c | 225 | #ifdef CONFIG_CACHE_L2X0 |
02afe8a7 | 226 | extern void __iomem *omap4_get_l2cache_base(void); |
4e65331c TL |
227 | #endif |
228 | ||
52fa2120 BC |
229 | struct device_node; |
230 | #ifdef CONFIG_OF | |
231 | int __init omap_intc_of_init(struct device_node *node, | |
232 | struct device_node *parent); | |
233 | #else | |
234 | int __init omap_intc_of_init(struct device_node *node, | |
235 | struct device_node *parent) | |
236 | { | |
237 | return 0; | |
238 | } | |
239 | #endif | |
240 | ||
02afe8a7 SS |
241 | #ifdef CONFIG_SMP |
242 | extern void __iomem *omap4_get_scu_base(void); | |
243 | #else | |
244 | static inline void __iomem *omap4_get_scu_base(void) | |
245 | { | |
246 | return NULL; | |
247 | } | |
4e65331c TL |
248 | #endif |
249 | ||
4e65331c TL |
250 | extern void __init gic_init_irq(void); |
251 | extern void omap_smc1(u32 fn, u32 arg); | |
501f0c75 | 252 | extern void __iomem *omap4_get_sar_ram_base(void); |
b2b9762f | 253 | extern void omap_do_wfi(void); |
4e65331c TL |
254 | |
255 | #ifdef CONFIG_SMP | |
256 | /* Needed for secondary core boot */ | |
257 | extern void omap_secondary_startup(void); | |
258 | extern u32 omap_modify_auxcoreboot0(u32 set_mask, u32 clear_mask); | |
259 | extern void omap_auxcoreboot_addr(u32 cpu_addr); | |
260 | extern u32 omap_read_auxcoreboot0(void); | |
261 | #endif | |
262 | ||
b2b9762f SS |
263 | #if defined(CONFIG_SMP) && defined(CONFIG_PM) |
264 | extern int omap4_mpuss_init(void); | |
265 | extern int omap4_enter_lowpower(unsigned int cpu, unsigned int power_state); | |
266 | extern int omap4_finish_suspend(unsigned long cpu_state); | |
267 | extern void omap4_cpu_resume(void); | |
b5b4f288 | 268 | extern int omap4_hotplug_cpu(unsigned int cpu, unsigned int power_state); |
3ba2a739 | 269 | extern u32 omap4_mpuss_read_prev_context_state(void); |
b2b9762f SS |
270 | #else |
271 | static inline int omap4_enter_lowpower(unsigned int cpu, | |
272 | unsigned int power_state) | |
273 | { | |
274 | cpu_do_idle(); | |
275 | return 0; | |
276 | } | |
277 | ||
b5b4f288 SS |
278 | static inline int omap4_hotplug_cpu(unsigned int cpu, unsigned int power_state) |
279 | { | |
280 | cpu_do_idle(); | |
281 | return 0; | |
282 | } | |
283 | ||
b2b9762f SS |
284 | static inline int omap4_mpuss_init(void) |
285 | { | |
286 | return 0; | |
287 | } | |
288 | ||
289 | static inline int omap4_finish_suspend(unsigned long cpu_state) | |
290 | { | |
291 | return 0; | |
292 | } | |
293 | ||
294 | static inline void omap4_cpu_resume(void) | |
295 | {} | |
3ba2a739 SS |
296 | |
297 | static inline u32 omap4_mpuss_read_prev_context_state(void) | |
298 | { | |
299 | return 0; | |
300 | } | |
b2b9762f | 301 | #endif |
258ee922 TL |
302 | |
303 | struct omap_sdrc_params; | |
304 | extern void omap_sdrc_init(struct omap_sdrc_params *sdrc_cs0, | |
305 | struct omap_sdrc_params *sdrc_cs1); | |
1ee47b0a B |
306 | struct omap2_hsmmc_info; |
307 | extern int omap4_twl6030_hsmmc_init(struct omap2_hsmmc_info *controllers); | |
258ee922 | 308 | |
b2b9762f | 309 | #endif /* __ASSEMBLER__ */ |
4e65331c | 310 | #endif /* __ARCH_ARM_MACH_OMAP2PLUS_COMMON_H */ |