ARM: OMAP2+: PRCM: create SoC-specific chip restart functions
[deliverable/linux.git] / arch / arm / mach-omap2 / common.h
CommitLineData
4e65331c
TL
1/*
2 * Header for code common to all OMAP2+ machines.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the
6 * Free Software Foundation; either version 2 of the License, or (at your
7 * option) any later version.
8 *
9 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
10 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
12 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
13 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
14 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
15 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
16 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
17 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
18 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
19 *
20 * You should have received a copy of the GNU General Public License along
21 * with this program; if not, write to the Free Software Foundation, Inc.,
22 * 675 Mass Ave, Cambridge, MA 02139, USA.
23 */
24
25#ifndef __ARCH_ARM_MACH_OMAP2PLUS_COMMON_H
26#define __ARCH_ARM_MACH_OMAP2PLUS_COMMON_H
b2b9762f 27#ifndef __ASSEMBLER__
4e65331c 28
ec2c0825 29#include <linux/irq.h>
4e65331c 30#include <linux/delay.h>
3a8761c0 31#include <linux/i2c.h>
1ee47b0a 32#include <linux/i2c/twl.h>
3a8761c0 33#include <linux/i2c-omap.h>
dbc04161 34
b2b9762f 35#include <asm/proc-fns.h>
4e65331c 36
e6a6e5ad 37#include "../plat-omap/common.h"
dbc04161 38
3a8761c0 39#include "i2c.h"
3d82cbbb 40#include "serial.h"
3a8761c0 41
54db6eee
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42#include "usb.h"
43
ec2c0825 44#define OMAP_INTC_START NR_IRQS
7d7e1eba 45
bbd707ac
SG
46#if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP2)
47int omap2_pm_init(void);
48#else
49static inline int omap2_pm_init(void)
50{
51 return 0;
52}
53#endif
54
55#if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3)
56int omap3_pm_init(void);
57#else
58static inline int omap3_pm_init(void)
59{
60 return 0;
61}
62#endif
63
64#if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP4)
65int omap4_pm_init(void);
66#else
67static inline int omap4_pm_init(void)
68{
69 return 0;
70}
71#endif
72
73#ifdef CONFIG_OMAP_MUX
74int omap_mux_late_init(void);
75#else
76static inline int omap_mux_late_init(void)
77{
78 return 0;
79}
80#endif
81
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TL
82extern void omap2_init_common_infrastructure(void);
83
84extern struct sys_timer omap2_timer;
85extern struct sys_timer omap3_timer;
86extern struct sys_timer omap3_secure_timer;
08f30989 87extern struct sys_timer omap3_am33xx_timer;
4e65331c 88extern struct sys_timer omap4_timer;
37b3280d 89extern struct sys_timer omap5_timer;
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90
91void omap2420_init_early(void);
92void omap2430_init_early(void);
93void omap3430_init_early(void);
94void omap35xx_init_early(void);
95void omap3630_init_early(void);
96void omap3_init_early(void); /* Do not use this one */
ce3fc89a 97void am33xx_init_early(void);
4e65331c 98void am35xx_init_early(void);
a920360f 99void ti81xx_init_early(void);
08f30989 100void am33xx_init_early(void);
4e65331c 101void omap4430_init_early(void);
05e152c7 102void omap5_init_early(void);
bbd707ac
SG
103void omap3_init_late(void); /* Do not use this one */
104void omap4430_init_late(void);
105void omap2420_init_late(void);
106void omap2430_init_late(void);
107void omap3430_init_late(void);
108void omap35xx_init_late(void);
109void omap3630_init_late(void);
110void am35xx_init_late(void);
111void ti81xx_init_late(void);
112void omap4430_init_late(void);
113int omap2_common_pm_late_init(void);
baa95883 114void omap_prcm_restart(char, const char *);
4e65331c 115
2f334a38
PW
116#if defined(CONFIG_SOC_OMAP2420) || defined(CONFIG_SOC_OMAP2430)
117void omap2xxx_restart(char mode, const char *cmd);
118#else
119static inline void omap2xxx_restart(char mode, const char *cmd)
120{
121}
122#endif
123
124#ifdef CONFIG_ARCH_OMAP3
125void omap3xxx_restart(char mode, const char *cmd);
126#else
127static inline void omap3xxx_restart(char mode, const char *cmd)
128{
129}
130#endif
131
132#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5)
133void omap44xx_restart(char mode, const char *cmd);
134#else
135static inline void omap44xx_restart(char mode, const char *cmd)
136{
137}
138#endif
139
b6a4226c
PW
140/* This gets called from mach-omap2/io.c, do not call this */
141void __init omap2_set_globals_tap(u32 class, void __iomem *tap);
142
143void __init omap242x_map_io(void);
144void __init omap243x_map_io(void);
145void __init omap3_map_io(void);
146void __init am33xx_map_io(void);
147void __init omap4_map_io(void);
148void __init omap5_map_io(void);
149void __init ti81xx_map_io(void);
150
151/* omap_barriers_init() is OMAP4 only */
2ec1fc4e 152void omap_barriers_init(void);
4e65331c
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153
154/**
155 * omap_test_timeout - busy-loop, testing a condition
156 * @cond: condition to test until it evaluates to true
157 * @timeout: maximum number of microseconds in the timeout
158 * @index: loop index (integer)
159 *
160 * Loop waiting for @cond to become true or until at least @timeout
161 * microseconds have passed. To use, define some integer @index in the
162 * calling code. After running, if @index == @timeout, then the loop has
163 * timed out.
164 */
165#define omap_test_timeout(cond, timeout, index) \
166({ \
167 for (index = 0; index < timeout; index++) { \
168 if (cond) \
169 break; \
170 udelay(1); \
171 } \
172})
173
174extern struct device *omap2_get_mpuss_device(void);
175extern struct device *omap2_get_iva_device(void);
176extern struct device *omap2_get_l3_device(void);
177extern struct device *omap4_get_dsp_device(void);
178
179void omap2_init_irq(void);
180void omap3_init_irq(void);
a920360f 181void ti81xx_init_irq(void);
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182extern int omap_irq_pending(void);
183void omap_intc_save_context(void);
184void omap_intc_restore_context(void);
185void omap3_intc_suspend(void);
186void omap3_intc_prepare_idle(void);
187void omap3_intc_resume_idle(void);
f88f4dd8
SS
188void omap2_intc_handle_irq(struct pt_regs *regs);
189void omap3_intc_handle_irq(struct pt_regs *regs);
c4082d49
S
190void omap_intc_of_init(void);
191void omap_gic_of_init(void);
4e65331c 192
4e65331c 193#ifdef CONFIG_CACHE_L2X0
02afe8a7 194extern void __iomem *omap4_get_l2cache_base(void);
4e65331c
TL
195#endif
196
52fa2120
BC
197struct device_node;
198#ifdef CONFIG_OF
c4082d49 199int __init intc_of_init(struct device_node *node,
52fa2120
BC
200 struct device_node *parent);
201#else
c4082d49 202int __init intc_of_init(struct device_node *node,
52fa2120
BC
203 struct device_node *parent)
204{
205 return 0;
206}
207#endif
208
02afe8a7
SS
209#ifdef CONFIG_SMP
210extern void __iomem *omap4_get_scu_base(void);
211#else
212static inline void __iomem *omap4_get_scu_base(void)
213{
214 return NULL;
215}
4e65331c
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216#endif
217
4e65331c
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218extern void __init gic_init_irq(void);
219extern void omap_smc1(u32 fn, u32 arg);
501f0c75 220extern void __iomem *omap4_get_sar_ram_base(void);
b2b9762f 221extern void omap_do_wfi(void);
4e65331c
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222
223#ifdef CONFIG_SMP
224/* Needed for secondary core boot */
225extern void omap_secondary_startup(void);
226extern u32 omap_modify_auxcoreboot0(u32 set_mask, u32 clear_mask);
227extern void omap_auxcoreboot_addr(u32 cpu_addr);
228extern u32 omap_read_auxcoreboot0(void);
06915321
MZ
229
230extern void omap4_cpu_die(unsigned int cpu);
231
232extern struct smp_operations omap4_smp_ops;
233
283f708c 234extern void omap5_secondary_startup(void);
4e65331c
TL
235#endif
236
b2b9762f
SS
237#if defined(CONFIG_SMP) && defined(CONFIG_PM)
238extern int omap4_mpuss_init(void);
239extern int omap4_enter_lowpower(unsigned int cpu, unsigned int power_state);
240extern int omap4_finish_suspend(unsigned long cpu_state);
241extern void omap4_cpu_resume(void);
b5b4f288 242extern int omap4_hotplug_cpu(unsigned int cpu, unsigned int power_state);
3ba2a739 243extern u32 omap4_mpuss_read_prev_context_state(void);
b2b9762f
SS
244#else
245static inline int omap4_enter_lowpower(unsigned int cpu,
246 unsigned int power_state)
247{
248 cpu_do_idle();
249 return 0;
250}
251
b5b4f288
SS
252static inline int omap4_hotplug_cpu(unsigned int cpu, unsigned int power_state)
253{
254 cpu_do_idle();
255 return 0;
256}
257
b2b9762f
SS
258static inline int omap4_mpuss_init(void)
259{
260 return 0;
261}
262
263static inline int omap4_finish_suspend(unsigned long cpu_state)
264{
265 return 0;
266}
267
268static inline void omap4_cpu_resume(void)
269{}
3ba2a739
SS
270
271static inline u32 omap4_mpuss_read_prev_context_state(void)
272{
273 return 0;
274}
b2b9762f 275#endif
258ee922
TL
276
277struct omap_sdrc_params;
278extern void omap_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
279 struct omap_sdrc_params *sdrc_cs1);
1ee47b0a
B
280struct omap2_hsmmc_info;
281extern int omap4_twl6030_hsmmc_init(struct omap2_hsmmc_info *controllers);
f583f0f2 282extern void omap_reserve(void);
258ee922 283
b2b9762f 284#endif /* __ASSEMBLER__ */
4e65331c 285#endif /* __ARCH_ARM_MACH_OMAP2PLUS_COMMON_H */
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