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4e65331c TL |
1 | /* |
2 | * Header for code common to all OMAP2+ machines. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify it | |
5 | * under the terms of the GNU General Public License as published by the | |
6 | * Free Software Foundation; either version 2 of the License, or (at your | |
7 | * option) any later version. | |
8 | * | |
9 | * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED | |
10 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF | |
11 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN | |
12 | * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, | |
13 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT | |
14 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF | |
15 | * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON | |
16 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
17 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF | |
18 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
19 | * | |
20 | * You should have received a copy of the GNU General Public License along | |
21 | * with this program; if not, write to the Free Software Foundation, Inc., | |
22 | * 675 Mass Ave, Cambridge, MA 02139, USA. | |
23 | */ | |
24 | ||
25 | #ifndef __ARCH_ARM_MACH_OMAP2PLUS_COMMON_H | |
26 | #define __ARCH_ARM_MACH_OMAP2PLUS_COMMON_H | |
b2b9762f | 27 | #ifndef __ASSEMBLER__ |
4e65331c TL |
28 | |
29 | #include <linux/delay.h> | |
30 | #include <plat/common.h> | |
b2b9762f | 31 | #include <asm/proc-fns.h> |
4e65331c TL |
32 | |
33 | #ifdef CONFIG_SOC_OMAP2420 | |
34 | extern void omap242x_map_common_io(void); | |
35 | #else | |
36 | static inline void omap242x_map_common_io(void) | |
37 | { | |
38 | } | |
39 | #endif | |
40 | ||
41 | #ifdef CONFIG_SOC_OMAP2430 | |
42 | extern void omap243x_map_common_io(void); | |
43 | #else | |
44 | static inline void omap243x_map_common_io(void) | |
45 | { | |
46 | } | |
47 | #endif | |
48 | ||
49 | #ifdef CONFIG_ARCH_OMAP3 | |
50 | extern void omap34xx_map_common_io(void); | |
51 | #else | |
52 | static inline void omap34xx_map_common_io(void) | |
53 | { | |
54 | } | |
55 | #endif | |
56 | ||
a920360f HP |
57 | #ifdef CONFIG_SOC_OMAPTI81XX |
58 | extern void omapti81xx_map_common_io(void); | |
4e65331c | 59 | #else |
a920360f | 60 | static inline void omapti81xx_map_common_io(void) |
4e65331c TL |
61 | { |
62 | } | |
63 | #endif | |
64 | ||
1e6cb146 AM |
65 | #ifdef CONFIG_SOC_OMAPAM33XX |
66 | extern void omapam33xx_map_common_io(void); | |
67 | #else | |
68 | static inline void omapam33xx_map_common_io(void) | |
69 | { | |
70 | } | |
71 | #endif | |
72 | ||
4e65331c TL |
73 | #ifdef CONFIG_ARCH_OMAP4 |
74 | extern void omap44xx_map_common_io(void); | |
75 | #else | |
76 | static inline void omap44xx_map_common_io(void) | |
77 | { | |
78 | } | |
79 | #endif | |
80 | ||
81 | extern void omap2_init_common_infrastructure(void); | |
82 | ||
83 | extern struct sys_timer omap2_timer; | |
84 | extern struct sys_timer omap3_timer; | |
85 | extern struct sys_timer omap3_secure_timer; | |
86 | extern struct sys_timer omap4_timer; | |
87 | ||
88 | void omap2420_init_early(void); | |
89 | void omap2430_init_early(void); | |
90 | void omap3430_init_early(void); | |
91 | void omap35xx_init_early(void); | |
92 | void omap3630_init_early(void); | |
93 | void omap3_init_early(void); /* Do not use this one */ | |
94 | void am35xx_init_early(void); | |
a920360f | 95 | void ti81xx_init_early(void); |
4e65331c | 96 | void omap4430_init_early(void); |
baa95883 | 97 | void omap_prcm_restart(char, const char *); |
4e65331c TL |
98 | |
99 | /* | |
100 | * IO bases for various OMAP processors | |
101 | * Except the tap base, rest all the io bases | |
102 | * listed are physical addresses. | |
103 | */ | |
104 | struct omap_globals { | |
105 | u32 class; /* OMAP class to detect */ | |
106 | void __iomem *tap; /* Control module ID code */ | |
107 | void __iomem *sdrc; /* SDRAM Controller */ | |
108 | void __iomem *sms; /* SDRAM Memory Scheduler */ | |
109 | void __iomem *ctrl; /* System Control Module */ | |
110 | void __iomem *ctrl_pad; /* PAD Control Module */ | |
111 | void __iomem *prm; /* Power and Reset Management */ | |
112 | void __iomem *cm; /* Clock Management */ | |
113 | void __iomem *cm2; | |
610eb8c2 | 114 | void __iomem *prcm_mpu; |
4e65331c TL |
115 | }; |
116 | ||
117 | void omap2_set_globals_242x(void); | |
118 | void omap2_set_globals_243x(void); | |
119 | void omap2_set_globals_3xxx(void); | |
120 | void omap2_set_globals_443x(void); | |
a920360f | 121 | void omap2_set_globals_ti81xx(void); |
1e6cb146 | 122 | void omap2_set_globals_am33xx(void); |
4e65331c TL |
123 | |
124 | /* These get called from omap2_set_globals_xxxx(), do not call these */ | |
125 | void omap2_set_globals_tap(struct omap_globals *); | |
126 | void omap2_set_globals_sdrc(struct omap_globals *); | |
127 | void omap2_set_globals_control(struct omap_globals *); | |
128 | void omap2_set_globals_prcm(struct omap_globals *); | |
129 | ||
130 | void omap242x_map_io(void); | |
131 | void omap243x_map_io(void); | |
132 | void omap3_map_io(void); | |
1e6cb146 | 133 | void am33xx_map_io(void); |
4e65331c | 134 | void omap4_map_io(void); |
a920360f | 135 | void ti81xx_map_io(void); |
2ec1fc4e | 136 | void omap_barriers_init(void); |
4e65331c | 137 | |
a4f34197 TL |
138 | extern void __init omap_init_consistent_dma_size(void); |
139 | ||
4e65331c TL |
140 | /** |
141 | * omap_test_timeout - busy-loop, testing a condition | |
142 | * @cond: condition to test until it evaluates to true | |
143 | * @timeout: maximum number of microseconds in the timeout | |
144 | * @index: loop index (integer) | |
145 | * | |
146 | * Loop waiting for @cond to become true or until at least @timeout | |
147 | * microseconds have passed. To use, define some integer @index in the | |
148 | * calling code. After running, if @index == @timeout, then the loop has | |
149 | * timed out. | |
150 | */ | |
151 | #define omap_test_timeout(cond, timeout, index) \ | |
152 | ({ \ | |
153 | for (index = 0; index < timeout; index++) { \ | |
154 | if (cond) \ | |
155 | break; \ | |
156 | udelay(1); \ | |
157 | } \ | |
158 | }) | |
159 | ||
160 | extern struct device *omap2_get_mpuss_device(void); | |
161 | extern struct device *omap2_get_iva_device(void); | |
162 | extern struct device *omap2_get_l3_device(void); | |
163 | extern struct device *omap4_get_dsp_device(void); | |
164 | ||
165 | void omap2_init_irq(void); | |
166 | void omap3_init_irq(void); | |
a920360f | 167 | void ti81xx_init_irq(void); |
4e65331c TL |
168 | extern int omap_irq_pending(void); |
169 | void omap_intc_save_context(void); | |
170 | void omap_intc_restore_context(void); | |
171 | void omap3_intc_suspend(void); | |
172 | void omap3_intc_prepare_idle(void); | |
173 | void omap3_intc_resume_idle(void); | |
f88f4dd8 SS |
174 | void omap2_intc_handle_irq(struct pt_regs *regs); |
175 | void omap3_intc_handle_irq(struct pt_regs *regs); | |
4e65331c | 176 | |
4e65331c | 177 | #ifdef CONFIG_CACHE_L2X0 |
02afe8a7 | 178 | extern void __iomem *omap4_get_l2cache_base(void); |
4e65331c TL |
179 | #endif |
180 | ||
52fa2120 BC |
181 | struct device_node; |
182 | #ifdef CONFIG_OF | |
183 | int __init omap_intc_of_init(struct device_node *node, | |
184 | struct device_node *parent); | |
185 | #else | |
186 | int __init omap_intc_of_init(struct device_node *node, | |
187 | struct device_node *parent) | |
188 | { | |
189 | return 0; | |
190 | } | |
191 | #endif | |
192 | ||
02afe8a7 SS |
193 | #ifdef CONFIG_SMP |
194 | extern void __iomem *omap4_get_scu_base(void); | |
195 | #else | |
196 | static inline void __iomem *omap4_get_scu_base(void) | |
197 | { | |
198 | return NULL; | |
199 | } | |
4e65331c TL |
200 | #endif |
201 | ||
4e65331c TL |
202 | extern void __init gic_init_irq(void); |
203 | extern void omap_smc1(u32 fn, u32 arg); | |
501f0c75 | 204 | extern void __iomem *omap4_get_sar_ram_base(void); |
b2b9762f | 205 | extern void omap_do_wfi(void); |
4e65331c TL |
206 | |
207 | #ifdef CONFIG_SMP | |
208 | /* Needed for secondary core boot */ | |
209 | extern void omap_secondary_startup(void); | |
210 | extern u32 omap_modify_auxcoreboot0(u32 set_mask, u32 clear_mask); | |
211 | extern void omap_auxcoreboot_addr(u32 cpu_addr); | |
212 | extern u32 omap_read_auxcoreboot0(void); | |
213 | #endif | |
214 | ||
b2b9762f SS |
215 | #if defined(CONFIG_SMP) && defined(CONFIG_PM) |
216 | extern int omap4_mpuss_init(void); | |
217 | extern int omap4_enter_lowpower(unsigned int cpu, unsigned int power_state); | |
218 | extern int omap4_finish_suspend(unsigned long cpu_state); | |
219 | extern void omap4_cpu_resume(void); | |
b5b4f288 | 220 | extern int omap4_hotplug_cpu(unsigned int cpu, unsigned int power_state); |
3ba2a739 | 221 | extern u32 omap4_mpuss_read_prev_context_state(void); |
b2b9762f SS |
222 | #else |
223 | static inline int omap4_enter_lowpower(unsigned int cpu, | |
224 | unsigned int power_state) | |
225 | { | |
226 | cpu_do_idle(); | |
227 | return 0; | |
228 | } | |
229 | ||
b5b4f288 SS |
230 | static inline int omap4_hotplug_cpu(unsigned int cpu, unsigned int power_state) |
231 | { | |
232 | cpu_do_idle(); | |
233 | return 0; | |
234 | } | |
235 | ||
b2b9762f SS |
236 | static inline int omap4_mpuss_init(void) |
237 | { | |
238 | return 0; | |
239 | } | |
240 | ||
241 | static inline int omap4_finish_suspend(unsigned long cpu_state) | |
242 | { | |
243 | return 0; | |
244 | } | |
245 | ||
246 | static inline void omap4_cpu_resume(void) | |
247 | {} | |
3ba2a739 SS |
248 | |
249 | static inline u32 omap4_mpuss_read_prev_context_state(void) | |
250 | { | |
251 | return 0; | |
252 | } | |
b2b9762f | 253 | #endif |
258ee922 TL |
254 | |
255 | struct omap_sdrc_params; | |
256 | extern void omap_sdrc_init(struct omap_sdrc_params *sdrc_cs0, | |
257 | struct omap_sdrc_params *sdrc_cs1); | |
258 | ||
b2b9762f | 259 | #endif /* __ASSEMBLER__ */ |
4e65331c | 260 | #endif /* __ARCH_ARM_MACH_OMAP2PLUS_COMMON_H */ |