ARM: OMAP2+: PRCM: remove omap_prcm_get_reset_sources()
[deliverable/linux.git] / arch / arm / mach-omap2 / common.h
CommitLineData
4e65331c
TL
1/*
2 * Header for code common to all OMAP2+ machines.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the
6 * Free Software Foundation; either version 2 of the License, or (at your
7 * option) any later version.
8 *
9 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
10 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
12 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
13 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
14 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
15 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
16 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
17 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
18 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
19 *
20 * You should have received a copy of the GNU General Public License along
21 * with this program; if not, write to the Free Software Foundation, Inc.,
22 * 675 Mass Ave, Cambridge, MA 02139, USA.
23 */
24
25#ifndef __ARCH_ARM_MACH_OMAP2PLUS_COMMON_H
26#define __ARCH_ARM_MACH_OMAP2PLUS_COMMON_H
b2b9762f 27#ifndef __ASSEMBLER__
4e65331c 28
ec2c0825 29#include <linux/irq.h>
4e65331c 30#include <linux/delay.h>
3a8761c0 31#include <linux/i2c.h>
1ee47b0a 32#include <linux/i2c/twl.h>
3a8761c0 33#include <linux/i2c-omap.h>
dbc04161 34
b2b9762f 35#include <asm/proc-fns.h>
4e65331c 36
e6a6e5ad 37#include "../plat-omap/common.h"
dbc04161 38
3a8761c0 39#include "i2c.h"
3d82cbbb 40#include "serial.h"
3a8761c0 41
54db6eee
TL
42#include "usb.h"
43
ec2c0825 44#define OMAP_INTC_START NR_IRQS
7d7e1eba 45
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46#ifdef CONFIG_SOC_OMAP2420
47extern void omap242x_map_common_io(void);
48#else
49static inline void omap242x_map_common_io(void)
50{
51}
52#endif
53
54#ifdef CONFIG_SOC_OMAP2430
55extern void omap243x_map_common_io(void);
56#else
57static inline void omap243x_map_common_io(void)
58{
59}
60#endif
61
62#ifdef CONFIG_ARCH_OMAP3
63extern void omap34xx_map_common_io(void);
64#else
65static inline void omap34xx_map_common_io(void)
66{
67}
68#endif
69
33959553 70#ifdef CONFIG_SOC_TI81XX
a920360f 71extern void omapti81xx_map_common_io(void);
4e65331c 72#else
a920360f 73static inline void omapti81xx_map_common_io(void)
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74{
75}
76#endif
77
bb6abcf4 78#ifdef CONFIG_SOC_AM33XX
1e6cb146
AM
79extern void omapam33xx_map_common_io(void);
80#else
81static inline void omapam33xx_map_common_io(void)
82{
83}
84#endif
85
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86#ifdef CONFIG_ARCH_OMAP4
87extern void omap44xx_map_common_io(void);
88#else
89static inline void omap44xx_map_common_io(void)
90{
91}
92#endif
93
bbd707ac
SG
94#if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP2)
95int omap2_pm_init(void);
96#else
97static inline int omap2_pm_init(void)
98{
99 return 0;
100}
101#endif
102
103#if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3)
104int omap3_pm_init(void);
105#else
106static inline int omap3_pm_init(void)
107{
108 return 0;
109}
110#endif
111
112#if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP4)
113int omap4_pm_init(void);
114#else
115static inline int omap4_pm_init(void)
116{
117 return 0;
118}
119#endif
120
121#ifdef CONFIG_OMAP_MUX
122int omap_mux_late_init(void);
123#else
124static inline int omap_mux_late_init(void)
125{
126 return 0;
127}
128#endif
129
05e152c7
S
130#ifdef CONFIG_SOC_OMAP5
131extern void omap5_map_common_io(void);
132#else
133static inline void omap5_map_common_io(void)
134{
135}
136#endif
137
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138extern void omap2_init_common_infrastructure(void);
139
140extern struct sys_timer omap2_timer;
141extern struct sys_timer omap3_timer;
142extern struct sys_timer omap3_secure_timer;
08f30989 143extern struct sys_timer omap3_am33xx_timer;
4e65331c 144extern struct sys_timer omap4_timer;
37b3280d 145extern struct sys_timer omap5_timer;
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146
147void omap2420_init_early(void);
148void omap2430_init_early(void);
149void omap3430_init_early(void);
150void omap35xx_init_early(void);
151void omap3630_init_early(void);
152void omap3_init_early(void); /* Do not use this one */
ce3fc89a 153void am33xx_init_early(void);
4e65331c 154void am35xx_init_early(void);
a920360f 155void ti81xx_init_early(void);
08f30989 156void am33xx_init_early(void);
4e65331c 157void omap4430_init_early(void);
05e152c7 158void omap5_init_early(void);
bbd707ac
SG
159void omap3_init_late(void); /* Do not use this one */
160void omap4430_init_late(void);
161void omap2420_init_late(void);
162void omap2430_init_late(void);
163void omap3430_init_late(void);
164void omap35xx_init_late(void);
165void omap3630_init_late(void);
166void am35xx_init_late(void);
167void ti81xx_init_late(void);
168void omap4430_init_late(void);
169int omap2_common_pm_late_init(void);
baa95883 170void omap_prcm_restart(char, const char *);
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171
172/*
173 * IO bases for various OMAP processors
174 * Except the tap base, rest all the io bases
175 * listed are physical addresses.
176 */
177struct omap_globals {
178 u32 class; /* OMAP class to detect */
179 void __iomem *tap; /* Control module ID code */
180 void __iomem *sdrc; /* SDRAM Controller */
181 void __iomem *sms; /* SDRAM Memory Scheduler */
182 void __iomem *ctrl; /* System Control Module */
183 void __iomem *ctrl_pad; /* PAD Control Module */
184 void __iomem *prm; /* Power and Reset Management */
185 void __iomem *cm; /* Clock Management */
186 void __iomem *cm2;
610eb8c2 187 void __iomem *prcm_mpu;
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188};
189
190void omap2_set_globals_242x(void);
191void omap2_set_globals_243x(void);
192void omap2_set_globals_3xxx(void);
193void omap2_set_globals_443x(void);
05e152c7 194void omap2_set_globals_5xxx(void);
a920360f 195void omap2_set_globals_ti81xx(void);
1e6cb146 196void omap2_set_globals_am33xx(void);
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197
198/* These get called from omap2_set_globals_xxxx(), do not call these */
199void omap2_set_globals_tap(struct omap_globals *);
ecc46cfd 200#if defined(CONFIG_SOC_HAS_OMAP2_SDRC)
4e65331c 201void omap2_set_globals_sdrc(struct omap_globals *);
ecc46cfd
VH
202#else
203static inline void omap2_set_globals_sdrc(struct omap_globals *omap2_globals)
204{ }
205#endif
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206void omap2_set_globals_control(struct omap_globals *);
207void omap2_set_globals_prcm(struct omap_globals *);
208
209void omap242x_map_io(void);
210void omap243x_map_io(void);
211void omap3_map_io(void);
1e6cb146 212void am33xx_map_io(void);
4e65331c 213void omap4_map_io(void);
05e152c7 214void omap5_map_io(void);
a920360f 215void ti81xx_map_io(void);
2ec1fc4e 216void omap_barriers_init(void);
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217
218/**
219 * omap_test_timeout - busy-loop, testing a condition
220 * @cond: condition to test until it evaluates to true
221 * @timeout: maximum number of microseconds in the timeout
222 * @index: loop index (integer)
223 *
224 * Loop waiting for @cond to become true or until at least @timeout
225 * microseconds have passed. To use, define some integer @index in the
226 * calling code. After running, if @index == @timeout, then the loop has
227 * timed out.
228 */
229#define omap_test_timeout(cond, timeout, index) \
230({ \
231 for (index = 0; index < timeout; index++) { \
232 if (cond) \
233 break; \
234 udelay(1); \
235 } \
236})
237
238extern struct device *omap2_get_mpuss_device(void);
239extern struct device *omap2_get_iva_device(void);
240extern struct device *omap2_get_l3_device(void);
241extern struct device *omap4_get_dsp_device(void);
242
243void omap2_init_irq(void);
244void omap3_init_irq(void);
a920360f 245void ti81xx_init_irq(void);
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246extern int omap_irq_pending(void);
247void omap_intc_save_context(void);
248void omap_intc_restore_context(void);
249void omap3_intc_suspend(void);
250void omap3_intc_prepare_idle(void);
251void omap3_intc_resume_idle(void);
f88f4dd8
SS
252void omap2_intc_handle_irq(struct pt_regs *regs);
253void omap3_intc_handle_irq(struct pt_regs *regs);
c4082d49
S
254void omap_intc_of_init(void);
255void omap_gic_of_init(void);
4e65331c 256
4e65331c 257#ifdef CONFIG_CACHE_L2X0
02afe8a7 258extern void __iomem *omap4_get_l2cache_base(void);
4e65331c
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259#endif
260
52fa2120
BC
261struct device_node;
262#ifdef CONFIG_OF
c4082d49 263int __init intc_of_init(struct device_node *node,
52fa2120
BC
264 struct device_node *parent);
265#else
c4082d49 266int __init intc_of_init(struct device_node *node,
52fa2120
BC
267 struct device_node *parent)
268{
269 return 0;
270}
271#endif
272
02afe8a7
SS
273#ifdef CONFIG_SMP
274extern void __iomem *omap4_get_scu_base(void);
275#else
276static inline void __iomem *omap4_get_scu_base(void)
277{
278 return NULL;
279}
4e65331c
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280#endif
281
4e65331c
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282extern void __init gic_init_irq(void);
283extern void omap_smc1(u32 fn, u32 arg);
501f0c75 284extern void __iomem *omap4_get_sar_ram_base(void);
b2b9762f 285extern void omap_do_wfi(void);
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286
287#ifdef CONFIG_SMP
288/* Needed for secondary core boot */
289extern void omap_secondary_startup(void);
290extern u32 omap_modify_auxcoreboot0(u32 set_mask, u32 clear_mask);
291extern void omap_auxcoreboot_addr(u32 cpu_addr);
292extern u32 omap_read_auxcoreboot0(void);
06915321
MZ
293
294extern void omap4_cpu_die(unsigned int cpu);
295
296extern struct smp_operations omap4_smp_ops;
297
283f708c 298extern void omap5_secondary_startup(void);
4e65331c
TL
299#endif
300
b2b9762f
SS
301#if defined(CONFIG_SMP) && defined(CONFIG_PM)
302extern int omap4_mpuss_init(void);
303extern int omap4_enter_lowpower(unsigned int cpu, unsigned int power_state);
304extern int omap4_finish_suspend(unsigned long cpu_state);
305extern void omap4_cpu_resume(void);
b5b4f288 306extern int omap4_hotplug_cpu(unsigned int cpu, unsigned int power_state);
3ba2a739 307extern u32 omap4_mpuss_read_prev_context_state(void);
b2b9762f
SS
308#else
309static inline int omap4_enter_lowpower(unsigned int cpu,
310 unsigned int power_state)
311{
312 cpu_do_idle();
313 return 0;
314}
315
b5b4f288
SS
316static inline int omap4_hotplug_cpu(unsigned int cpu, unsigned int power_state)
317{
318 cpu_do_idle();
319 return 0;
320}
321
b2b9762f
SS
322static inline int omap4_mpuss_init(void)
323{
324 return 0;
325}
326
327static inline int omap4_finish_suspend(unsigned long cpu_state)
328{
329 return 0;
330}
331
332static inline void omap4_cpu_resume(void)
333{}
3ba2a739
SS
334
335static inline u32 omap4_mpuss_read_prev_context_state(void)
336{
337 return 0;
338}
b2b9762f 339#endif
258ee922
TL
340
341struct omap_sdrc_params;
342extern void omap_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
343 struct omap_sdrc_params *sdrc_cs1);
1ee47b0a
B
344struct omap2_hsmmc_info;
345extern int omap4_twl6030_hsmmc_init(struct omap2_hsmmc_info *controllers);
f583f0f2 346extern void omap_reserve(void);
258ee922 347
b2b9762f 348#endif /* __ASSEMBLER__ */
4e65331c 349#endif /* __ARCH_ARM_MACH_OMAP2PLUS_COMMON_H */
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