ARM: OMAP: Split plat/cpu.h into local soc.h for mach-omap1 and mach-omap2
[deliverable/linux.git] / arch / arm / mach-omap2 / common.h
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1/*
2 * Header for code common to all OMAP2+ machines.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the
6 * Free Software Foundation; either version 2 of the License, or (at your
7 * option) any later version.
8 *
9 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
10 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
12 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
13 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
14 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
15 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
16 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
17 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
18 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
19 *
20 * You should have received a copy of the GNU General Public License along
21 * with this program; if not, write to the Free Software Foundation, Inc.,
22 * 675 Mass Ave, Cambridge, MA 02139, USA.
23 */
24
25#ifndef __ARCH_ARM_MACH_OMAP2PLUS_COMMON_H
26#define __ARCH_ARM_MACH_OMAP2PLUS_COMMON_H
b2b9762f 27#ifndef __ASSEMBLER__
4e65331c 28
ec2c0825 29#include <linux/irq.h>
4e65331c 30#include <linux/delay.h>
3a8761c0 31#include <linux/i2c.h>
1ee47b0a 32#include <linux/i2c/twl.h>
3a8761c0 33#include <linux/i2c-omap.h>
dbc04161 34
b2b9762f 35#include <asm/proc-fns.h>
4e65331c 36
dbc04161 37#include <plat/serial.h>
e6a6e5ad
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38
39#include "../plat-omap/common.h"
dbc04161 40
3a8761c0
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41#include "i2c.h"
42
ec2c0825 43#define OMAP_INTC_START NR_IRQS
7d7e1eba 44
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45#ifdef CONFIG_SOC_OMAP2420
46extern void omap242x_map_common_io(void);
47#else
48static inline void omap242x_map_common_io(void)
49{
50}
51#endif
52
53#ifdef CONFIG_SOC_OMAP2430
54extern void omap243x_map_common_io(void);
55#else
56static inline void omap243x_map_common_io(void)
57{
58}
59#endif
60
61#ifdef CONFIG_ARCH_OMAP3
62extern void omap34xx_map_common_io(void);
63#else
64static inline void omap34xx_map_common_io(void)
65{
66}
67#endif
68
33959553 69#ifdef CONFIG_SOC_TI81XX
a920360f 70extern void omapti81xx_map_common_io(void);
4e65331c 71#else
a920360f 72static inline void omapti81xx_map_common_io(void)
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73{
74}
75#endif
76
bb6abcf4 77#ifdef CONFIG_SOC_AM33XX
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78extern void omapam33xx_map_common_io(void);
79#else
80static inline void omapam33xx_map_common_io(void)
81{
82}
83#endif
84
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85#ifdef CONFIG_ARCH_OMAP4
86extern void omap44xx_map_common_io(void);
87#else
88static inline void omap44xx_map_common_io(void)
89{
90}
91#endif
92
bbd707ac
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93#if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP2)
94int omap2_pm_init(void);
95#else
96static inline int omap2_pm_init(void)
97{
98 return 0;
99}
100#endif
101
102#if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3)
103int omap3_pm_init(void);
104#else
105static inline int omap3_pm_init(void)
106{
107 return 0;
108}
109#endif
110
111#if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP4)
112int omap4_pm_init(void);
113#else
114static inline int omap4_pm_init(void)
115{
116 return 0;
117}
118#endif
119
120#ifdef CONFIG_OMAP_MUX
121int omap_mux_late_init(void);
122#else
123static inline int omap_mux_late_init(void)
124{
125 return 0;
126}
127#endif
128
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129#ifdef CONFIG_SOC_OMAP5
130extern void omap5_map_common_io(void);
131#else
132static inline void omap5_map_common_io(void)
133{
134}
135#endif
136
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137extern void omap2_init_common_infrastructure(void);
138
139extern struct sys_timer omap2_timer;
140extern struct sys_timer omap3_timer;
141extern struct sys_timer omap3_secure_timer;
08f30989 142extern struct sys_timer omap3_am33xx_timer;
4e65331c 143extern struct sys_timer omap4_timer;
37b3280d 144extern struct sys_timer omap5_timer;
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145
146void omap2420_init_early(void);
147void omap2430_init_early(void);
148void omap3430_init_early(void);
149void omap35xx_init_early(void);
150void omap3630_init_early(void);
151void omap3_init_early(void); /* Do not use this one */
ce3fc89a 152void am33xx_init_early(void);
4e65331c 153void am35xx_init_early(void);
a920360f 154void ti81xx_init_early(void);
08f30989 155void am33xx_init_early(void);
4e65331c 156void omap4430_init_early(void);
05e152c7 157void omap5_init_early(void);
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SG
158void omap3_init_late(void); /* Do not use this one */
159void omap4430_init_late(void);
160void omap2420_init_late(void);
161void omap2430_init_late(void);
162void omap3430_init_late(void);
163void omap35xx_init_late(void);
164void omap3630_init_late(void);
165void am35xx_init_late(void);
166void ti81xx_init_late(void);
167void omap4430_init_late(void);
168int omap2_common_pm_late_init(void);
baa95883 169void omap_prcm_restart(char, const char *);
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170
171/*
172 * IO bases for various OMAP processors
173 * Except the tap base, rest all the io bases
174 * listed are physical addresses.
175 */
176struct omap_globals {
177 u32 class; /* OMAP class to detect */
178 void __iomem *tap; /* Control module ID code */
179 void __iomem *sdrc; /* SDRAM Controller */
180 void __iomem *sms; /* SDRAM Memory Scheduler */
181 void __iomem *ctrl; /* System Control Module */
182 void __iomem *ctrl_pad; /* PAD Control Module */
183 void __iomem *prm; /* Power and Reset Management */
184 void __iomem *cm; /* Clock Management */
185 void __iomem *cm2;
610eb8c2 186 void __iomem *prcm_mpu;
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187};
188
189void omap2_set_globals_242x(void);
190void omap2_set_globals_243x(void);
191void omap2_set_globals_3xxx(void);
192void omap2_set_globals_443x(void);
05e152c7 193void omap2_set_globals_5xxx(void);
a920360f 194void omap2_set_globals_ti81xx(void);
1e6cb146 195void omap2_set_globals_am33xx(void);
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196
197/* These get called from omap2_set_globals_xxxx(), do not call these */
198void omap2_set_globals_tap(struct omap_globals *);
ecc46cfd 199#if defined(CONFIG_SOC_HAS_OMAP2_SDRC)
4e65331c 200void omap2_set_globals_sdrc(struct omap_globals *);
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VH
201#else
202static inline void omap2_set_globals_sdrc(struct omap_globals *omap2_globals)
203{ }
204#endif
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205void omap2_set_globals_control(struct omap_globals *);
206void omap2_set_globals_prcm(struct omap_globals *);
207
208void omap242x_map_io(void);
209void omap243x_map_io(void);
210void omap3_map_io(void);
1e6cb146 211void am33xx_map_io(void);
4e65331c 212void omap4_map_io(void);
05e152c7 213void omap5_map_io(void);
a920360f 214void ti81xx_map_io(void);
2ec1fc4e 215void omap_barriers_init(void);
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216
217/**
218 * omap_test_timeout - busy-loop, testing a condition
219 * @cond: condition to test until it evaluates to true
220 * @timeout: maximum number of microseconds in the timeout
221 * @index: loop index (integer)
222 *
223 * Loop waiting for @cond to become true or until at least @timeout
224 * microseconds have passed. To use, define some integer @index in the
225 * calling code. After running, if @index == @timeout, then the loop has
226 * timed out.
227 */
228#define omap_test_timeout(cond, timeout, index) \
229({ \
230 for (index = 0; index < timeout; index++) { \
231 if (cond) \
232 break; \
233 udelay(1); \
234 } \
235})
236
237extern struct device *omap2_get_mpuss_device(void);
238extern struct device *omap2_get_iva_device(void);
239extern struct device *omap2_get_l3_device(void);
240extern struct device *omap4_get_dsp_device(void);
241
242void omap2_init_irq(void);
243void omap3_init_irq(void);
a920360f 244void ti81xx_init_irq(void);
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245extern int omap_irq_pending(void);
246void omap_intc_save_context(void);
247void omap_intc_restore_context(void);
248void omap3_intc_suspend(void);
249void omap3_intc_prepare_idle(void);
250void omap3_intc_resume_idle(void);
f88f4dd8
SS
251void omap2_intc_handle_irq(struct pt_regs *regs);
252void omap3_intc_handle_irq(struct pt_regs *regs);
c4082d49
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253void omap_intc_of_init(void);
254void omap_gic_of_init(void);
4e65331c 255
4e65331c 256#ifdef CONFIG_CACHE_L2X0
02afe8a7 257extern void __iomem *omap4_get_l2cache_base(void);
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258#endif
259
52fa2120
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260struct device_node;
261#ifdef CONFIG_OF
c4082d49 262int __init intc_of_init(struct device_node *node,
52fa2120
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263 struct device_node *parent);
264#else
c4082d49 265int __init intc_of_init(struct device_node *node,
52fa2120
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266 struct device_node *parent)
267{
268 return 0;
269}
270#endif
271
02afe8a7
SS
272#ifdef CONFIG_SMP
273extern void __iomem *omap4_get_scu_base(void);
274#else
275static inline void __iomem *omap4_get_scu_base(void)
276{
277 return NULL;
278}
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279#endif
280
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281extern void __init gic_init_irq(void);
282extern void omap_smc1(u32 fn, u32 arg);
501f0c75 283extern void __iomem *omap4_get_sar_ram_base(void);
b2b9762f 284extern void omap_do_wfi(void);
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285
286#ifdef CONFIG_SMP
287/* Needed for secondary core boot */
288extern void omap_secondary_startup(void);
289extern u32 omap_modify_auxcoreboot0(u32 set_mask, u32 clear_mask);
290extern void omap_auxcoreboot_addr(u32 cpu_addr);
291extern u32 omap_read_auxcoreboot0(void);
06915321
MZ
292
293extern void omap4_cpu_die(unsigned int cpu);
294
295extern struct smp_operations omap4_smp_ops;
296
283f708c 297extern void omap5_secondary_startup(void);
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298#endif
299
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SS
300#if defined(CONFIG_SMP) && defined(CONFIG_PM)
301extern int omap4_mpuss_init(void);
302extern int omap4_enter_lowpower(unsigned int cpu, unsigned int power_state);
303extern int omap4_finish_suspend(unsigned long cpu_state);
304extern void omap4_cpu_resume(void);
b5b4f288 305extern int omap4_hotplug_cpu(unsigned int cpu, unsigned int power_state);
3ba2a739 306extern u32 omap4_mpuss_read_prev_context_state(void);
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SS
307#else
308static inline int omap4_enter_lowpower(unsigned int cpu,
309 unsigned int power_state)
310{
311 cpu_do_idle();
312 return 0;
313}
314
b5b4f288
SS
315static inline int omap4_hotplug_cpu(unsigned int cpu, unsigned int power_state)
316{
317 cpu_do_idle();
318 return 0;
319}
320
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321static inline int omap4_mpuss_init(void)
322{
323 return 0;
324}
325
326static inline int omap4_finish_suspend(unsigned long cpu_state)
327{
328 return 0;
329}
330
331static inline void omap4_cpu_resume(void)
332{}
3ba2a739
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333
334static inline u32 omap4_mpuss_read_prev_context_state(void)
335{
336 return 0;
337}
b2b9762f 338#endif
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339
340struct omap_sdrc_params;
341extern void omap_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
342 struct omap_sdrc_params *sdrc_cs1);
1ee47b0a
B
343struct omap2_hsmmc_info;
344extern int omap4_twl6030_hsmmc_init(struct omap2_hsmmc_info *controllers);
f583f0f2 345extern void omap_reserve(void);
258ee922 346
b2b9762f 347#endif /* __ASSEMBLER__ */
4e65331c 348#endif /* __ARCH_ARM_MACH_OMAP2PLUS_COMMON_H */
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