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Merge tag 'dt-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
[deliverable/linux.git] / arch / arm / mach-omap2 / control.c
CommitLineData
69d88a00
PW		 1/*
2 * OMAP2/3 System Control Module register access
3 *
3e6ece13 4 * Copyright (C) 2007, 2012 Texas Instruments, Inc.
69d88a00
PW		 5 * Copyright (C) 2007 Nokia Corporation
6 *
7 * Written by Paul Walmsley
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13#undef DEBUG
14
15#include <linux/kernel.h>
a58caad1 16#include <linux/io.h>
69d88a00 17
dbc04161 18#include "soc.h"
ee0839c2
TL		 19#include "iomap.h"
20#include "common.h"
80140786
RN		 21#include "cm-regbits-34xx.h"
22#include "prm-regbits-34xx.h"
139563ad 23#include "prm3xxx.h"
ff4ae5d9 24#include "cm3xxx.h"
80140786 25#include "sdrc.h"
38815733 26#include "pm.h"
4814ced5 27#include "control.h"
69d88a00 28
596efe47
PW		 29/* Used by omap3_ctrl_save_padconf() */
30#define START_PADCONF_SAVE 0x2
31#define PADCONF_SAVE_DONE 0x1
32
a58caad1 33static void __iomem *omap2_ctrl_base;
0c349246 34static void __iomem *omap4_ctrl_pad_base;
69d88a00 35
c96631e1 36#if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
80140786
RN		 37struct omap3_scratchpad {
38 u32 boot_config_ptr;
39 u32 public_restore_ptr;
40 u32 secure_ram_restore_ptr;
41 u32 sdrc_module_semaphore;
42 u32 prcm_block_offset;
43 u32 sdrc_block_offset;
44};
45
46struct omap3_scratchpad_prcm_block {
47 u32 prm_clksrc_ctrl;
48 u32 prm_clksel;
49 u32 cm_clksel_core;
50 u32 cm_clksel_wkup;
51 u32 cm_clken_pll;
52 u32 cm_autoidle_pll;
53 u32 cm_clksel1_pll;
54 u32 cm_clksel2_pll;
55 u32 cm_clksel3_pll;
56 u32 cm_clken_pll_mpu;
57 u32 cm_autoidle_pll_mpu;
58 u32 cm_clksel1_pll_mpu;
59 u32 cm_clksel2_pll_mpu;
60 u32 prcm_block_size;
61};
62
63struct omap3_scratchpad_sdrc_block {
64 u16 sysconfig;
65 u16 cs_cfg;
66 u16 sharing;
67 u16 err_type;
68 u32 dll_a_ctrl;
69 u32 dll_b_ctrl;
70 u32 power;
71 u32 cs_0;
72 u32 mcfg_0;
73 u16 mr_0;
74 u16 emr_1_0;
75 u16 emr_2_0;
76 u16 emr_3_0;
77 u32 actim_ctrla_0;
78 u32 actim_ctrlb_0;
79 u32 rfr_ctrl_0;
80 u32 cs_1;
81 u32 mcfg_1;
82 u16 mr_1;
83 u16 emr_1_1;
84 u16 emr_2_1;
85 u16 emr_3_1;
86 u32 actim_ctrla_1;
87 u32 actim_ctrlb_1;
88 u32 rfr_ctrl_1;
89 u16 dcdl_1_ctrl;
90 u16 dcdl_2_ctrl;
91 u32 flags;
92 u32 block_size;
93};
94
27d59a4a
TK		 95void *omap3_secure_ram_storage;
96
80140786
RN		 97/*
98 * This is used to store ARM registers in SDRAM before attempting
99 * an MPU OFF. The save and restore happens from the SRAM sleep code.
100 * The address is stored in scratchpad, so that it can be used
101 * during the restore path.
102 */
103u32 omap3_arm_context[128];
104
c96631e1
RN		 105struct omap3_control_regs {
106 u32 sysconfig;
107 u32 devconf0;
108 u32 mem_dftrw0;
109 u32 mem_dftrw1;
110 u32 msuspendmux_0;
111 u32 msuspendmux_1;
112 u32 msuspendmux_2;
113 u32 msuspendmux_3;
114 u32 msuspendmux_4;
115 u32 msuspendmux_5;
116 u32 sec_ctrl;
117 u32 devconf1;
118 u32 csirxfe;
119 u32 iva2_bootaddr;
120 u32 iva2_bootmod;
121 u32 debobs_0;
122 u32 debobs_1;
123 u32 debobs_2;
124 u32 debobs_3;
125 u32 debobs_4;
126 u32 debobs_5;
127 u32 debobs_6;
128 u32 debobs_7;
129 u32 debobs_8;
130 u32 prog_io0;
131 u32 prog_io1;
132 u32 dss_dpll_spreading;
133 u32 core_dpll_spreading;
134 u32 per_dpll_spreading;
135 u32 usbhost_dpll_spreading;
136 u32 pbias_lite;
137 u32 temp_sensor;
138 u32 sramldo4;
139 u32 sramldo5;
140 u32 csi;
f5f9d132 141 u32 padconf_sys_nirq;
c96631e1
RN		 142};
143
144static struct omap3_control_regs control_context;
145#endif /* CONFIG_ARCH_OMAP3 && CONFIG_PM */
146
a58caad1 147#define OMAP_CTRL_REGADDR(reg) (omap2_ctrl_base + (reg))
70ba71a2 148#define OMAP4_CTRL_PAD_REGADDR(reg) (omap4_ctrl_pad_base + (reg))
69d88a00 149
b6a4226c
PW		 150void __init omap2_set_globals_control(void __iomem *ctrl,
151 void __iomem *ctrl_pad)
69d88a00 152{
b6a4226c
PW		 153 omap2_ctrl_base = ctrl;
154 omap4_ctrl_pad_base = ctrl_pad;
69d88a00
PW		 155}
156
a58caad1 157void __iomem *omap_ctrl_base_get(void)
69d88a00
PW		 158{
159 return omap2_ctrl_base;
160}
161
162u8 omap_ctrl_readb(u16 offset)
163{
164 return __raw_readb(OMAP_CTRL_REGADDR(offset));
165}
166
167u16 omap_ctrl_readw(u16 offset)
168{
169 return __raw_readw(OMAP_CTRL_REGADDR(offset));
170}
171
172u32 omap_ctrl_readl(u16 offset)
173{
174 return __raw_readl(OMAP_CTRL_REGADDR(offset));
175}
176
177void omap_ctrl_writeb(u8 val, u16 offset)
178{
69d88a00
PW		 179 __raw_writeb(val, OMAP_CTRL_REGADDR(offset));
180}
181
182void omap_ctrl_writew(u16 val, u16 offset)
183{
69d88a00
PW		 184 __raw_writew(val, OMAP_CTRL_REGADDR(offset));
185}
186
187void omap_ctrl_writel(u32 val, u16 offset)
188{
69d88a00
PW		 189 __raw_writel(val, OMAP_CTRL_REGADDR(offset));
190}
191
70ba71a2
SS		 192/*
193 * On OMAP4 control pad are not addressable from control
194 * core base. So the common omap_ctrl_read/write APIs breaks
195 * Hence export separate APIs to manage the omap4 pad control
196 * registers. This APIs will work only for OMAP4
197 */
198
199u32 omap4_ctrl_pad_readl(u16 offset)
200{
201 return __raw_readl(OMAP4_CTRL_PAD_REGADDR(offset));
202}
203
204void omap4_ctrl_pad_writel(u32 val, u16 offset)
205{
206 __raw_writel(val, OMAP4_CTRL_PAD_REGADDR(offset));
207}
208
166353bd
PW		 209#ifdef CONFIG_ARCH_OMAP3
210
211/**
212 * omap3_ctrl_write_boot_mode - set scratchpad boot mode for the next boot
213 * @bootmode: 8-bit value to pass to some boot code
214 *
215 * Set the bootmode in the scratchpad RAM. This is used after the
216 * system restarts. Not sure what actually uses this - it may be the
217 * bootloader, rather than the boot ROM - contrary to the preserved
218 * comment below. No return value.
219 */
220void omap3_ctrl_write_boot_mode(u8 bootmode)
221{
222 u32 l;
223
224 l = ('B' << 24) | ('M' << 16) | bootmode;
225
226 /*
227 * Reserve the first word in scratchpad for communicating
228 * with the boot ROM. A pointer to a data structure
229 * describing the boot process can be stored there,
230 * cf. OMAP34xx TRM, Initialization / Software Booting
231 * Configuration.
232 *
233 * XXX This should use some omap_ctrl_writel()-type function
234 */
235 __raw_writel(l, OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD + 4));
236}
237
238#endif
239
90f1380e
ORL		 240/**
241 * omap_ctrl_write_dsp_boot_addr - set boot address for a remote processor
242 * @bootaddr: physical address of the boot loader
243 *
244 * Set boot address for the boot loader of a supported processor
245 * when a power ON sequence occurs.
246 */
247void omap_ctrl_write_dsp_boot_addr(u32 bootaddr)
248{
249 u32 offset = cpu_is_omap243x() ? OMAP243X_CONTROL_IVA2_BOOTADDR :
250 cpu_is_omap34xx() ? OMAP343X_CONTROL_IVA2_BOOTADDR :
251 cpu_is_omap44xx() ? OMAP4_CTRL_MODULE_CORE_DSP_BOOTADDR :
252 0;
253
254 if (!offset) {
255 pr_err("%s: unsupported omap type\n", __func__);
256 return;
257 }
258
259 omap_ctrl_writel(bootaddr, offset);
260}
261
262/**
263 * omap_ctrl_write_dsp_boot_mode - set boot mode for a remote processor
264 * @bootmode: 8-bit value to pass to some boot code
265 *
266 * Sets boot mode for the boot loader of a supported processor
267 * when a power ON sequence occurs.
268 */
269void omap_ctrl_write_dsp_boot_mode(u8 bootmode)
270{
271 u32 offset = cpu_is_omap243x() ? OMAP243X_CONTROL_IVA2_BOOTMOD :
272 cpu_is_omap34xx() ? OMAP343X_CONTROL_IVA2_BOOTMOD :
273 0;
274
275 if (!offset) {
276 pr_err("%s: unsupported omap type\n", __func__);
277 return;
278 }
279
280 omap_ctrl_writel(bootmode, offset);
281}
282
c96631e1 283#if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
80140786
RN		 284/*
285 * Clears the scratchpad contents in case of cold boot-
286 * called during bootup
287 */
288void omap3_clear_scratchpad_contents(void)
289{
290 u32 max_offset = OMAP343X_SCRATCHPAD_ROM_OFFSET;
4d63bc1d 291 void __iomem *v_addr;
80140786
RN		 292 u32 offset = 0;
293 v_addr = OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD_ROM);
c4d7e58f 294 if (omap2_prm_read_mod_reg(OMAP3430_GR_MOD, OMAP3_PRM_RSTST_OFFSET) &
2bc4ef71 295 OMAP3430_GLOBAL_COLD_RST_MASK) {
80140786
RN		 296 for ( ; offset <= max_offset; offset += 0x4)
297 __raw_writel(0x0, (v_addr + offset));
c4d7e58f
PW		 298 omap2_prm_set_mod_reg_bits(OMAP3430_GLOBAL_COLD_RST_MASK,
299 OMAP3430_GR_MOD,
300 OMAP3_PRM_RSTST_OFFSET);
80140786
RN		 301 }
302}
303
304/* Populate the scratchpad structure with restore structure */
305void omap3_save_scratchpad_contents(void)
306{
4d63bc1d 307 void __iomem *scratchpad_address;
80140786
RN		 308 u32 arm_context_addr;
309 struct omap3_scratchpad scratchpad_contents;
310 struct omap3_scratchpad_prcm_block prcm_block_contents;
311 struct omap3_scratchpad_sdrc_block sdrc_block_contents;
312
f7dfe3d8
JP		 313 /*
314 * Populate the Scratchpad contents
315 *
316 * The "get_*restore_pointer" functions are used to provide a
317 * physical restore address where the ROM code jumps while waking
318 * up from MPU OFF/OSWR state.
319 * The restore pointer is stored into the scratchpad.
320 */
80140786 321 scratchpad_contents.boot_config_ptr = 0x0;
458e999e
NM		 322 if (cpu_is_omap3630())
323 scratchpad_contents.public_restore_ptr =
14c79bbe 324 virt_to_phys(omap3_restore_3630);
458e999e 325 else if (omap_rev() != OMAP3430_REV_ES3_0 &&
0795a75a
TK		 326 omap_rev() != OMAP3430_REV_ES3_1)
327 scratchpad_contents.public_restore_ptr =
14c79bbe 328 virt_to_phys(omap3_restore);
0795a75a
TK		 329 else
330 scratchpad_contents.public_restore_ptr =
14c79bbe
KH		 331 virt_to_phys(omap3_restore_es3);
332
27d59a4a
TK		 333 if (omap_type() == OMAP2_DEVICE_TYPE_GP)
334 scratchpad_contents.secure_ram_restore_ptr = 0x0;
335 else
336 scratchpad_contents.secure_ram_restore_ptr =
337 (u32) __pa(omap3_secure_ram_storage);
80140786
RN		 338 scratchpad_contents.sdrc_module_semaphore = 0x0;
339 scratchpad_contents.prcm_block_offset = 0x2C;
340 scratchpad_contents.sdrc_block_offset = 0x64;
341
342 /* Populate the PRCM block contents */
c4d7e58f
PW		 343 prcm_block_contents.prm_clksrc_ctrl =
344 omap2_prm_read_mod_reg(OMAP3430_GR_MOD,
345 OMAP3_PRM_CLKSRC_CTRL_OFFSET);
346 prcm_block_contents.prm_clksel =
347 omap2_prm_read_mod_reg(OMAP3430_CCR_MOD,
348 OMAP3_PRM_CLKSEL_OFFSET);
80140786 349 prcm_block_contents.cm_clksel_core =
c4d7e58f 350 omap2_cm_read_mod_reg(CORE_MOD, CM_CLKSEL);
80140786 351 prcm_block_contents.cm_clksel_wkup =
c4d7e58f 352 omap2_cm_read_mod_reg(WKUP_MOD, CM_CLKSEL);
80140786 353 prcm_block_contents.cm_clken_pll =
c4d7e58f 354 omap2_cm_read_mod_reg(PLL_MOD, CM_CLKEN);
a8ae645c
EV		 355 /*
356 * As per erratum i671, ROM code does not respect the PER DPLL
357 * programming scheme if CM_AUTOIDLE_PLL..AUTO_PERIPH_DPLL == 1.
358 * Then, in anycase, clear these bits to avoid extra latencies.
359 */
80140786 360 prcm_block_contents.cm_autoidle_pll =
a8ae645c
EV		 361 omap2_cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE) &
362 ~OMAP3430_AUTO_PERIPH_DPLL_MASK;
80140786 363 prcm_block_contents.cm_clksel1_pll =
c4d7e58f 364 omap2_cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL1_PLL);
80140786 365 prcm_block_contents.cm_clksel2_pll =
c4d7e58f 366 omap2_cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL2_PLL);
80140786 367 prcm_block_contents.cm_clksel3_pll =
c4d7e58f 368 omap2_cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL3);
80140786 369 prcm_block_contents.cm_clken_pll_mpu =
c4d7e58f 370 omap2_cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKEN_PLL);
80140786 371 prcm_block_contents.cm_autoidle_pll_mpu =
c4d7e58f 372 omap2_cm_read_mod_reg(MPU_MOD, OMAP3430_CM_AUTOIDLE_PLL);
80140786 373 prcm_block_contents.cm_clksel1_pll_mpu =
c4d7e58f 374 omap2_cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL);
80140786 375 prcm_block_contents.cm_clksel2_pll_mpu =
c4d7e58f 376 omap2_cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL);
80140786
RN		 377 prcm_block_contents.prcm_block_size = 0x0;
378
379 /* Populate the SDRC block contents */
380 sdrc_block_contents.sysconfig =
381 (sdrc_read_reg(SDRC_SYSCONFIG) & 0xFFFF);
382 sdrc_block_contents.cs_cfg =
383 (sdrc_read_reg(SDRC_CS_CFG) & 0xFFFF);
384 sdrc_block_contents.sharing =
385 (sdrc_read_reg(SDRC_SHARING) & 0xFFFF);
386 sdrc_block_contents.err_type =
387 (sdrc_read_reg(SDRC_ERR_TYPE) & 0xFFFF);
388 sdrc_block_contents.dll_a_ctrl = sdrc_read_reg(SDRC_DLLA_CTRL);
389 sdrc_block_contents.dll_b_ctrl = 0x0;
f265dc4c
RN		 390 /*
391 * Due to a OMAP3 errata (1.142), on EMU/HS devices SRDC should
392 * be programed to issue automatic self refresh on timeout
393 * of AUTO_CNT = 1 prior to any transition to OFF mode.
394 */
395 if ((omap_type() != OMAP2_DEVICE_TYPE_GP)
396 && (omap_rev() >= OMAP3430_REV_ES3_0))
397 sdrc_block_contents.power = (sdrc_read_reg(SDRC_POWER) &
398 ~(SDRC_POWER_AUTOCOUNT_MASK|
399 SDRC_POWER_CLKCTRL_MASK)) |
400 (1 << SDRC_POWER_AUTOCOUNT_SHIFT) |
401 SDRC_SELF_REFRESH_ON_AUTOCOUNT;
402 else
403 sdrc_block_contents.power = sdrc_read_reg(SDRC_POWER);
404
80140786
RN		 405 sdrc_block_contents.cs_0 = 0x0;
406 sdrc_block_contents.mcfg_0 = sdrc_read_reg(SDRC_MCFG_0);
407 sdrc_block_contents.mr_0 = (sdrc_read_reg(SDRC_MR_0) & 0xFFFF);
408 sdrc_block_contents.emr_1_0 = 0x0;
409 sdrc_block_contents.emr_2_0 = 0x0;
410 sdrc_block_contents.emr_3_0 = 0x0;
411 sdrc_block_contents.actim_ctrla_0 =
412 sdrc_read_reg(SDRC_ACTIM_CTRL_A_0);
413 sdrc_block_contents.actim_ctrlb_0 =
414 sdrc_read_reg(SDRC_ACTIM_CTRL_B_0);
415 sdrc_block_contents.rfr_ctrl_0 =
416 sdrc_read_reg(SDRC_RFR_CTRL_0);
417 sdrc_block_contents.cs_1 = 0x0;
418 sdrc_block_contents.mcfg_1 = sdrc_read_reg(SDRC_MCFG_1);
419 sdrc_block_contents.mr_1 = sdrc_read_reg(SDRC_MR_1) & 0xFFFF;
420 sdrc_block_contents.emr_1_1 = 0x0;
421 sdrc_block_contents.emr_2_1 = 0x0;
422 sdrc_block_contents.emr_3_1 = 0x0;
423 sdrc_block_contents.actim_ctrla_1 =
424 sdrc_read_reg(SDRC_ACTIM_CTRL_A_1);
425 sdrc_block_contents.actim_ctrlb_1 =
426 sdrc_read_reg(SDRC_ACTIM_CTRL_B_1);
427 sdrc_block_contents.rfr_ctrl_1 =
428 sdrc_read_reg(SDRC_RFR_CTRL_1);
429 sdrc_block_contents.dcdl_1_ctrl = 0x0;
430 sdrc_block_contents.dcdl_2_ctrl = 0x0;
431 sdrc_block_contents.flags = 0x0;
432 sdrc_block_contents.block_size = 0x0;
433
434 arm_context_addr = virt_to_phys(omap3_arm_context);
435
436 /* Copy all the contents to the scratchpad location */
437 scratchpad_address = OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD);
438 memcpy_toio(scratchpad_address, &scratchpad_contents,
439 sizeof(scratchpad_contents));
440 /* Scratchpad contents being 32 bits, a divide by 4 done here */
441 memcpy_toio(scratchpad_address +
442 scratchpad_contents.prcm_block_offset,
443 &prcm_block_contents, sizeof(prcm_block_contents));
444 memcpy_toio(scratchpad_address +
445 scratchpad_contents.sdrc_block_offset,
446 &sdrc_block_contents, sizeof(sdrc_block_contents));
447 /*
448 * Copies the address of the location in SDRAM where ARM
449 * registers get saved during a MPU OFF transition.
450 */
451 memcpy_toio(scratchpad_address +
452 scratchpad_contents.sdrc_block_offset +
453 sizeof(sdrc_block_contents), &arm_context_addr, 4);
454}
455
c96631e1
RN		 456void omap3_control_save_context(void)
457{
458 control_context.sysconfig = omap_ctrl_readl(OMAP2_CONTROL_SYSCONFIG);
459 control_context.devconf0 = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
460 control_context.mem_dftrw0 =
461 omap_ctrl_readl(OMAP343X_CONTROL_MEM_DFTRW0);
462 control_context.mem_dftrw1 =
463 omap_ctrl_readl(OMAP343X_CONTROL_MEM_DFTRW1);
464 control_context.msuspendmux_0 =
465 omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_0);
466 control_context.msuspendmux_1 =
467 omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_1);
468 control_context.msuspendmux_2 =
469 omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_2);
470 control_context.msuspendmux_3 =
471 omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_3);
472 control_context.msuspendmux_4 =
473 omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_4);
474 control_context.msuspendmux_5 =
475 omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_5);
476 control_context.sec_ctrl = omap_ctrl_readl(OMAP2_CONTROL_SEC_CTRL);
477 control_context.devconf1 = omap_ctrl_readl(OMAP343X_CONTROL_DEVCONF1);
478 control_context.csirxfe = omap_ctrl_readl(OMAP343X_CONTROL_CSIRXFE);
479 control_context.iva2_bootaddr =
480 omap_ctrl_readl(OMAP343X_CONTROL_IVA2_BOOTADDR);
481 control_context.iva2_bootmod =
482 omap_ctrl_readl(OMAP343X_CONTROL_IVA2_BOOTMOD);
483 control_context.debobs_0 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(0));
484 control_context.debobs_1 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(1));
485 control_context.debobs_2 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(2));
486 control_context.debobs_3 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(3));
487 control_context.debobs_4 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(4));
488 control_context.debobs_5 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(5));
489 control_context.debobs_6 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(6));
490 control_context.debobs_7 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(7));
491 control_context.debobs_8 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(8));
492 control_context.prog_io0 = omap_ctrl_readl(OMAP343X_CONTROL_PROG_IO0);
493 control_context.prog_io1 = omap_ctrl_readl(OMAP343X_CONTROL_PROG_IO1);
494 control_context.dss_dpll_spreading =
495 omap_ctrl_readl(OMAP343X_CONTROL_DSS_DPLL_SPREADING);
496 control_context.core_dpll_spreading =
497 omap_ctrl_readl(OMAP343X_CONTROL_CORE_DPLL_SPREADING);
498 control_context.per_dpll_spreading =
499 omap_ctrl_readl(OMAP343X_CONTROL_PER_DPLL_SPREADING);
500 control_context.usbhost_dpll_spreading =
501 omap_ctrl_readl(OMAP343X_CONTROL_USBHOST_DPLL_SPREADING);
502 control_context.pbias_lite =
503 omap_ctrl_readl(OMAP343X_CONTROL_PBIAS_LITE);
504 control_context.temp_sensor =
505 omap_ctrl_readl(OMAP343X_CONTROL_TEMP_SENSOR);
506 control_context.sramldo4 = omap_ctrl_readl(OMAP343X_CONTROL_SRAMLDO4);
507 control_context.sramldo5 = omap_ctrl_readl(OMAP343X_CONTROL_SRAMLDO5);
508 control_context.csi = omap_ctrl_readl(OMAP343X_CONTROL_CSI);
f5f9d132
PW		 509 control_context.padconf_sys_nirq =
510 omap_ctrl_readl(OMAP343X_CONTROL_PADCONF_SYSNIRQ);
c96631e1
RN		 511 return;
512}
513
514void omap3_control_restore_context(void)
515{
516 omap_ctrl_writel(control_context.sysconfig, OMAP2_CONTROL_SYSCONFIG);
517 omap_ctrl_writel(control_context.devconf0, OMAP2_CONTROL_DEVCONF0);
518 omap_ctrl_writel(control_context.mem_dftrw0,
519 OMAP343X_CONTROL_MEM_DFTRW0);
520 omap_ctrl_writel(control_context.mem_dftrw1,
521 OMAP343X_CONTROL_MEM_DFTRW1);
522 omap_ctrl_writel(control_context.msuspendmux_0,
523 OMAP2_CONTROL_MSUSPENDMUX_0);
524 omap_ctrl_writel(control_context.msuspendmux_1,
525 OMAP2_CONTROL_MSUSPENDMUX_1);
526 omap_ctrl_writel(control_context.msuspendmux_2,
527 OMAP2_CONTROL_MSUSPENDMUX_2);
528 omap_ctrl_writel(control_context.msuspendmux_3,
529 OMAP2_CONTROL_MSUSPENDMUX_3);
530 omap_ctrl_writel(control_context.msuspendmux_4,
531 OMAP2_CONTROL_MSUSPENDMUX_4);
532 omap_ctrl_writel(control_context.msuspendmux_5,
533 OMAP2_CONTROL_MSUSPENDMUX_5);
534 omap_ctrl_writel(control_context.sec_ctrl, OMAP2_CONTROL_SEC_CTRL);
535 omap_ctrl_writel(control_context.devconf1, OMAP343X_CONTROL_DEVCONF1);
536 omap_ctrl_writel(control_context.csirxfe, OMAP343X_CONTROL_CSIRXFE);
537 omap_ctrl_writel(control_context.iva2_bootaddr,
538 OMAP343X_CONTROL_IVA2_BOOTADDR);
539 omap_ctrl_writel(control_context.iva2_bootmod,
540 OMAP343X_CONTROL_IVA2_BOOTMOD);
541 omap_ctrl_writel(control_context.debobs_0, OMAP343X_CONTROL_DEBOBS(0));
542 omap_ctrl_writel(control_context.debobs_1, OMAP343X_CONTROL_DEBOBS(1));
543 omap_ctrl_writel(control_context.debobs_2, OMAP343X_CONTROL_DEBOBS(2));
544 omap_ctrl_writel(control_context.debobs_3, OMAP343X_CONTROL_DEBOBS(3));
545 omap_ctrl_writel(control_context.debobs_4, OMAP343X_CONTROL_DEBOBS(4));
546 omap_ctrl_writel(control_context.debobs_5, OMAP343X_CONTROL_DEBOBS(5));
547 omap_ctrl_writel(control_context.debobs_6, OMAP343X_CONTROL_DEBOBS(6));
548 omap_ctrl_writel(control_context.debobs_7, OMAP343X_CONTROL_DEBOBS(7));
549 omap_ctrl_writel(control_context.debobs_8, OMAP343X_CONTROL_DEBOBS(8));
550 omap_ctrl_writel(control_context.prog_io0, OMAP343X_CONTROL_PROG_IO0);
551 omap_ctrl_writel(control_context.prog_io1, OMAP343X_CONTROL_PROG_IO1);
552 omap_ctrl_writel(control_context.dss_dpll_spreading,
553 OMAP343X_CONTROL_DSS_DPLL_SPREADING);
554 omap_ctrl_writel(control_context.core_dpll_spreading,
555 OMAP343X_CONTROL_CORE_DPLL_SPREADING);
556 omap_ctrl_writel(control_context.per_dpll_spreading,
557 OMAP343X_CONTROL_PER_DPLL_SPREADING);
558 omap_ctrl_writel(control_context.usbhost_dpll_spreading,
559 OMAP343X_CONTROL_USBHOST_DPLL_SPREADING);
560 omap_ctrl_writel(control_context.pbias_lite,
561 OMAP343X_CONTROL_PBIAS_LITE);
562 omap_ctrl_writel(control_context.temp_sensor,
563 OMAP343X_CONTROL_TEMP_SENSOR);
564 omap_ctrl_writel(control_context.sramldo4, OMAP343X_CONTROL_SRAMLDO4);
565 omap_ctrl_writel(control_context.sramldo5, OMAP343X_CONTROL_SRAMLDO5);
566 omap_ctrl_writel(control_context.csi, OMAP343X_CONTROL_CSI);
f5f9d132
PW		 567 omap_ctrl_writel(control_context.padconf_sys_nirq,
568 OMAP343X_CONTROL_PADCONF_SYSNIRQ);
c96631e1
RN		 569 return;
570}
458e999e
NM		 571
572void omap3630_ctrl_disable_rta(void)
573{
574 if (!cpu_is_omap3630())
575 return;
576 omap_ctrl_writel(OMAP36XX_RTA_DISABLE, OMAP36XX_CONTROL_MEM_RTA_CTRL);
577}
578
596efe47
PW		 579/**
580 * omap3_ctrl_save_padconf - save padconf registers to scratchpad RAM
581 *
582 * Tell the SCM to start saving the padconf registers, then wait for
583 * the process to complete. Returns 0 unconditionally, although it
584 * should also eventually be able to return -ETIMEDOUT, if the save
585 * does not complete.
586 *
587 * XXX This function is missing a timeout. What should it be?
588 */
589int omap3_ctrl_save_padconf(void)
590{
591 u32 cpo;
592
593 /* Save the padconf registers */
594 cpo = omap_ctrl_readl(OMAP343X_CONTROL_PADCONF_OFF);
595 cpo |= START_PADCONF_SAVE;
596 omap_ctrl_writel(cpo, OMAP343X_CONTROL_PADCONF_OFF);
597
598 /* wait for the save to complete */
599 while (!(omap_ctrl_readl(OMAP343X_CONTROL_GENERAL_PURPOSE_STATUS)
600 & PADCONF_SAVE_DONE))
601 udelay(1);
602
603 return 0;
604}
605
c96631e1 606#endif /* CONFIG_ARCH_OMAP3 && CONFIG_PM */
Linux kernel - Deliverables
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