Commit | Line | Data |
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69d88a00 PW |
1 | /* |
2 | * OMAP2/3 System Control Module register access | |
3 | * | |
3e6ece13 | 4 | * Copyright (C) 2007, 2012 Texas Instruments, Inc. |
69d88a00 PW |
5 | * Copyright (C) 2007 Nokia Corporation |
6 | * | |
7 | * Written by Paul Walmsley | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as | |
11 | * published by the Free Software Foundation. | |
12 | */ | |
13 | #undef DEBUG | |
14 | ||
15 | #include <linux/kernel.h> | |
a58caad1 | 16 | #include <linux/io.h> |
69d88a00 | 17 | |
dbc04161 | 18 | #include "soc.h" |
ee0839c2 TL |
19 | #include "iomap.h" |
20 | #include "common.h" | |
80140786 RN |
21 | #include "cm-regbits-34xx.h" |
22 | #include "prm-regbits-34xx.h" | |
139563ad | 23 | #include "prm3xxx.h" |
ff4ae5d9 | 24 | #include "cm3xxx.h" |
80140786 | 25 | #include "sdrc.h" |
38815733 | 26 | #include "pm.h" |
4814ced5 | 27 | #include "control.h" |
69d88a00 | 28 | |
596efe47 PW |
29 | /* Used by omap3_ctrl_save_padconf() */ |
30 | #define START_PADCONF_SAVE 0x2 | |
31 | #define PADCONF_SAVE_DONE 0x1 | |
32 | ||
a58caad1 | 33 | static void __iomem *omap2_ctrl_base; |
0c349246 | 34 | static void __iomem *omap4_ctrl_pad_base; |
69d88a00 | 35 | |
c96631e1 | 36 | #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM) |
80140786 RN |
37 | struct omap3_scratchpad { |
38 | u32 boot_config_ptr; | |
39 | u32 public_restore_ptr; | |
40 | u32 secure_ram_restore_ptr; | |
41 | u32 sdrc_module_semaphore; | |
42 | u32 prcm_block_offset; | |
43 | u32 sdrc_block_offset; | |
44 | }; | |
45 | ||
46 | struct omap3_scratchpad_prcm_block { | |
47 | u32 prm_clksrc_ctrl; | |
48 | u32 prm_clksel; | |
c6a2d839 | 49 | u32 cm_contents[11]; |
80140786 RN |
50 | u32 prcm_block_size; |
51 | }; | |
52 | ||
53 | struct omap3_scratchpad_sdrc_block { | |
54 | u16 sysconfig; | |
55 | u16 cs_cfg; | |
56 | u16 sharing; | |
57 | u16 err_type; | |
58 | u32 dll_a_ctrl; | |
59 | u32 dll_b_ctrl; | |
60 | u32 power; | |
61 | u32 cs_0; | |
62 | u32 mcfg_0; | |
63 | u16 mr_0; | |
64 | u16 emr_1_0; | |
65 | u16 emr_2_0; | |
66 | u16 emr_3_0; | |
67 | u32 actim_ctrla_0; | |
68 | u32 actim_ctrlb_0; | |
69 | u32 rfr_ctrl_0; | |
70 | u32 cs_1; | |
71 | u32 mcfg_1; | |
72 | u16 mr_1; | |
73 | u16 emr_1_1; | |
74 | u16 emr_2_1; | |
75 | u16 emr_3_1; | |
76 | u32 actim_ctrla_1; | |
77 | u32 actim_ctrlb_1; | |
78 | u32 rfr_ctrl_1; | |
79 | u16 dcdl_1_ctrl; | |
80 | u16 dcdl_2_ctrl; | |
81 | u32 flags; | |
82 | u32 block_size; | |
83 | }; | |
84 | ||
27d59a4a TK |
85 | void *omap3_secure_ram_storage; |
86 | ||
80140786 RN |
87 | /* |
88 | * This is used to store ARM registers in SDRAM before attempting | |
89 | * an MPU OFF. The save and restore happens from the SRAM sleep code. | |
90 | * The address is stored in scratchpad, so that it can be used | |
91 | * during the restore path. | |
92 | */ | |
93 | u32 omap3_arm_context[128]; | |
94 | ||
c96631e1 RN |
95 | struct omap3_control_regs { |
96 | u32 sysconfig; | |
97 | u32 devconf0; | |
98 | u32 mem_dftrw0; | |
99 | u32 mem_dftrw1; | |
100 | u32 msuspendmux_0; | |
101 | u32 msuspendmux_1; | |
102 | u32 msuspendmux_2; | |
103 | u32 msuspendmux_3; | |
104 | u32 msuspendmux_4; | |
105 | u32 msuspendmux_5; | |
106 | u32 sec_ctrl; | |
107 | u32 devconf1; | |
108 | u32 csirxfe; | |
109 | u32 iva2_bootaddr; | |
110 | u32 iva2_bootmod; | |
111 | u32 debobs_0; | |
112 | u32 debobs_1; | |
113 | u32 debobs_2; | |
114 | u32 debobs_3; | |
115 | u32 debobs_4; | |
116 | u32 debobs_5; | |
117 | u32 debobs_6; | |
118 | u32 debobs_7; | |
119 | u32 debobs_8; | |
120 | u32 prog_io0; | |
121 | u32 prog_io1; | |
122 | u32 dss_dpll_spreading; | |
123 | u32 core_dpll_spreading; | |
124 | u32 per_dpll_spreading; | |
125 | u32 usbhost_dpll_spreading; | |
126 | u32 pbias_lite; | |
127 | u32 temp_sensor; | |
128 | u32 sramldo4; | |
129 | u32 sramldo5; | |
130 | u32 csi; | |
f5f9d132 | 131 | u32 padconf_sys_nirq; |
c96631e1 RN |
132 | }; |
133 | ||
134 | static struct omap3_control_regs control_context; | |
135 | #endif /* CONFIG_ARCH_OMAP3 && CONFIG_PM */ | |
136 | ||
a58caad1 | 137 | #define OMAP_CTRL_REGADDR(reg) (omap2_ctrl_base + (reg)) |
70ba71a2 | 138 | #define OMAP4_CTRL_PAD_REGADDR(reg) (omap4_ctrl_pad_base + (reg)) |
69d88a00 | 139 | |
b6a4226c PW |
140 | void __init omap2_set_globals_control(void __iomem *ctrl, |
141 | void __iomem *ctrl_pad) | |
69d88a00 | 142 | { |
b6a4226c PW |
143 | omap2_ctrl_base = ctrl; |
144 | omap4_ctrl_pad_base = ctrl_pad; | |
69d88a00 PW |
145 | } |
146 | ||
a58caad1 | 147 | void __iomem *omap_ctrl_base_get(void) |
69d88a00 PW |
148 | { |
149 | return omap2_ctrl_base; | |
150 | } | |
151 | ||
152 | u8 omap_ctrl_readb(u16 offset) | |
153 | { | |
edfaf05c | 154 | return readb_relaxed(OMAP_CTRL_REGADDR(offset)); |
69d88a00 PW |
155 | } |
156 | ||
157 | u16 omap_ctrl_readw(u16 offset) | |
158 | { | |
edfaf05c | 159 | return readw_relaxed(OMAP_CTRL_REGADDR(offset)); |
69d88a00 PW |
160 | } |
161 | ||
162 | u32 omap_ctrl_readl(u16 offset) | |
163 | { | |
edfaf05c | 164 | return readl_relaxed(OMAP_CTRL_REGADDR(offset)); |
69d88a00 PW |
165 | } |
166 | ||
167 | void omap_ctrl_writeb(u8 val, u16 offset) | |
168 | { | |
edfaf05c | 169 | writeb_relaxed(val, OMAP_CTRL_REGADDR(offset)); |
69d88a00 PW |
170 | } |
171 | ||
172 | void omap_ctrl_writew(u16 val, u16 offset) | |
173 | { | |
edfaf05c | 174 | writew_relaxed(val, OMAP_CTRL_REGADDR(offset)); |
69d88a00 PW |
175 | } |
176 | ||
177 | void omap_ctrl_writel(u32 val, u16 offset) | |
178 | { | |
edfaf05c | 179 | writel_relaxed(val, OMAP_CTRL_REGADDR(offset)); |
69d88a00 PW |
180 | } |
181 | ||
70ba71a2 SS |
182 | /* |
183 | * On OMAP4 control pad are not addressable from control | |
184 | * core base. So the common omap_ctrl_read/write APIs breaks | |
185 | * Hence export separate APIs to manage the omap4 pad control | |
186 | * registers. This APIs will work only for OMAP4 | |
187 | */ | |
188 | ||
189 | u32 omap4_ctrl_pad_readl(u16 offset) | |
190 | { | |
edfaf05c | 191 | return readl_relaxed(OMAP4_CTRL_PAD_REGADDR(offset)); |
70ba71a2 SS |
192 | } |
193 | ||
194 | void omap4_ctrl_pad_writel(u32 val, u16 offset) | |
195 | { | |
edfaf05c | 196 | writel_relaxed(val, OMAP4_CTRL_PAD_REGADDR(offset)); |
70ba71a2 SS |
197 | } |
198 | ||
166353bd PW |
199 | #ifdef CONFIG_ARCH_OMAP3 |
200 | ||
201 | /** | |
202 | * omap3_ctrl_write_boot_mode - set scratchpad boot mode for the next boot | |
203 | * @bootmode: 8-bit value to pass to some boot code | |
204 | * | |
205 | * Set the bootmode in the scratchpad RAM. This is used after the | |
206 | * system restarts. Not sure what actually uses this - it may be the | |
207 | * bootloader, rather than the boot ROM - contrary to the preserved | |
208 | * comment below. No return value. | |
209 | */ | |
210 | void omap3_ctrl_write_boot_mode(u8 bootmode) | |
211 | { | |
212 | u32 l; | |
213 | ||
214 | l = ('B' << 24) | ('M' << 16) | bootmode; | |
215 | ||
216 | /* | |
217 | * Reserve the first word in scratchpad for communicating | |
218 | * with the boot ROM. A pointer to a data structure | |
219 | * describing the boot process can be stored there, | |
220 | * cf. OMAP34xx TRM, Initialization / Software Booting | |
221 | * Configuration. | |
222 | * | |
223 | * XXX This should use some omap_ctrl_writel()-type function | |
224 | */ | |
edfaf05c | 225 | writel_relaxed(l, OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD + 4)); |
166353bd PW |
226 | } |
227 | ||
228 | #endif | |
229 | ||
90f1380e ORL |
230 | /** |
231 | * omap_ctrl_write_dsp_boot_addr - set boot address for a remote processor | |
232 | * @bootaddr: physical address of the boot loader | |
233 | * | |
234 | * Set boot address for the boot loader of a supported processor | |
235 | * when a power ON sequence occurs. | |
236 | */ | |
237 | void omap_ctrl_write_dsp_boot_addr(u32 bootaddr) | |
238 | { | |
239 | u32 offset = cpu_is_omap243x() ? OMAP243X_CONTROL_IVA2_BOOTADDR : | |
240 | cpu_is_omap34xx() ? OMAP343X_CONTROL_IVA2_BOOTADDR : | |
241 | cpu_is_omap44xx() ? OMAP4_CTRL_MODULE_CORE_DSP_BOOTADDR : | |
668468b1 | 242 | soc_is_omap54xx() ? OMAP4_CTRL_MODULE_CORE_DSP_BOOTADDR : |
90f1380e ORL |
243 | 0; |
244 | ||
245 | if (!offset) { | |
246 | pr_err("%s: unsupported omap type\n", __func__); | |
247 | return; | |
248 | } | |
249 | ||
250 | omap_ctrl_writel(bootaddr, offset); | |
251 | } | |
252 | ||
253 | /** | |
254 | * omap_ctrl_write_dsp_boot_mode - set boot mode for a remote processor | |
255 | * @bootmode: 8-bit value to pass to some boot code | |
256 | * | |
257 | * Sets boot mode for the boot loader of a supported processor | |
258 | * when a power ON sequence occurs. | |
259 | */ | |
260 | void omap_ctrl_write_dsp_boot_mode(u8 bootmode) | |
261 | { | |
262 | u32 offset = cpu_is_omap243x() ? OMAP243X_CONTROL_IVA2_BOOTMOD : | |
263 | cpu_is_omap34xx() ? OMAP343X_CONTROL_IVA2_BOOTMOD : | |
264 | 0; | |
265 | ||
266 | if (!offset) { | |
267 | pr_err("%s: unsupported omap type\n", __func__); | |
268 | return; | |
269 | } | |
270 | ||
271 | omap_ctrl_writel(bootmode, offset); | |
272 | } | |
273 | ||
c96631e1 | 274 | #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM) |
80140786 RN |
275 | /* |
276 | * Clears the scratchpad contents in case of cold boot- | |
277 | * called during bootup | |
278 | */ | |
279 | void omap3_clear_scratchpad_contents(void) | |
280 | { | |
281 | u32 max_offset = OMAP343X_SCRATCHPAD_ROM_OFFSET; | |
4d63bc1d | 282 | void __iomem *v_addr; |
80140786 RN |
283 | u32 offset = 0; |
284 | v_addr = OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD_ROM); | |
c4d7e58f | 285 | if (omap2_prm_read_mod_reg(OMAP3430_GR_MOD, OMAP3_PRM_RSTST_OFFSET) & |
2bc4ef71 | 286 | OMAP3430_GLOBAL_COLD_RST_MASK) { |
80140786 | 287 | for ( ; offset <= max_offset; offset += 0x4) |
edfaf05c | 288 | writel_relaxed(0x0, (v_addr + offset)); |
c4d7e58f PW |
289 | omap2_prm_set_mod_reg_bits(OMAP3430_GLOBAL_COLD_RST_MASK, |
290 | OMAP3430_GR_MOD, | |
291 | OMAP3_PRM_RSTST_OFFSET); | |
80140786 RN |
292 | } |
293 | } | |
294 | ||
295 | /* Populate the scratchpad structure with restore structure */ | |
296 | void omap3_save_scratchpad_contents(void) | |
297 | { | |
4d63bc1d | 298 | void __iomem *scratchpad_address; |
80140786 RN |
299 | u32 arm_context_addr; |
300 | struct omap3_scratchpad scratchpad_contents; | |
301 | struct omap3_scratchpad_prcm_block prcm_block_contents; | |
302 | struct omap3_scratchpad_sdrc_block sdrc_block_contents; | |
303 | ||
f7dfe3d8 JP |
304 | /* |
305 | * Populate the Scratchpad contents | |
306 | * | |
307 | * The "get_*restore_pointer" functions are used to provide a | |
308 | * physical restore address where the ROM code jumps while waking | |
309 | * up from MPU OFF/OSWR state. | |
310 | * The restore pointer is stored into the scratchpad. | |
311 | */ | |
80140786 | 312 | scratchpad_contents.boot_config_ptr = 0x0; |
458e999e NM |
313 | if (cpu_is_omap3630()) |
314 | scratchpad_contents.public_restore_ptr = | |
14c79bbe | 315 | virt_to_phys(omap3_restore_3630); |
458e999e | 316 | else if (omap_rev() != OMAP3430_REV_ES3_0 && |
0795a75a TK |
317 | omap_rev() != OMAP3430_REV_ES3_1) |
318 | scratchpad_contents.public_restore_ptr = | |
14c79bbe | 319 | virt_to_phys(omap3_restore); |
0795a75a TK |
320 | else |
321 | scratchpad_contents.public_restore_ptr = | |
14c79bbe KH |
322 | virt_to_phys(omap3_restore_es3); |
323 | ||
27d59a4a TK |
324 | if (omap_type() == OMAP2_DEVICE_TYPE_GP) |
325 | scratchpad_contents.secure_ram_restore_ptr = 0x0; | |
326 | else | |
327 | scratchpad_contents.secure_ram_restore_ptr = | |
328 | (u32) __pa(omap3_secure_ram_storage); | |
80140786 RN |
329 | scratchpad_contents.sdrc_module_semaphore = 0x0; |
330 | scratchpad_contents.prcm_block_offset = 0x2C; | |
331 | scratchpad_contents.sdrc_block_offset = 0x64; | |
332 | ||
333 | /* Populate the PRCM block contents */ | |
c4d7e58f PW |
334 | prcm_block_contents.prm_clksrc_ctrl = |
335 | omap2_prm_read_mod_reg(OMAP3430_GR_MOD, | |
336 | OMAP3_PRM_CLKSRC_CTRL_OFFSET); | |
337 | prcm_block_contents.prm_clksel = | |
338 | omap2_prm_read_mod_reg(OMAP3430_CCR_MOD, | |
339 | OMAP3_PRM_CLKSEL_OFFSET); | |
c6a2d839 TK |
340 | |
341 | omap3_cm_save_scratchpad_contents(prcm_block_contents.cm_contents); | |
342 | ||
80140786 RN |
343 | prcm_block_contents.prcm_block_size = 0x0; |
344 | ||
345 | /* Populate the SDRC block contents */ | |
346 | sdrc_block_contents.sysconfig = | |
347 | (sdrc_read_reg(SDRC_SYSCONFIG) & 0xFFFF); | |
348 | sdrc_block_contents.cs_cfg = | |
349 | (sdrc_read_reg(SDRC_CS_CFG) & 0xFFFF); | |
350 | sdrc_block_contents.sharing = | |
351 | (sdrc_read_reg(SDRC_SHARING) & 0xFFFF); | |
352 | sdrc_block_contents.err_type = | |
353 | (sdrc_read_reg(SDRC_ERR_TYPE) & 0xFFFF); | |
354 | sdrc_block_contents.dll_a_ctrl = sdrc_read_reg(SDRC_DLLA_CTRL); | |
355 | sdrc_block_contents.dll_b_ctrl = 0x0; | |
f265dc4c RN |
356 | /* |
357 | * Due to a OMAP3 errata (1.142), on EMU/HS devices SRDC should | |
358 | * be programed to issue automatic self refresh on timeout | |
359 | * of AUTO_CNT = 1 prior to any transition to OFF mode. | |
360 | */ | |
361 | if ((omap_type() != OMAP2_DEVICE_TYPE_GP) | |
362 | && (omap_rev() >= OMAP3430_REV_ES3_0)) | |
363 | sdrc_block_contents.power = (sdrc_read_reg(SDRC_POWER) & | |
364 | ~(SDRC_POWER_AUTOCOUNT_MASK| | |
365 | SDRC_POWER_CLKCTRL_MASK)) | | |
366 | (1 << SDRC_POWER_AUTOCOUNT_SHIFT) | | |
367 | SDRC_SELF_REFRESH_ON_AUTOCOUNT; | |
368 | else | |
369 | sdrc_block_contents.power = sdrc_read_reg(SDRC_POWER); | |
370 | ||
80140786 RN |
371 | sdrc_block_contents.cs_0 = 0x0; |
372 | sdrc_block_contents.mcfg_0 = sdrc_read_reg(SDRC_MCFG_0); | |
373 | sdrc_block_contents.mr_0 = (sdrc_read_reg(SDRC_MR_0) & 0xFFFF); | |
374 | sdrc_block_contents.emr_1_0 = 0x0; | |
375 | sdrc_block_contents.emr_2_0 = 0x0; | |
376 | sdrc_block_contents.emr_3_0 = 0x0; | |
377 | sdrc_block_contents.actim_ctrla_0 = | |
378 | sdrc_read_reg(SDRC_ACTIM_CTRL_A_0); | |
379 | sdrc_block_contents.actim_ctrlb_0 = | |
380 | sdrc_read_reg(SDRC_ACTIM_CTRL_B_0); | |
381 | sdrc_block_contents.rfr_ctrl_0 = | |
382 | sdrc_read_reg(SDRC_RFR_CTRL_0); | |
383 | sdrc_block_contents.cs_1 = 0x0; | |
384 | sdrc_block_contents.mcfg_1 = sdrc_read_reg(SDRC_MCFG_1); | |
385 | sdrc_block_contents.mr_1 = sdrc_read_reg(SDRC_MR_1) & 0xFFFF; | |
386 | sdrc_block_contents.emr_1_1 = 0x0; | |
387 | sdrc_block_contents.emr_2_1 = 0x0; | |
388 | sdrc_block_contents.emr_3_1 = 0x0; | |
389 | sdrc_block_contents.actim_ctrla_1 = | |
390 | sdrc_read_reg(SDRC_ACTIM_CTRL_A_1); | |
391 | sdrc_block_contents.actim_ctrlb_1 = | |
392 | sdrc_read_reg(SDRC_ACTIM_CTRL_B_1); | |
393 | sdrc_block_contents.rfr_ctrl_1 = | |
394 | sdrc_read_reg(SDRC_RFR_CTRL_1); | |
395 | sdrc_block_contents.dcdl_1_ctrl = 0x0; | |
396 | sdrc_block_contents.dcdl_2_ctrl = 0x0; | |
397 | sdrc_block_contents.flags = 0x0; | |
398 | sdrc_block_contents.block_size = 0x0; | |
399 | ||
400 | arm_context_addr = virt_to_phys(omap3_arm_context); | |
401 | ||
402 | /* Copy all the contents to the scratchpad location */ | |
403 | scratchpad_address = OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD); | |
404 | memcpy_toio(scratchpad_address, &scratchpad_contents, | |
405 | sizeof(scratchpad_contents)); | |
406 | /* Scratchpad contents being 32 bits, a divide by 4 done here */ | |
407 | memcpy_toio(scratchpad_address + | |
408 | scratchpad_contents.prcm_block_offset, | |
409 | &prcm_block_contents, sizeof(prcm_block_contents)); | |
410 | memcpy_toio(scratchpad_address + | |
411 | scratchpad_contents.sdrc_block_offset, | |
412 | &sdrc_block_contents, sizeof(sdrc_block_contents)); | |
413 | /* | |
414 | * Copies the address of the location in SDRAM where ARM | |
415 | * registers get saved during a MPU OFF transition. | |
416 | */ | |
417 | memcpy_toio(scratchpad_address + | |
418 | scratchpad_contents.sdrc_block_offset + | |
419 | sizeof(sdrc_block_contents), &arm_context_addr, 4); | |
420 | } | |
421 | ||
c96631e1 RN |
422 | void omap3_control_save_context(void) |
423 | { | |
424 | control_context.sysconfig = omap_ctrl_readl(OMAP2_CONTROL_SYSCONFIG); | |
425 | control_context.devconf0 = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0); | |
426 | control_context.mem_dftrw0 = | |
427 | omap_ctrl_readl(OMAP343X_CONTROL_MEM_DFTRW0); | |
428 | control_context.mem_dftrw1 = | |
429 | omap_ctrl_readl(OMAP343X_CONTROL_MEM_DFTRW1); | |
430 | control_context.msuspendmux_0 = | |
431 | omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_0); | |
432 | control_context.msuspendmux_1 = | |
433 | omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_1); | |
434 | control_context.msuspendmux_2 = | |
435 | omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_2); | |
436 | control_context.msuspendmux_3 = | |
437 | omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_3); | |
438 | control_context.msuspendmux_4 = | |
439 | omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_4); | |
440 | control_context.msuspendmux_5 = | |
441 | omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_5); | |
442 | control_context.sec_ctrl = omap_ctrl_readl(OMAP2_CONTROL_SEC_CTRL); | |
443 | control_context.devconf1 = omap_ctrl_readl(OMAP343X_CONTROL_DEVCONF1); | |
444 | control_context.csirxfe = omap_ctrl_readl(OMAP343X_CONTROL_CSIRXFE); | |
445 | control_context.iva2_bootaddr = | |
446 | omap_ctrl_readl(OMAP343X_CONTROL_IVA2_BOOTADDR); | |
447 | control_context.iva2_bootmod = | |
448 | omap_ctrl_readl(OMAP343X_CONTROL_IVA2_BOOTMOD); | |
449 | control_context.debobs_0 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(0)); | |
450 | control_context.debobs_1 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(1)); | |
451 | control_context.debobs_2 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(2)); | |
452 | control_context.debobs_3 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(3)); | |
453 | control_context.debobs_4 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(4)); | |
454 | control_context.debobs_5 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(5)); | |
455 | control_context.debobs_6 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(6)); | |
456 | control_context.debobs_7 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(7)); | |
457 | control_context.debobs_8 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(8)); | |
458 | control_context.prog_io0 = omap_ctrl_readl(OMAP343X_CONTROL_PROG_IO0); | |
459 | control_context.prog_io1 = omap_ctrl_readl(OMAP343X_CONTROL_PROG_IO1); | |
460 | control_context.dss_dpll_spreading = | |
461 | omap_ctrl_readl(OMAP343X_CONTROL_DSS_DPLL_SPREADING); | |
462 | control_context.core_dpll_spreading = | |
463 | omap_ctrl_readl(OMAP343X_CONTROL_CORE_DPLL_SPREADING); | |
464 | control_context.per_dpll_spreading = | |
465 | omap_ctrl_readl(OMAP343X_CONTROL_PER_DPLL_SPREADING); | |
466 | control_context.usbhost_dpll_spreading = | |
467 | omap_ctrl_readl(OMAP343X_CONTROL_USBHOST_DPLL_SPREADING); | |
468 | control_context.pbias_lite = | |
469 | omap_ctrl_readl(OMAP343X_CONTROL_PBIAS_LITE); | |
470 | control_context.temp_sensor = | |
471 | omap_ctrl_readl(OMAP343X_CONTROL_TEMP_SENSOR); | |
472 | control_context.sramldo4 = omap_ctrl_readl(OMAP343X_CONTROL_SRAMLDO4); | |
473 | control_context.sramldo5 = omap_ctrl_readl(OMAP343X_CONTROL_SRAMLDO5); | |
474 | control_context.csi = omap_ctrl_readl(OMAP343X_CONTROL_CSI); | |
f5f9d132 PW |
475 | control_context.padconf_sys_nirq = |
476 | omap_ctrl_readl(OMAP343X_CONTROL_PADCONF_SYSNIRQ); | |
c96631e1 RN |
477 | return; |
478 | } | |
479 | ||
480 | void omap3_control_restore_context(void) | |
481 | { | |
482 | omap_ctrl_writel(control_context.sysconfig, OMAP2_CONTROL_SYSCONFIG); | |
483 | omap_ctrl_writel(control_context.devconf0, OMAP2_CONTROL_DEVCONF0); | |
484 | omap_ctrl_writel(control_context.mem_dftrw0, | |
485 | OMAP343X_CONTROL_MEM_DFTRW0); | |
486 | omap_ctrl_writel(control_context.mem_dftrw1, | |
487 | OMAP343X_CONTROL_MEM_DFTRW1); | |
488 | omap_ctrl_writel(control_context.msuspendmux_0, | |
489 | OMAP2_CONTROL_MSUSPENDMUX_0); | |
490 | omap_ctrl_writel(control_context.msuspendmux_1, | |
491 | OMAP2_CONTROL_MSUSPENDMUX_1); | |
492 | omap_ctrl_writel(control_context.msuspendmux_2, | |
493 | OMAP2_CONTROL_MSUSPENDMUX_2); | |
494 | omap_ctrl_writel(control_context.msuspendmux_3, | |
495 | OMAP2_CONTROL_MSUSPENDMUX_3); | |
496 | omap_ctrl_writel(control_context.msuspendmux_4, | |
497 | OMAP2_CONTROL_MSUSPENDMUX_4); | |
498 | omap_ctrl_writel(control_context.msuspendmux_5, | |
499 | OMAP2_CONTROL_MSUSPENDMUX_5); | |
500 | omap_ctrl_writel(control_context.sec_ctrl, OMAP2_CONTROL_SEC_CTRL); | |
501 | omap_ctrl_writel(control_context.devconf1, OMAP343X_CONTROL_DEVCONF1); | |
502 | omap_ctrl_writel(control_context.csirxfe, OMAP343X_CONTROL_CSIRXFE); | |
503 | omap_ctrl_writel(control_context.iva2_bootaddr, | |
504 | OMAP343X_CONTROL_IVA2_BOOTADDR); | |
505 | omap_ctrl_writel(control_context.iva2_bootmod, | |
506 | OMAP343X_CONTROL_IVA2_BOOTMOD); | |
507 | omap_ctrl_writel(control_context.debobs_0, OMAP343X_CONTROL_DEBOBS(0)); | |
508 | omap_ctrl_writel(control_context.debobs_1, OMAP343X_CONTROL_DEBOBS(1)); | |
509 | omap_ctrl_writel(control_context.debobs_2, OMAP343X_CONTROL_DEBOBS(2)); | |
510 | omap_ctrl_writel(control_context.debobs_3, OMAP343X_CONTROL_DEBOBS(3)); | |
511 | omap_ctrl_writel(control_context.debobs_4, OMAP343X_CONTROL_DEBOBS(4)); | |
512 | omap_ctrl_writel(control_context.debobs_5, OMAP343X_CONTROL_DEBOBS(5)); | |
513 | omap_ctrl_writel(control_context.debobs_6, OMAP343X_CONTROL_DEBOBS(6)); | |
514 | omap_ctrl_writel(control_context.debobs_7, OMAP343X_CONTROL_DEBOBS(7)); | |
515 | omap_ctrl_writel(control_context.debobs_8, OMAP343X_CONTROL_DEBOBS(8)); | |
516 | omap_ctrl_writel(control_context.prog_io0, OMAP343X_CONTROL_PROG_IO0); | |
517 | omap_ctrl_writel(control_context.prog_io1, OMAP343X_CONTROL_PROG_IO1); | |
518 | omap_ctrl_writel(control_context.dss_dpll_spreading, | |
519 | OMAP343X_CONTROL_DSS_DPLL_SPREADING); | |
520 | omap_ctrl_writel(control_context.core_dpll_spreading, | |
521 | OMAP343X_CONTROL_CORE_DPLL_SPREADING); | |
522 | omap_ctrl_writel(control_context.per_dpll_spreading, | |
523 | OMAP343X_CONTROL_PER_DPLL_SPREADING); | |
524 | omap_ctrl_writel(control_context.usbhost_dpll_spreading, | |
525 | OMAP343X_CONTROL_USBHOST_DPLL_SPREADING); | |
526 | omap_ctrl_writel(control_context.pbias_lite, | |
527 | OMAP343X_CONTROL_PBIAS_LITE); | |
528 | omap_ctrl_writel(control_context.temp_sensor, | |
529 | OMAP343X_CONTROL_TEMP_SENSOR); | |
530 | omap_ctrl_writel(control_context.sramldo4, OMAP343X_CONTROL_SRAMLDO4); | |
531 | omap_ctrl_writel(control_context.sramldo5, OMAP343X_CONTROL_SRAMLDO5); | |
532 | omap_ctrl_writel(control_context.csi, OMAP343X_CONTROL_CSI); | |
f5f9d132 PW |
533 | omap_ctrl_writel(control_context.padconf_sys_nirq, |
534 | OMAP343X_CONTROL_PADCONF_SYSNIRQ); | |
c96631e1 RN |
535 | return; |
536 | } | |
458e999e NM |
537 | |
538 | void omap3630_ctrl_disable_rta(void) | |
539 | { | |
540 | if (!cpu_is_omap3630()) | |
541 | return; | |
542 | omap_ctrl_writel(OMAP36XX_RTA_DISABLE, OMAP36XX_CONTROL_MEM_RTA_CTRL); | |
543 | } | |
544 | ||
596efe47 PW |
545 | /** |
546 | * omap3_ctrl_save_padconf - save padconf registers to scratchpad RAM | |
547 | * | |
548 | * Tell the SCM to start saving the padconf registers, then wait for | |
549 | * the process to complete. Returns 0 unconditionally, although it | |
550 | * should also eventually be able to return -ETIMEDOUT, if the save | |
551 | * does not complete. | |
552 | * | |
553 | * XXX This function is missing a timeout. What should it be? | |
554 | */ | |
555 | int omap3_ctrl_save_padconf(void) | |
556 | { | |
557 | u32 cpo; | |
558 | ||
559 | /* Save the padconf registers */ | |
560 | cpo = omap_ctrl_readl(OMAP343X_CONTROL_PADCONF_OFF); | |
561 | cpo |= START_PADCONF_SAVE; | |
562 | omap_ctrl_writel(cpo, OMAP343X_CONTROL_PADCONF_OFF); | |
563 | ||
564 | /* wait for the save to complete */ | |
565 | while (!(omap_ctrl_readl(OMAP343X_CONTROL_GENERAL_PURPOSE_STATUS) | |
566 | & PADCONF_SAVE_DONE)) | |
567 | udelay(1); | |
568 | ||
569 | return 0; | |
570 | } | |
571 | ||
49e03402 TK |
572 | /** |
573 | * omap3_ctrl_set_iva_bootmode_idle - sets the IVA2 bootmode to idle | |
574 | * | |
575 | * Sets the bootmode for IVA2 to idle. This is needed by the PM code to | |
576 | * force disable IVA2 so that it does not prevent any low-power states. | |
577 | */ | |
578 | void omap3_ctrl_set_iva_bootmode_idle(void) | |
579 | { | |
580 | omap_ctrl_writel(OMAP3_IVA2_BOOTMOD_IDLE, | |
581 | OMAP343X_CONTROL_IVA2_BOOTMOD); | |
582 | } | |
c96631e1 | 583 | #endif /* CONFIG_ARCH_OMAP3 && CONFIG_PM */ |