Commit | Line | Data |
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69d88a00 PW |
1 | /* |
2 | * OMAP2/3 System Control Module register access | |
3 | * | |
4 | * Copyright (C) 2007 Texas Instruments, Inc. | |
5 | * Copyright (C) 2007 Nokia Corporation | |
6 | * | |
7 | * Written by Paul Walmsley | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as | |
11 | * published by the Free Software Foundation. | |
12 | */ | |
13 | #undef DEBUG | |
14 | ||
15 | #include <linux/kernel.h> | |
a58caad1 | 16 | #include <linux/io.h> |
69d88a00 | 17 | |
ce491cf8 | 18 | #include <plat/common.h> |
80140786 | 19 | #include <plat/sdrc.h> |
4814ced5 | 20 | |
80140786 RN |
21 | #include "cm-regbits-34xx.h" |
22 | #include "prm-regbits-34xx.h" | |
59fb659b PW |
23 | #include "prm2xxx_3xxx.h" |
24 | #include "cm2xxx_3xxx.h" | |
80140786 | 25 | #include "sdrc.h" |
38815733 | 26 | #include "pm.h" |
4814ced5 | 27 | #include "control.h" |
69d88a00 | 28 | |
596efe47 PW |
29 | /* Used by omap3_ctrl_save_padconf() */ |
30 | #define START_PADCONF_SAVE 0x2 | |
31 | #define PADCONF_SAVE_DONE 0x1 | |
32 | ||
a58caad1 | 33 | static void __iomem *omap2_ctrl_base; |
0c349246 | 34 | static void __iomem *omap4_ctrl_pad_base; |
69d88a00 | 35 | |
c96631e1 | 36 | #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM) |
80140786 RN |
37 | struct omap3_scratchpad { |
38 | u32 boot_config_ptr; | |
39 | u32 public_restore_ptr; | |
40 | u32 secure_ram_restore_ptr; | |
41 | u32 sdrc_module_semaphore; | |
42 | u32 prcm_block_offset; | |
43 | u32 sdrc_block_offset; | |
44 | }; | |
45 | ||
46 | struct omap3_scratchpad_prcm_block { | |
47 | u32 prm_clksrc_ctrl; | |
48 | u32 prm_clksel; | |
49 | u32 cm_clksel_core; | |
50 | u32 cm_clksel_wkup; | |
51 | u32 cm_clken_pll; | |
52 | u32 cm_autoidle_pll; | |
53 | u32 cm_clksel1_pll; | |
54 | u32 cm_clksel2_pll; | |
55 | u32 cm_clksel3_pll; | |
56 | u32 cm_clken_pll_mpu; | |
57 | u32 cm_autoidle_pll_mpu; | |
58 | u32 cm_clksel1_pll_mpu; | |
59 | u32 cm_clksel2_pll_mpu; | |
60 | u32 prcm_block_size; | |
61 | }; | |
62 | ||
63 | struct omap3_scratchpad_sdrc_block { | |
64 | u16 sysconfig; | |
65 | u16 cs_cfg; | |
66 | u16 sharing; | |
67 | u16 err_type; | |
68 | u32 dll_a_ctrl; | |
69 | u32 dll_b_ctrl; | |
70 | u32 power; | |
71 | u32 cs_0; | |
72 | u32 mcfg_0; | |
73 | u16 mr_0; | |
74 | u16 emr_1_0; | |
75 | u16 emr_2_0; | |
76 | u16 emr_3_0; | |
77 | u32 actim_ctrla_0; | |
78 | u32 actim_ctrlb_0; | |
79 | u32 rfr_ctrl_0; | |
80 | u32 cs_1; | |
81 | u32 mcfg_1; | |
82 | u16 mr_1; | |
83 | u16 emr_1_1; | |
84 | u16 emr_2_1; | |
85 | u16 emr_3_1; | |
86 | u32 actim_ctrla_1; | |
87 | u32 actim_ctrlb_1; | |
88 | u32 rfr_ctrl_1; | |
89 | u16 dcdl_1_ctrl; | |
90 | u16 dcdl_2_ctrl; | |
91 | u32 flags; | |
92 | u32 block_size; | |
93 | }; | |
94 | ||
27d59a4a TK |
95 | void *omap3_secure_ram_storage; |
96 | ||
80140786 RN |
97 | /* |
98 | * This is used to store ARM registers in SDRAM before attempting | |
99 | * an MPU OFF. The save and restore happens from the SRAM sleep code. | |
100 | * The address is stored in scratchpad, so that it can be used | |
101 | * during the restore path. | |
102 | */ | |
103 | u32 omap3_arm_context[128]; | |
104 | ||
c96631e1 RN |
105 | struct omap3_control_regs { |
106 | u32 sysconfig; | |
107 | u32 devconf0; | |
108 | u32 mem_dftrw0; | |
109 | u32 mem_dftrw1; | |
110 | u32 msuspendmux_0; | |
111 | u32 msuspendmux_1; | |
112 | u32 msuspendmux_2; | |
113 | u32 msuspendmux_3; | |
114 | u32 msuspendmux_4; | |
115 | u32 msuspendmux_5; | |
116 | u32 sec_ctrl; | |
117 | u32 devconf1; | |
118 | u32 csirxfe; | |
119 | u32 iva2_bootaddr; | |
120 | u32 iva2_bootmod; | |
121 | u32 debobs_0; | |
122 | u32 debobs_1; | |
123 | u32 debobs_2; | |
124 | u32 debobs_3; | |
125 | u32 debobs_4; | |
126 | u32 debobs_5; | |
127 | u32 debobs_6; | |
128 | u32 debobs_7; | |
129 | u32 debobs_8; | |
130 | u32 prog_io0; | |
131 | u32 prog_io1; | |
132 | u32 dss_dpll_spreading; | |
133 | u32 core_dpll_spreading; | |
134 | u32 per_dpll_spreading; | |
135 | u32 usbhost_dpll_spreading; | |
136 | u32 pbias_lite; | |
137 | u32 temp_sensor; | |
138 | u32 sramldo4; | |
139 | u32 sramldo5; | |
140 | u32 csi; | |
f5f9d132 | 141 | u32 padconf_sys_nirq; |
c96631e1 RN |
142 | }; |
143 | ||
144 | static struct omap3_control_regs control_context; | |
145 | #endif /* CONFIG_ARCH_OMAP3 && CONFIG_PM */ | |
146 | ||
a58caad1 | 147 | #define OMAP_CTRL_REGADDR(reg) (omap2_ctrl_base + (reg)) |
70ba71a2 | 148 | #define OMAP4_CTRL_PAD_REGADDR(reg) (omap4_ctrl_pad_base + (reg)) |
69d88a00 | 149 | |
a58caad1 | 150 | void __init omap2_set_globals_control(struct omap_globals *omap2_globals) |
69d88a00 | 151 | { |
b7ebb10b SS |
152 | /* Static mapping, never released */ |
153 | if (omap2_globals->ctrl) { | |
154 | omap2_ctrl_base = ioremap(omap2_globals->ctrl, SZ_4K); | |
155 | WARN_ON(!omap2_ctrl_base); | |
156 | } | |
0c349246 SS |
157 | |
158 | /* Static mapping, never released */ | |
159 | if (omap2_globals->ctrl_pad) { | |
160 | omap4_ctrl_pad_base = ioremap(omap2_globals->ctrl_pad, SZ_4K); | |
161 | WARN_ON(!omap4_ctrl_pad_base); | |
162 | } | |
69d88a00 PW |
163 | } |
164 | ||
a58caad1 | 165 | void __iomem *omap_ctrl_base_get(void) |
69d88a00 PW |
166 | { |
167 | return omap2_ctrl_base; | |
168 | } | |
169 | ||
170 | u8 omap_ctrl_readb(u16 offset) | |
171 | { | |
172 | return __raw_readb(OMAP_CTRL_REGADDR(offset)); | |
173 | } | |
174 | ||
175 | u16 omap_ctrl_readw(u16 offset) | |
176 | { | |
177 | return __raw_readw(OMAP_CTRL_REGADDR(offset)); | |
178 | } | |
179 | ||
180 | u32 omap_ctrl_readl(u16 offset) | |
181 | { | |
182 | return __raw_readl(OMAP_CTRL_REGADDR(offset)); | |
183 | } | |
184 | ||
185 | void omap_ctrl_writeb(u8 val, u16 offset) | |
186 | { | |
69d88a00 PW |
187 | __raw_writeb(val, OMAP_CTRL_REGADDR(offset)); |
188 | } | |
189 | ||
190 | void omap_ctrl_writew(u16 val, u16 offset) | |
191 | { | |
69d88a00 PW |
192 | __raw_writew(val, OMAP_CTRL_REGADDR(offset)); |
193 | } | |
194 | ||
195 | void omap_ctrl_writel(u32 val, u16 offset) | |
196 | { | |
69d88a00 PW |
197 | __raw_writel(val, OMAP_CTRL_REGADDR(offset)); |
198 | } | |
199 | ||
70ba71a2 SS |
200 | /* |
201 | * On OMAP4 control pad are not addressable from control | |
202 | * core base. So the common omap_ctrl_read/write APIs breaks | |
203 | * Hence export separate APIs to manage the omap4 pad control | |
204 | * registers. This APIs will work only for OMAP4 | |
205 | */ | |
206 | ||
207 | u32 omap4_ctrl_pad_readl(u16 offset) | |
208 | { | |
209 | return __raw_readl(OMAP4_CTRL_PAD_REGADDR(offset)); | |
210 | } | |
211 | ||
212 | void omap4_ctrl_pad_writel(u32 val, u16 offset) | |
213 | { | |
214 | __raw_writel(val, OMAP4_CTRL_PAD_REGADDR(offset)); | |
215 | } | |
216 | ||
166353bd PW |
217 | #ifdef CONFIG_ARCH_OMAP3 |
218 | ||
219 | /** | |
220 | * omap3_ctrl_write_boot_mode - set scratchpad boot mode for the next boot | |
221 | * @bootmode: 8-bit value to pass to some boot code | |
222 | * | |
223 | * Set the bootmode in the scratchpad RAM. This is used after the | |
224 | * system restarts. Not sure what actually uses this - it may be the | |
225 | * bootloader, rather than the boot ROM - contrary to the preserved | |
226 | * comment below. No return value. | |
227 | */ | |
228 | void omap3_ctrl_write_boot_mode(u8 bootmode) | |
229 | { | |
230 | u32 l; | |
231 | ||
232 | l = ('B' << 24) | ('M' << 16) | bootmode; | |
233 | ||
234 | /* | |
235 | * Reserve the first word in scratchpad for communicating | |
236 | * with the boot ROM. A pointer to a data structure | |
237 | * describing the boot process can be stored there, | |
238 | * cf. OMAP34xx TRM, Initialization / Software Booting | |
239 | * Configuration. | |
240 | * | |
241 | * XXX This should use some omap_ctrl_writel()-type function | |
242 | */ | |
243 | __raw_writel(l, OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD + 4)); | |
244 | } | |
245 | ||
246 | #endif | |
247 | ||
c96631e1 | 248 | #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM) |
80140786 RN |
249 | /* |
250 | * Clears the scratchpad contents in case of cold boot- | |
251 | * called during bootup | |
252 | */ | |
253 | void omap3_clear_scratchpad_contents(void) | |
254 | { | |
255 | u32 max_offset = OMAP343X_SCRATCHPAD_ROM_OFFSET; | |
4d63bc1d | 256 | void __iomem *v_addr; |
80140786 RN |
257 | u32 offset = 0; |
258 | v_addr = OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD_ROM); | |
c4d7e58f | 259 | if (omap2_prm_read_mod_reg(OMAP3430_GR_MOD, OMAP3_PRM_RSTST_OFFSET) & |
2bc4ef71 | 260 | OMAP3430_GLOBAL_COLD_RST_MASK) { |
80140786 RN |
261 | for ( ; offset <= max_offset; offset += 0x4) |
262 | __raw_writel(0x0, (v_addr + offset)); | |
c4d7e58f PW |
263 | omap2_prm_set_mod_reg_bits(OMAP3430_GLOBAL_COLD_RST_MASK, |
264 | OMAP3430_GR_MOD, | |
265 | OMAP3_PRM_RSTST_OFFSET); | |
80140786 RN |
266 | } |
267 | } | |
268 | ||
269 | /* Populate the scratchpad structure with restore structure */ | |
270 | void omap3_save_scratchpad_contents(void) | |
271 | { | |
4d63bc1d | 272 | void __iomem *scratchpad_address; |
80140786 RN |
273 | u32 arm_context_addr; |
274 | struct omap3_scratchpad scratchpad_contents; | |
275 | struct omap3_scratchpad_prcm_block prcm_block_contents; | |
276 | struct omap3_scratchpad_sdrc_block sdrc_block_contents; | |
277 | ||
f7dfe3d8 JP |
278 | /* |
279 | * Populate the Scratchpad contents | |
280 | * | |
281 | * The "get_*restore_pointer" functions are used to provide a | |
282 | * physical restore address where the ROM code jumps while waking | |
283 | * up from MPU OFF/OSWR state. | |
284 | * The restore pointer is stored into the scratchpad. | |
285 | */ | |
80140786 | 286 | scratchpad_contents.boot_config_ptr = 0x0; |
458e999e NM |
287 | if (cpu_is_omap3630()) |
288 | scratchpad_contents.public_restore_ptr = | |
289 | virt_to_phys(get_omap3630_restore_pointer()); | |
290 | else if (omap_rev() != OMAP3430_REV_ES3_0 && | |
0795a75a TK |
291 | omap_rev() != OMAP3430_REV_ES3_1) |
292 | scratchpad_contents.public_restore_ptr = | |
293 | virt_to_phys(get_restore_pointer()); | |
294 | else | |
295 | scratchpad_contents.public_restore_ptr = | |
296 | virt_to_phys(get_es3_restore_pointer()); | |
27d59a4a TK |
297 | if (omap_type() == OMAP2_DEVICE_TYPE_GP) |
298 | scratchpad_contents.secure_ram_restore_ptr = 0x0; | |
299 | else | |
300 | scratchpad_contents.secure_ram_restore_ptr = | |
301 | (u32) __pa(omap3_secure_ram_storage); | |
80140786 RN |
302 | scratchpad_contents.sdrc_module_semaphore = 0x0; |
303 | scratchpad_contents.prcm_block_offset = 0x2C; | |
304 | scratchpad_contents.sdrc_block_offset = 0x64; | |
305 | ||
306 | /* Populate the PRCM block contents */ | |
c4d7e58f PW |
307 | prcm_block_contents.prm_clksrc_ctrl = |
308 | omap2_prm_read_mod_reg(OMAP3430_GR_MOD, | |
309 | OMAP3_PRM_CLKSRC_CTRL_OFFSET); | |
310 | prcm_block_contents.prm_clksel = | |
311 | omap2_prm_read_mod_reg(OMAP3430_CCR_MOD, | |
312 | OMAP3_PRM_CLKSEL_OFFSET); | |
80140786 | 313 | prcm_block_contents.cm_clksel_core = |
c4d7e58f | 314 | omap2_cm_read_mod_reg(CORE_MOD, CM_CLKSEL); |
80140786 | 315 | prcm_block_contents.cm_clksel_wkup = |
c4d7e58f | 316 | omap2_cm_read_mod_reg(WKUP_MOD, CM_CLKSEL); |
80140786 | 317 | prcm_block_contents.cm_clken_pll = |
c4d7e58f | 318 | omap2_cm_read_mod_reg(PLL_MOD, CM_CLKEN); |
a8ae645c EV |
319 | /* |
320 | * As per erratum i671, ROM code does not respect the PER DPLL | |
321 | * programming scheme if CM_AUTOIDLE_PLL..AUTO_PERIPH_DPLL == 1. | |
322 | * Then, in anycase, clear these bits to avoid extra latencies. | |
323 | */ | |
80140786 | 324 | prcm_block_contents.cm_autoidle_pll = |
a8ae645c EV |
325 | omap2_cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE) & |
326 | ~OMAP3430_AUTO_PERIPH_DPLL_MASK; | |
80140786 | 327 | prcm_block_contents.cm_clksel1_pll = |
c4d7e58f | 328 | omap2_cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL1_PLL); |
80140786 | 329 | prcm_block_contents.cm_clksel2_pll = |
c4d7e58f | 330 | omap2_cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL2_PLL); |
80140786 | 331 | prcm_block_contents.cm_clksel3_pll = |
c4d7e58f | 332 | omap2_cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL3); |
80140786 | 333 | prcm_block_contents.cm_clken_pll_mpu = |
c4d7e58f | 334 | omap2_cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKEN_PLL); |
80140786 | 335 | prcm_block_contents.cm_autoidle_pll_mpu = |
c4d7e58f | 336 | omap2_cm_read_mod_reg(MPU_MOD, OMAP3430_CM_AUTOIDLE_PLL); |
80140786 | 337 | prcm_block_contents.cm_clksel1_pll_mpu = |
c4d7e58f | 338 | omap2_cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL); |
80140786 | 339 | prcm_block_contents.cm_clksel2_pll_mpu = |
c4d7e58f | 340 | omap2_cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL); |
80140786 RN |
341 | prcm_block_contents.prcm_block_size = 0x0; |
342 | ||
343 | /* Populate the SDRC block contents */ | |
344 | sdrc_block_contents.sysconfig = | |
345 | (sdrc_read_reg(SDRC_SYSCONFIG) & 0xFFFF); | |
346 | sdrc_block_contents.cs_cfg = | |
347 | (sdrc_read_reg(SDRC_CS_CFG) & 0xFFFF); | |
348 | sdrc_block_contents.sharing = | |
349 | (sdrc_read_reg(SDRC_SHARING) & 0xFFFF); | |
350 | sdrc_block_contents.err_type = | |
351 | (sdrc_read_reg(SDRC_ERR_TYPE) & 0xFFFF); | |
352 | sdrc_block_contents.dll_a_ctrl = sdrc_read_reg(SDRC_DLLA_CTRL); | |
353 | sdrc_block_contents.dll_b_ctrl = 0x0; | |
f265dc4c RN |
354 | /* |
355 | * Due to a OMAP3 errata (1.142), on EMU/HS devices SRDC should | |
356 | * be programed to issue automatic self refresh on timeout | |
357 | * of AUTO_CNT = 1 prior to any transition to OFF mode. | |
358 | */ | |
359 | if ((omap_type() != OMAP2_DEVICE_TYPE_GP) | |
360 | && (omap_rev() >= OMAP3430_REV_ES3_0)) | |
361 | sdrc_block_contents.power = (sdrc_read_reg(SDRC_POWER) & | |
362 | ~(SDRC_POWER_AUTOCOUNT_MASK| | |
363 | SDRC_POWER_CLKCTRL_MASK)) | | |
364 | (1 << SDRC_POWER_AUTOCOUNT_SHIFT) | | |
365 | SDRC_SELF_REFRESH_ON_AUTOCOUNT; | |
366 | else | |
367 | sdrc_block_contents.power = sdrc_read_reg(SDRC_POWER); | |
368 | ||
80140786 RN |
369 | sdrc_block_contents.cs_0 = 0x0; |
370 | sdrc_block_contents.mcfg_0 = sdrc_read_reg(SDRC_MCFG_0); | |
371 | sdrc_block_contents.mr_0 = (sdrc_read_reg(SDRC_MR_0) & 0xFFFF); | |
372 | sdrc_block_contents.emr_1_0 = 0x0; | |
373 | sdrc_block_contents.emr_2_0 = 0x0; | |
374 | sdrc_block_contents.emr_3_0 = 0x0; | |
375 | sdrc_block_contents.actim_ctrla_0 = | |
376 | sdrc_read_reg(SDRC_ACTIM_CTRL_A_0); | |
377 | sdrc_block_contents.actim_ctrlb_0 = | |
378 | sdrc_read_reg(SDRC_ACTIM_CTRL_B_0); | |
379 | sdrc_block_contents.rfr_ctrl_0 = | |
380 | sdrc_read_reg(SDRC_RFR_CTRL_0); | |
381 | sdrc_block_contents.cs_1 = 0x0; | |
382 | sdrc_block_contents.mcfg_1 = sdrc_read_reg(SDRC_MCFG_1); | |
383 | sdrc_block_contents.mr_1 = sdrc_read_reg(SDRC_MR_1) & 0xFFFF; | |
384 | sdrc_block_contents.emr_1_1 = 0x0; | |
385 | sdrc_block_contents.emr_2_1 = 0x0; | |
386 | sdrc_block_contents.emr_3_1 = 0x0; | |
387 | sdrc_block_contents.actim_ctrla_1 = | |
388 | sdrc_read_reg(SDRC_ACTIM_CTRL_A_1); | |
389 | sdrc_block_contents.actim_ctrlb_1 = | |
390 | sdrc_read_reg(SDRC_ACTIM_CTRL_B_1); | |
391 | sdrc_block_contents.rfr_ctrl_1 = | |
392 | sdrc_read_reg(SDRC_RFR_CTRL_1); | |
393 | sdrc_block_contents.dcdl_1_ctrl = 0x0; | |
394 | sdrc_block_contents.dcdl_2_ctrl = 0x0; | |
395 | sdrc_block_contents.flags = 0x0; | |
396 | sdrc_block_contents.block_size = 0x0; | |
397 | ||
398 | arm_context_addr = virt_to_phys(omap3_arm_context); | |
399 | ||
400 | /* Copy all the contents to the scratchpad location */ | |
401 | scratchpad_address = OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD); | |
402 | memcpy_toio(scratchpad_address, &scratchpad_contents, | |
403 | sizeof(scratchpad_contents)); | |
404 | /* Scratchpad contents being 32 bits, a divide by 4 done here */ | |
405 | memcpy_toio(scratchpad_address + | |
406 | scratchpad_contents.prcm_block_offset, | |
407 | &prcm_block_contents, sizeof(prcm_block_contents)); | |
408 | memcpy_toio(scratchpad_address + | |
409 | scratchpad_contents.sdrc_block_offset, | |
410 | &sdrc_block_contents, sizeof(sdrc_block_contents)); | |
411 | /* | |
412 | * Copies the address of the location in SDRAM where ARM | |
413 | * registers get saved during a MPU OFF transition. | |
414 | */ | |
415 | memcpy_toio(scratchpad_address + | |
416 | scratchpad_contents.sdrc_block_offset + | |
417 | sizeof(sdrc_block_contents), &arm_context_addr, 4); | |
418 | } | |
419 | ||
c96631e1 RN |
420 | void omap3_control_save_context(void) |
421 | { | |
422 | control_context.sysconfig = omap_ctrl_readl(OMAP2_CONTROL_SYSCONFIG); | |
423 | control_context.devconf0 = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0); | |
424 | control_context.mem_dftrw0 = | |
425 | omap_ctrl_readl(OMAP343X_CONTROL_MEM_DFTRW0); | |
426 | control_context.mem_dftrw1 = | |
427 | omap_ctrl_readl(OMAP343X_CONTROL_MEM_DFTRW1); | |
428 | control_context.msuspendmux_0 = | |
429 | omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_0); | |
430 | control_context.msuspendmux_1 = | |
431 | omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_1); | |
432 | control_context.msuspendmux_2 = | |
433 | omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_2); | |
434 | control_context.msuspendmux_3 = | |
435 | omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_3); | |
436 | control_context.msuspendmux_4 = | |
437 | omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_4); | |
438 | control_context.msuspendmux_5 = | |
439 | omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_5); | |
440 | control_context.sec_ctrl = omap_ctrl_readl(OMAP2_CONTROL_SEC_CTRL); | |
441 | control_context.devconf1 = omap_ctrl_readl(OMAP343X_CONTROL_DEVCONF1); | |
442 | control_context.csirxfe = omap_ctrl_readl(OMAP343X_CONTROL_CSIRXFE); | |
443 | control_context.iva2_bootaddr = | |
444 | omap_ctrl_readl(OMAP343X_CONTROL_IVA2_BOOTADDR); | |
445 | control_context.iva2_bootmod = | |
446 | omap_ctrl_readl(OMAP343X_CONTROL_IVA2_BOOTMOD); | |
447 | control_context.debobs_0 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(0)); | |
448 | control_context.debobs_1 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(1)); | |
449 | control_context.debobs_2 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(2)); | |
450 | control_context.debobs_3 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(3)); | |
451 | control_context.debobs_4 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(4)); | |
452 | control_context.debobs_5 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(5)); | |
453 | control_context.debobs_6 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(6)); | |
454 | control_context.debobs_7 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(7)); | |
455 | control_context.debobs_8 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(8)); | |
456 | control_context.prog_io0 = omap_ctrl_readl(OMAP343X_CONTROL_PROG_IO0); | |
457 | control_context.prog_io1 = omap_ctrl_readl(OMAP343X_CONTROL_PROG_IO1); | |
458 | control_context.dss_dpll_spreading = | |
459 | omap_ctrl_readl(OMAP343X_CONTROL_DSS_DPLL_SPREADING); | |
460 | control_context.core_dpll_spreading = | |
461 | omap_ctrl_readl(OMAP343X_CONTROL_CORE_DPLL_SPREADING); | |
462 | control_context.per_dpll_spreading = | |
463 | omap_ctrl_readl(OMAP343X_CONTROL_PER_DPLL_SPREADING); | |
464 | control_context.usbhost_dpll_spreading = | |
465 | omap_ctrl_readl(OMAP343X_CONTROL_USBHOST_DPLL_SPREADING); | |
466 | control_context.pbias_lite = | |
467 | omap_ctrl_readl(OMAP343X_CONTROL_PBIAS_LITE); | |
468 | control_context.temp_sensor = | |
469 | omap_ctrl_readl(OMAP343X_CONTROL_TEMP_SENSOR); | |
470 | control_context.sramldo4 = omap_ctrl_readl(OMAP343X_CONTROL_SRAMLDO4); | |
471 | control_context.sramldo5 = omap_ctrl_readl(OMAP343X_CONTROL_SRAMLDO5); | |
472 | control_context.csi = omap_ctrl_readl(OMAP343X_CONTROL_CSI); | |
f5f9d132 PW |
473 | control_context.padconf_sys_nirq = |
474 | omap_ctrl_readl(OMAP343X_CONTROL_PADCONF_SYSNIRQ); | |
c96631e1 RN |
475 | return; |
476 | } | |
477 | ||
478 | void omap3_control_restore_context(void) | |
479 | { | |
480 | omap_ctrl_writel(control_context.sysconfig, OMAP2_CONTROL_SYSCONFIG); | |
481 | omap_ctrl_writel(control_context.devconf0, OMAP2_CONTROL_DEVCONF0); | |
482 | omap_ctrl_writel(control_context.mem_dftrw0, | |
483 | OMAP343X_CONTROL_MEM_DFTRW0); | |
484 | omap_ctrl_writel(control_context.mem_dftrw1, | |
485 | OMAP343X_CONTROL_MEM_DFTRW1); | |
486 | omap_ctrl_writel(control_context.msuspendmux_0, | |
487 | OMAP2_CONTROL_MSUSPENDMUX_0); | |
488 | omap_ctrl_writel(control_context.msuspendmux_1, | |
489 | OMAP2_CONTROL_MSUSPENDMUX_1); | |
490 | omap_ctrl_writel(control_context.msuspendmux_2, | |
491 | OMAP2_CONTROL_MSUSPENDMUX_2); | |
492 | omap_ctrl_writel(control_context.msuspendmux_3, | |
493 | OMAP2_CONTROL_MSUSPENDMUX_3); | |
494 | omap_ctrl_writel(control_context.msuspendmux_4, | |
495 | OMAP2_CONTROL_MSUSPENDMUX_4); | |
496 | omap_ctrl_writel(control_context.msuspendmux_5, | |
497 | OMAP2_CONTROL_MSUSPENDMUX_5); | |
498 | omap_ctrl_writel(control_context.sec_ctrl, OMAP2_CONTROL_SEC_CTRL); | |
499 | omap_ctrl_writel(control_context.devconf1, OMAP343X_CONTROL_DEVCONF1); | |
500 | omap_ctrl_writel(control_context.csirxfe, OMAP343X_CONTROL_CSIRXFE); | |
501 | omap_ctrl_writel(control_context.iva2_bootaddr, | |
502 | OMAP343X_CONTROL_IVA2_BOOTADDR); | |
503 | omap_ctrl_writel(control_context.iva2_bootmod, | |
504 | OMAP343X_CONTROL_IVA2_BOOTMOD); | |
505 | omap_ctrl_writel(control_context.debobs_0, OMAP343X_CONTROL_DEBOBS(0)); | |
506 | omap_ctrl_writel(control_context.debobs_1, OMAP343X_CONTROL_DEBOBS(1)); | |
507 | omap_ctrl_writel(control_context.debobs_2, OMAP343X_CONTROL_DEBOBS(2)); | |
508 | omap_ctrl_writel(control_context.debobs_3, OMAP343X_CONTROL_DEBOBS(3)); | |
509 | omap_ctrl_writel(control_context.debobs_4, OMAP343X_CONTROL_DEBOBS(4)); | |
510 | omap_ctrl_writel(control_context.debobs_5, OMAP343X_CONTROL_DEBOBS(5)); | |
511 | omap_ctrl_writel(control_context.debobs_6, OMAP343X_CONTROL_DEBOBS(6)); | |
512 | omap_ctrl_writel(control_context.debobs_7, OMAP343X_CONTROL_DEBOBS(7)); | |
513 | omap_ctrl_writel(control_context.debobs_8, OMAP343X_CONTROL_DEBOBS(8)); | |
514 | omap_ctrl_writel(control_context.prog_io0, OMAP343X_CONTROL_PROG_IO0); | |
515 | omap_ctrl_writel(control_context.prog_io1, OMAP343X_CONTROL_PROG_IO1); | |
516 | omap_ctrl_writel(control_context.dss_dpll_spreading, | |
517 | OMAP343X_CONTROL_DSS_DPLL_SPREADING); | |
518 | omap_ctrl_writel(control_context.core_dpll_spreading, | |
519 | OMAP343X_CONTROL_CORE_DPLL_SPREADING); | |
520 | omap_ctrl_writel(control_context.per_dpll_spreading, | |
521 | OMAP343X_CONTROL_PER_DPLL_SPREADING); | |
522 | omap_ctrl_writel(control_context.usbhost_dpll_spreading, | |
523 | OMAP343X_CONTROL_USBHOST_DPLL_SPREADING); | |
524 | omap_ctrl_writel(control_context.pbias_lite, | |
525 | OMAP343X_CONTROL_PBIAS_LITE); | |
526 | omap_ctrl_writel(control_context.temp_sensor, | |
527 | OMAP343X_CONTROL_TEMP_SENSOR); | |
528 | omap_ctrl_writel(control_context.sramldo4, OMAP343X_CONTROL_SRAMLDO4); | |
529 | omap_ctrl_writel(control_context.sramldo5, OMAP343X_CONTROL_SRAMLDO5); | |
530 | omap_ctrl_writel(control_context.csi, OMAP343X_CONTROL_CSI); | |
f5f9d132 PW |
531 | omap_ctrl_writel(control_context.padconf_sys_nirq, |
532 | OMAP343X_CONTROL_PADCONF_SYSNIRQ); | |
c96631e1 RN |
533 | return; |
534 | } | |
458e999e NM |
535 | |
536 | void omap3630_ctrl_disable_rta(void) | |
537 | { | |
538 | if (!cpu_is_omap3630()) | |
539 | return; | |
540 | omap_ctrl_writel(OMAP36XX_RTA_DISABLE, OMAP36XX_CONTROL_MEM_RTA_CTRL); | |
541 | } | |
542 | ||
596efe47 PW |
543 | /** |
544 | * omap3_ctrl_save_padconf - save padconf registers to scratchpad RAM | |
545 | * | |
546 | * Tell the SCM to start saving the padconf registers, then wait for | |
547 | * the process to complete. Returns 0 unconditionally, although it | |
548 | * should also eventually be able to return -ETIMEDOUT, if the save | |
549 | * does not complete. | |
550 | * | |
551 | * XXX This function is missing a timeout. What should it be? | |
552 | */ | |
553 | int omap3_ctrl_save_padconf(void) | |
554 | { | |
555 | u32 cpo; | |
556 | ||
557 | /* Save the padconf registers */ | |
558 | cpo = omap_ctrl_readl(OMAP343X_CONTROL_PADCONF_OFF); | |
559 | cpo |= START_PADCONF_SAVE; | |
560 | omap_ctrl_writel(cpo, OMAP343X_CONTROL_PADCONF_OFF); | |
561 | ||
562 | /* wait for the save to complete */ | |
563 | while (!(omap_ctrl_readl(OMAP343X_CONTROL_GENERAL_PURPOSE_STATUS) | |
564 | & PADCONF_SAVE_DONE)) | |
565 | udelay(1); | |
566 | ||
567 | return 0; | |
568 | } | |
569 | ||
c96631e1 | 570 | #endif /* CONFIG_ARCH_OMAP3 && CONFIG_PM */ |