projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 69d88a00 | 1 | /* |
| 4814ced5 | 2 | * arch/arm/mach-omap2/control.h |
| 69d88a00 | 3 | * |
| 44169075 | 4 | * OMAP2/3/4 System Control Module definitions |
| 69d88a00 | 5 | * |
| 4814ced5 PW |
6 | * Copyright (C) 2007-2010 Texas Instruments, Inc. |
| 7 | * Copyright (C) 2007-2008, 2010 Nokia Corporation | |
| 69d88a00 PW |
8 | * |
| 9 | * Written by Paul Walmsley | |
| 10 | * | |
| 11 | * This program is free software; you can redistribute it and/or modify | |
| 12 | * it under the terms of the GNU General Public License as published by | |
| 13 | * the Free Software Foundation. | |
| 14 | */ | |
| 15 | ||
| 4814ced5 PW |
16 | #ifndef __ARCH_ARM_MACH_OMAP2_CONTROL_H |
| 17 | #define __ARCH_ARM_MACH_OMAP2_CONTROL_H | |
| 646e3ed1 | 18 | |
| 802edcb7 SS |
19 | #include <mach/ctrl_module_core_44xx.h> |
| 20 | #include <mach/ctrl_module_wkup_44xx.h> | |
| 21 | #include <mach/ctrl_module_pad_core_44xx.h> | |
| 22 | #include <mach/ctrl_module_pad_wkup_44xx.h> | |
| 69d88a00 | 23 | |
| 646e3ed1 | 24 | #ifndef __ASSEMBLY__ |
| 69d88a00 | 25 | #define OMAP242X_CTRL_REGADDR(reg) \ |
| 233fd64e | 26 | OMAP2_L4_IO_ADDRESS(OMAP242X_CTRL_BASE + (reg)) |
| 69d88a00 | 27 | #define OMAP243X_CTRL_REGADDR(reg) \ |
| 233fd64e | 28 | OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE + (reg)) |
| 69d88a00 | 29 | #define OMAP343X_CTRL_REGADDR(reg) \ |
| 233fd64e | 30 | OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE + (reg)) |
| 646e3ed1 | 31 | #else |
| 233fd64e SS |
32 | #define OMAP242X_CTRL_REGADDR(reg) \ |
| 33 | OMAP2_L4_IO_ADDRESS(OMAP242X_CTRL_BASE + (reg)) | |
| 34 | #define OMAP243X_CTRL_REGADDR(reg) \ | |
| 35 | OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE + (reg)) | |
| 36 | #define OMAP343X_CTRL_REGADDR(reg) \ | |
| 37 | OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE + (reg)) | |
| 646e3ed1 | 38 | #endif /* __ASSEMBLY__ */ |
| 69d88a00 PW |
39 | |
| 40 | /* | |
| 41 | * As elsewhere, the "OMAP2_" prefix indicates that the macro is valid for | |
| 42 | * OMAP24XX and OMAP34XX. | |
| 43 | */ | |
| 44 | ||
| 45 | /* Control submodule offsets */ | |
| 46 | ||
| 47 | #define OMAP2_CONTROL_INTERFACE 0x000 | |
| 48 | #define OMAP2_CONTROL_PADCONFS 0x030 | |
| 49 | #define OMAP2_CONTROL_GENERAL 0x270 | |
| 50 | #define OMAP343X_CONTROL_MEM_WKUP 0x600 | |
| 51 | #define OMAP343X_CONTROL_PADCONFS_WKUP 0xa00 | |
| 52 | #define OMAP343X_CONTROL_GENERAL_WKUP 0xa60 | |
| 53 | ||
| a920360f HP |
54 | /* TI81XX spefic control submodules */ |
| 55 | #define TI81XX_CONTROL_DEVCONF 0x600 | |
| 01001712 | 56 | |
| 69d88a00 PW |
57 | /* Control register offsets - read/write with omap_ctrl_{read,write}{bwl}() */ |
| 58 | ||
| 59 | #define OMAP2_CONTROL_SYSCONFIG (OMAP2_CONTROL_INTERFACE + 0x10) | |
| 60 | ||
| 61 | /* CONTROL_GENERAL register offsets common to OMAP2 & 3 */ | |
| 62 | #define OMAP2_CONTROL_DEVCONF0 (OMAP2_CONTROL_GENERAL + 0x0004) | |
| 63 | #define OMAP2_CONTROL_MSUSPENDMUX_0 (OMAP2_CONTROL_GENERAL + 0x0020) | |
| 64 | #define OMAP2_CONTROL_MSUSPENDMUX_1 (OMAP2_CONTROL_GENERAL + 0x0024) | |
| 65 | #define OMAP2_CONTROL_MSUSPENDMUX_2 (OMAP2_CONTROL_GENERAL + 0x0028) | |
| 66 | #define OMAP2_CONTROL_MSUSPENDMUX_3 (OMAP2_CONTROL_GENERAL + 0x002c) | |
| 67 | #define OMAP2_CONTROL_MSUSPENDMUX_4 (OMAP2_CONTROL_GENERAL + 0x0030) | |
| 68 | #define OMAP2_CONTROL_MSUSPENDMUX_5 (OMAP2_CONTROL_GENERAL + 0x0034) | |
| 69 | #define OMAP2_CONTROL_SEC_CTRL (OMAP2_CONTROL_GENERAL + 0x0040) | |
| 70 | #define OMAP2_CONTROL_RPUB_KEY_H_0 (OMAP2_CONTROL_GENERAL + 0x0090) | |
| 71 | #define OMAP2_CONTROL_RPUB_KEY_H_1 (OMAP2_CONTROL_GENERAL + 0x0094) | |
| 72 | #define OMAP2_CONTROL_RPUB_KEY_H_2 (OMAP2_CONTROL_GENERAL + 0x0098) | |
| 73 | #define OMAP2_CONTROL_RPUB_KEY_H_3 (OMAP2_CONTROL_GENERAL + 0x009c) | |
| 74 | ||
| 75 | /* 242x-only CONTROL_GENERAL register offsets */ | |
| 76 | #define OMAP242X_CONTROL_DEVCONF OMAP2_CONTROL_DEVCONF0 /* match TRM */ | |
| 77 | #define OMAP242X_CONTROL_OCM_RAM_PERM (OMAP2_CONTROL_GENERAL + 0x0068) | |
| 78 | ||
| 79 | /* 243x-only CONTROL_GENERAL register offsets */ | |
| 80 | /* CONTROL_IVA2_BOOT{ADDR,MOD} are at the same place on 343x - noted below */ | |
| 81 | #define OMAP243X_CONTROL_DEVCONF1 (OMAP2_CONTROL_GENERAL + 0x0078) | |
| 82 | #define OMAP243X_CONTROL_CSIRXFE (OMAP2_CONTROL_GENERAL + 0x007c) | |
| 83 | #define OMAP243X_CONTROL_IVA2_BOOTADDR (OMAP2_CONTROL_GENERAL + 0x0190) | |
| 84 | #define OMAP243X_CONTROL_IVA2_BOOTMOD (OMAP2_CONTROL_GENERAL + 0x0194) | |
| 85 | #define OMAP243X_CONTROL_IVA2_GEMCFG (OMAP2_CONTROL_GENERAL + 0x0198) | |
| 90c62bf0 | 86 | #define OMAP243X_CONTROL_PBIAS_LITE (OMAP2_CONTROL_GENERAL + 0x0230) |
| 69d88a00 PW |
87 | |
| 88 | /* 24xx-only CONTROL_GENERAL register offsets */ | |
| 89 | #define OMAP24XX_CONTROL_DEBOBS (OMAP2_CONTROL_GENERAL + 0x0000) | |
| 90 | #define OMAP24XX_CONTROL_EMU_SUPPORT (OMAP2_CONTROL_GENERAL + 0x0008) | |
| 91 | #define OMAP24XX_CONTROL_SEC_TEST (OMAP2_CONTROL_GENERAL + 0x0044) | |
| 92 | #define OMAP24XX_CONTROL_PSA_CTRL (OMAP2_CONTROL_GENERAL + 0x0048) | |
| 93 | #define OMAP24XX_CONTROL_PSA_CMD (OMAP2_CONTROL_GENERAL + 0x004c) | |
| 94 | #define OMAP24XX_CONTROL_PSA_VALUE (OMAP2_CONTROL_GENERAL + 0x0050) | |
| 95 | #define OMAP24XX_CONTROL_SEC_EMU (OMAP2_CONTROL_GENERAL + 0x0060) | |
| 96 | #define OMAP24XX_CONTROL_SEC_TAP (OMAP2_CONTROL_GENERAL + 0x0064) | |
| 97 | #define OMAP24XX_CONTROL_OCM_PUB_RAM_ADD (OMAP2_CONTROL_GENERAL + 0x006c) | |
| 98 | #define OMAP24XX_CONTROL_EXT_SEC_RAM_START_ADD (OMAP2_CONTROL_GENERAL + 0x0070) | |
| 1df5a8d0 | 99 | #define OMAP24XX_CONTROL_EXT_SEC_RAM_STOP_ADD (OMAP2_CONTROL_GENERAL + 0x0074) |
| 69d88a00 PW |
100 | #define OMAP24XX_CONTROL_SEC_STATUS (OMAP2_CONTROL_GENERAL + 0x0080) |
| 101 | #define OMAP24XX_CONTROL_SEC_ERR_STATUS (OMAP2_CONTROL_GENERAL + 0x0084) | |
| 102 | #define OMAP24XX_CONTROL_STATUS (OMAP2_CONTROL_GENERAL + 0x0088) | |
| 103 | #define OMAP24XX_CONTROL_GENERAL_PURPOSE_STATUS (OMAP2_CONTROL_GENERAL + 0x008c) | |
| 104 | #define OMAP24XX_CONTROL_RAND_KEY_0 (OMAP2_CONTROL_GENERAL + 0x00a0) | |
| 105 | #define OMAP24XX_CONTROL_RAND_KEY_1 (OMAP2_CONTROL_GENERAL + 0x00a4) | |
| 106 | #define OMAP24XX_CONTROL_RAND_KEY_2 (OMAP2_CONTROL_GENERAL + 0x00a8) | |
| 107 | #define OMAP24XX_CONTROL_RAND_KEY_3 (OMAP2_CONTROL_GENERAL + 0x00ac) | |
| 108 | #define OMAP24XX_CONTROL_CUST_KEY_0 (OMAP2_CONTROL_GENERAL + 0x00b0) | |
| 109 | #define OMAP24XX_CONTROL_CUST_KEY_1 (OMAP2_CONTROL_GENERAL + 0x00b4) | |
| 110 | #define OMAP24XX_CONTROL_TEST_KEY_0 (OMAP2_CONTROL_GENERAL + 0x00c0) | |
| 111 | #define OMAP24XX_CONTROL_TEST_KEY_1 (OMAP2_CONTROL_GENERAL + 0x00c4) | |
| 112 | #define OMAP24XX_CONTROL_TEST_KEY_2 (OMAP2_CONTROL_GENERAL + 0x00c8) | |
| 113 | #define OMAP24XX_CONTROL_TEST_KEY_3 (OMAP2_CONTROL_GENERAL + 0x00cc) | |
| 114 | #define OMAP24XX_CONTROL_TEST_KEY_4 (OMAP2_CONTROL_GENERAL + 0x00d0) | |
| 115 | #define OMAP24XX_CONTROL_TEST_KEY_5 (OMAP2_CONTROL_GENERAL + 0x00d4) | |
| 116 | #define OMAP24XX_CONTROL_TEST_KEY_6 (OMAP2_CONTROL_GENERAL + 0x00d8) | |
| 117 | #define OMAP24XX_CONTROL_TEST_KEY_7 (OMAP2_CONTROL_GENERAL + 0x00dc) | |
| 118 | #define OMAP24XX_CONTROL_TEST_KEY_8 (OMAP2_CONTROL_GENERAL + 0x00e0) | |
| 119 | #define OMAP24XX_CONTROL_TEST_KEY_9 (OMAP2_CONTROL_GENERAL + 0x00e4) | |
| 120 | ||
| c171a258 RN |
121 | #define OMAP343X_CONTROL_PADCONF_SYSNIRQ (OMAP2_CONTROL_INTERFACE + 0x01b0) |
| 122 | ||
| 69d88a00 PW |
123 | /* 34xx-only CONTROL_GENERAL register offsets */ |
| 124 | #define OMAP343X_CONTROL_PADCONF_OFF (OMAP2_CONTROL_GENERAL + 0x0000) | |
| 125 | #define OMAP343X_CONTROL_MEM_DFTRW0 (OMAP2_CONTROL_GENERAL + 0x0008) | |
| 126 | #define OMAP343X_CONTROL_MEM_DFTRW1 (OMAP2_CONTROL_GENERAL + 0x000c) | |
| 127 | #define OMAP343X_CONTROL_DEVCONF1 (OMAP2_CONTROL_GENERAL + 0x0068) | |
| 128 | #define OMAP343X_CONTROL_CSIRXFE (OMAP2_CONTROL_GENERAL + 0x006c) | |
| 129 | #define OMAP343X_CONTROL_SEC_STATUS (OMAP2_CONTROL_GENERAL + 0x0070) | |
| 130 | #define OMAP343X_CONTROL_SEC_ERR_STATUS (OMAP2_CONTROL_GENERAL + 0x0074) | |
| 131 | #define OMAP343X_CONTROL_SEC_ERR_STATUS_DEBUG (OMAP2_CONTROL_GENERAL + 0x0078) | |
| 132 | #define OMAP343X_CONTROL_STATUS (OMAP2_CONTROL_GENERAL + 0x0080) | |
| 133 | #define OMAP343X_CONTROL_GENERAL_PURPOSE_STATUS (OMAP2_CONTROL_GENERAL + 0x0084) | |
| 134 | #define OMAP343X_CONTROL_RPUB_KEY_H_4 (OMAP2_CONTROL_GENERAL + 0x00a0) | |
| 135 | #define OMAP343X_CONTROL_RAND_KEY_0 (OMAP2_CONTROL_GENERAL + 0x00a8) | |
| 136 | #define OMAP343X_CONTROL_RAND_KEY_1 (OMAP2_CONTROL_GENERAL + 0x00ac) | |
| 137 | #define OMAP343X_CONTROL_RAND_KEY_2 (OMAP2_CONTROL_GENERAL + 0x00b0) | |
| 138 | #define OMAP343X_CONTROL_RAND_KEY_3 (OMAP2_CONTROL_GENERAL + 0x00b4) | |
| 139 | #define OMAP343X_CONTROL_TEST_KEY_0 (OMAP2_CONTROL_GENERAL + 0x00c8) | |
| 140 | #define OMAP343X_CONTROL_TEST_KEY_1 (OMAP2_CONTROL_GENERAL + 0x00cc) | |
| 141 | #define OMAP343X_CONTROL_TEST_KEY_2 (OMAP2_CONTROL_GENERAL + 0x00d0) | |
| 142 | #define OMAP343X_CONTROL_TEST_KEY_3 (OMAP2_CONTROL_GENERAL + 0x00d4) | |
| 143 | #define OMAP343X_CONTROL_TEST_KEY_4 (OMAP2_CONTROL_GENERAL + 0x00d8) | |
| 144 | #define OMAP343X_CONTROL_TEST_KEY_5 (OMAP2_CONTROL_GENERAL + 0x00dc) | |
| 145 | #define OMAP343X_CONTROL_TEST_KEY_6 (OMAP2_CONTROL_GENERAL + 0x00e0) | |
| 146 | #define OMAP343X_CONTROL_TEST_KEY_7 (OMAP2_CONTROL_GENERAL + 0x00e4) | |
| 147 | #define OMAP343X_CONTROL_TEST_KEY_8 (OMAP2_CONTROL_GENERAL + 0x00e8) | |
| 148 | #define OMAP343X_CONTROL_TEST_KEY_9 (OMAP2_CONTROL_GENERAL + 0x00ec) | |
| 149 | #define OMAP343X_CONTROL_TEST_KEY_10 (OMAP2_CONTROL_GENERAL + 0x00f0) | |
| 150 | #define OMAP343X_CONTROL_TEST_KEY_11 (OMAP2_CONTROL_GENERAL + 0x00f4) | |
| 151 | #define OMAP343X_CONTROL_TEST_KEY_12 (OMAP2_CONTROL_GENERAL + 0x00f8) | |
| 152 | #define OMAP343X_CONTROL_TEST_KEY_13 (OMAP2_CONTROL_GENERAL + 0x00fc) | |
| 2f34ce81 TG |
153 | #define OMAP343X_CONTROL_FUSE_OPP1_VDD1 (OMAP2_CONTROL_GENERAL + 0x0110) |
| 154 | #define OMAP343X_CONTROL_FUSE_OPP2_VDD1 (OMAP2_CONTROL_GENERAL + 0x0114) | |
| 155 | #define OMAP343X_CONTROL_FUSE_OPP3_VDD1 (OMAP2_CONTROL_GENERAL + 0x0118) | |
| 156 | #define OMAP343X_CONTROL_FUSE_OPP4_VDD1 (OMAP2_CONTROL_GENERAL + 0x011c) | |
| 157 | #define OMAP343X_CONTROL_FUSE_OPP5_VDD1 (OMAP2_CONTROL_GENERAL + 0x0120) | |
| 158 | #define OMAP343X_CONTROL_FUSE_OPP1_VDD2 (OMAP2_CONTROL_GENERAL + 0x0124) | |
| 159 | #define OMAP343X_CONTROL_FUSE_OPP2_VDD2 (OMAP2_CONTROL_GENERAL + 0x0128) | |
| 160 | #define OMAP343X_CONTROL_FUSE_OPP3_VDD2 (OMAP2_CONTROL_GENERAL + 0x012c) | |
| 161 | #define OMAP343X_CONTROL_FUSE_SR (OMAP2_CONTROL_GENERAL + 0x0130) | |
| 69d88a00 PW |
162 | #define OMAP343X_CONTROL_IVA2_BOOTADDR (OMAP2_CONTROL_GENERAL + 0x0190) |
| 163 | #define OMAP343X_CONTROL_IVA2_BOOTMOD (OMAP2_CONTROL_GENERAL + 0x0194) | |
| c96631e1 | 164 | #define OMAP343X_CONTROL_DEBOBS(i) (OMAP2_CONTROL_GENERAL + 0x01B0 \ |
| 83969bfa | 165 | + ((i) >> 1) * 4 + (!((i) & 1)) * 2) |
| c96631e1 RN |
166 | #define OMAP343X_CONTROL_PROG_IO0 (OMAP2_CONTROL_GENERAL + 0x01D4) |
| 167 | #define OMAP343X_CONTROL_PROG_IO1 (OMAP2_CONTROL_GENERAL + 0x01D8) | |
| 168 | #define OMAP343X_CONTROL_DSS_DPLL_SPREADING (OMAP2_CONTROL_GENERAL + 0x01E0) | |
| 169 | #define OMAP343X_CONTROL_CORE_DPLL_SPREADING (OMAP2_CONTROL_GENERAL + 0x01E4) | |
| 170 | #define OMAP343X_CONTROL_PER_DPLL_SPREADING (OMAP2_CONTROL_GENERAL + 0x01E8) | |
| 171 | #define OMAP343X_CONTROL_USBHOST_DPLL_SPREADING (OMAP2_CONTROL_GENERAL + 0x01EC) | |
| 172 | #define OMAP343X_CONTROL_PBIAS_LITE (OMAP2_CONTROL_GENERAL + 0x02B0) | |
| 173 | #define OMAP343X_CONTROL_TEMP_SENSOR (OMAP2_CONTROL_GENERAL + 0x02B4) | |
| 174 | #define OMAP343X_CONTROL_SRAMLDO4 (OMAP2_CONTROL_GENERAL + 0x02B8) | |
| 175 | #define OMAP343X_CONTROL_SRAMLDO5 (OMAP2_CONTROL_GENERAL + 0x02C0) | |
| 176 | #define OMAP343X_CONTROL_CSI (OMAP2_CONTROL_GENERAL + 0x02C4) | |
| 177 | ||
| 2f34ce81 TG |
178 | /* OMAP3630 only CONTROL_GENERAL register offsets */ |
| 179 | #define OMAP3630_CONTROL_FUSE_OPP1G_VDD1 (OMAP2_CONTROL_GENERAL + 0x0110) | |
| 180 | #define OMAP3630_CONTROL_FUSE_OPP50_VDD1 (OMAP2_CONTROL_GENERAL + 0x0114) | |
| 181 | #define OMAP3630_CONTROL_FUSE_OPP100_VDD1 (OMAP2_CONTROL_GENERAL + 0x0118) | |
| 182 | #define OMAP3630_CONTROL_FUSE_OPP120_VDD1 (OMAP2_CONTROL_GENERAL + 0x0120) | |
| 183 | #define OMAP3630_CONTROL_FUSE_OPP50_VDD2 (OMAP2_CONTROL_GENERAL + 0x0128) | |
| 184 | #define OMAP3630_CONTROL_FUSE_OPP100_VDD2 (OMAP2_CONTROL_GENERAL + 0x012C) | |
| 185 | ||
| bd38107b TG |
186 | /* OMAP44xx control efuse offsets */ |
| 187 | #define OMAP44XX_CONTROL_FUSE_IVA_OPP50 0x22C | |
| 188 | #define OMAP44XX_CONTROL_FUSE_IVA_OPP100 0x22F | |
| 189 | #define OMAP44XX_CONTROL_FUSE_IVA_OPPTURBO 0x232 | |
| 190 | #define OMAP44XX_CONTROL_FUSE_IVA_OPPNITRO 0x235 | |
| 191 | #define OMAP44XX_CONTROL_FUSE_MPU_OPP50 0x240 | |
| 192 | #define OMAP44XX_CONTROL_FUSE_MPU_OPP100 0x243 | |
| 193 | #define OMAP44XX_CONTROL_FUSE_MPU_OPPTURBO 0x246 | |
| 194 | #define OMAP44XX_CONTROL_FUSE_MPU_OPPNITRO 0x249 | |
| 195 | #define OMAP44XX_CONTROL_FUSE_CORE_OPP50 0x254 | |
| 196 | #define OMAP44XX_CONTROL_FUSE_CORE_OPP100 0x257 | |
| 197 | ||
| 05842a32 RL |
198 | /* AM35XX only CONTROL_GENERAL register offsets */ |
| 199 | #define AM35XX_CONTROL_MSUSPENDMUX_6 (OMAP2_CONTROL_GENERAL + 0x0038) | |
| 200 | #define AM35XX_CONTROL_DEVCONF2 (OMAP2_CONTROL_GENERAL + 0x0310) | |
| 201 | #define AM35XX_CONTROL_DEVCONF3 (OMAP2_CONTROL_GENERAL + 0x0314) | |
| 202 | #define AM35XX_CONTROL_CBA_PRIORITY (OMAP2_CONTROL_GENERAL + 0x0320) | |
| 203 | #define AM35XX_CONTROL_LVL_INTR_CLEAR (OMAP2_CONTROL_GENERAL + 0x0324) | |
| 204 | #define AM35XX_CONTROL_IP_SW_RESET (OMAP2_CONTROL_GENERAL + 0x0328) | |
| 205 | #define AM35XX_CONTROL_IPSS_CLK_CTRL (OMAP2_CONTROL_GENERAL + 0x032C) | |
| c96631e1 RN |
206 | |
| 207 | /* 34xx PADCONF register offsets */ | |
| 208 | #define OMAP343X_PADCONF_ETK(i) (OMAP2_CONTROL_PADCONFS + 0x5a8 + \ | |
| 209 | (i)*2) | |
| 210 | #define OMAP343X_PADCONF_ETK_CLK OMAP343X_PADCONF_ETK(0) | |
| 211 | #define OMAP343X_PADCONF_ETK_CTL OMAP343X_PADCONF_ETK(1) | |
| 212 | #define OMAP343X_PADCONF_ETK_D0 OMAP343X_PADCONF_ETK(2) | |
| 213 | #define OMAP343X_PADCONF_ETK_D1 OMAP343X_PADCONF_ETK(3) | |
| 214 | #define OMAP343X_PADCONF_ETK_D2 OMAP343X_PADCONF_ETK(4) | |
| 215 | #define OMAP343X_PADCONF_ETK_D3 OMAP343X_PADCONF_ETK(5) | |
| 216 | #define OMAP343X_PADCONF_ETK_D4 OMAP343X_PADCONF_ETK(6) | |
| 217 | #define OMAP343X_PADCONF_ETK_D5 OMAP343X_PADCONF_ETK(7) | |
| 218 | #define OMAP343X_PADCONF_ETK_D6 OMAP343X_PADCONF_ETK(8) | |
| 219 | #define OMAP343X_PADCONF_ETK_D7 OMAP343X_PADCONF_ETK(9) | |
| 220 | #define OMAP343X_PADCONF_ETK_D8 OMAP343X_PADCONF_ETK(10) | |
| 221 | #define OMAP343X_PADCONF_ETK_D9 OMAP343X_PADCONF_ETK(11) | |
| 222 | #define OMAP343X_PADCONF_ETK_D10 OMAP343X_PADCONF_ETK(12) | |
| 223 | #define OMAP343X_PADCONF_ETK_D11 OMAP343X_PADCONF_ETK(13) | |
| 224 | #define OMAP343X_PADCONF_ETK_D12 OMAP343X_PADCONF_ETK(14) | |
| 225 | #define OMAP343X_PADCONF_ETK_D13 OMAP343X_PADCONF_ETK(15) | |
| 226 | #define OMAP343X_PADCONF_ETK_D14 OMAP343X_PADCONF_ETK(16) | |
| 227 | #define OMAP343X_PADCONF_ETK_D15 OMAP343X_PADCONF_ETK(17) | |
| 228 | ||
| 229 | /* 34xx GENERAL_WKUP regist offsets */ | |
| 230 | #define OMAP343X_CONTROL_WKUP_DEBOBSMUX(i) (OMAP343X_CONTROL_GENERAL_WKUP + \ | |
| 231 | 0x008 + (i)) | |
| 232 | #define OMAP343X_CONTROL_WKUP_DEBOBS0 (OMAP343X_CONTROL_GENERAL_WKUP + 0x008) | |
| 233 | #define OMAP343X_CONTROL_WKUP_DEBOBS1 (OMAP343X_CONTROL_GENERAL_WKUP + 0x00C) | |
| 234 | #define OMAP343X_CONTROL_WKUP_DEBOBS2 (OMAP343X_CONTROL_GENERAL_WKUP + 0x010) | |
| 235 | #define OMAP343X_CONTROL_WKUP_DEBOBS3 (OMAP343X_CONTROL_GENERAL_WKUP + 0x014) | |
| 236 | #define OMAP343X_CONTROL_WKUP_DEBOBS4 (OMAP343X_CONTROL_GENERAL_WKUP + 0x018) | |
| 69d88a00 | 237 | |
| 70f23fd6 | 238 | /* 36xx-only RTA - Retention till Access control registers and bits */ |
| 458e999e NM |
239 | #define OMAP36XX_CONTROL_MEM_RTA_CTRL 0x40C |
| 240 | #define OMAP36XX_RTA_DISABLE 0x0 | |
| 241 | ||
| 8111b221 KH |
242 | /* 34xx D2D idle-related pins, handled by PM core */ |
| 243 | #define OMAP3_PADCONF_SAD2D_MSTANDBY 0x250 | |
| 244 | #define OMAP3_PADCONF_SAD2D_IDLEACK 0x254 | |
| 245 | ||
| a920360f HP |
246 | /* TI81XX CONTROL_DEVCONF register offsets */ |
| 247 | #define TI81XX_CONTROL_DEVICE_ID (TI81XX_CONTROL_DEVCONF + 0x000) | |
| 01001712 | 248 | |
| 69d88a00 PW |
249 | /* |
| 250 | * REVISIT: This list of registers is not comprehensive - there are more | |
| 251 | * that should be added. | |
| 252 | */ | |
| 253 | ||
| 254 | /* | |
| 255 | * Control module register bit defines - these should eventually go into | |
| 256 | * their own regbits file. Some of these will be complicated, depending | |
| 257 | * on the device type (general-purpose, emulator, test, secure, bad, other) | |
| 258 | * and the security mode (secure, non-secure, don't care) | |
| 259 | */ | |
| 260 | /* CONTROL_DEVCONF0 bits */ | |
| 90c62bf0 | 261 | #define OMAP2_MMCSDIO1ADPCLKISEL (1 << 24) /* MMC1 loop back clock */ |
| 69d88a00 PW |
262 | #define OMAP24XX_USBSTANDBYCTRL (1 << 15) |
| 263 | #define OMAP2_MCBSP2_CLKS_MASK (1 << 6) | |
| cf4c87ab PW |
264 | #define OMAP2_MCBSP1_FSR_MASK (1 << 4) |
| 265 | #define OMAP2_MCBSP1_CLKR_MASK (1 << 3) | |
| 69d88a00 PW |
266 | #define OMAP2_MCBSP1_CLKS_MASK (1 << 2) |
| 267 | ||
| 268 | /* CONTROL_DEVCONF1 bits */ | |
| 90c62bf0 TL |
269 | #define OMAP243X_MMC1_ACTIVE_OVERWRITE (1 << 31) |
| 270 | #define OMAP2_MMCSDIO2ADPCLKISEL (1 << 6) /* MMC2 loop back clock */ | |
| 69d88a00 PW |
271 | #define OMAP2_MCBSP5_CLKS_MASK (1 << 4) /* > 242x */ |
| 272 | #define OMAP2_MCBSP4_CLKS_MASK (1 << 2) /* > 242x */ | |
| 273 | #define OMAP2_MCBSP3_CLKS_MASK (1 << 0) /* > 242x */ | |
| 274 | ||
| 275 | /* CONTROL_STATUS bits */ | |
| 276 | #define OMAP2_DEVICETYPE_MASK (0x7 << 8) | |
| 277 | #define OMAP2_SYSBOOT_5_MASK (1 << 5) | |
| 278 | #define OMAP2_SYSBOOT_4_MASK (1 << 4) | |
| 279 | #define OMAP2_SYSBOOT_3_MASK (1 << 3) | |
| 280 | #define OMAP2_SYSBOOT_2_MASK (1 << 2) | |
| 281 | #define OMAP2_SYSBOOT_1_MASK (1 << 1) | |
| 282 | #define OMAP2_SYSBOOT_0_MASK (1 << 0) | |
| 283 | ||
| 90c62bf0 TL |
284 | /* CONTROL_PBIAS_LITE bits */ |
| 285 | #define OMAP343X_PBIASLITESUPPLY_HIGH1 (1 << 15) | |
| 286 | #define OMAP343X_PBIASLITEVMODEERROR1 (1 << 11) | |
| 287 | #define OMAP343X_PBIASSPEEDCTRL1 (1 << 10) | |
| 288 | #define OMAP343X_PBIASLITEPWRDNZ1 (1 << 9) | |
| 289 | #define OMAP343X_PBIASLITEVMODE1 (1 << 8) | |
| 290 | #define OMAP343X_PBIASLITESUPPLY_HIGH0 (1 << 7) | |
| 291 | #define OMAP343X_PBIASLITEVMODEERROR0 (1 << 3) | |
| 292 | #define OMAP2_PBIASSPEEDCTRL0 (1 << 2) | |
| 293 | #define OMAP2_PBIASLITEPWRDNZ0 (1 << 1) | |
| 294 | #define OMAP2_PBIASLITEVMODE0 (1 << 0) | |
| 295 | ||
| 555d503f M |
296 | /* CONTROL_PROG_IO1 bits */ |
| 297 | #define OMAP3630_PRG_SDMMC1_SPEEDCTRL (1 << 20) | |
| 298 | ||
| 1155e426 KH |
299 | /* CONTROL_IVA2_BOOTMOD bits */ |
| 300 | #define OMAP3_IVA2_BOOTMOD_SHIFT 0 | |
| 301 | #define OMAP3_IVA2_BOOTMOD_MASK (0xf << 0) | |
| 302 | #define OMAP3_IVA2_BOOTMOD_IDLE (0x1 << 0) | |
| 303 | ||
| 5a1a5abd KH |
304 | /* CONTROL_PADCONF_X bits */ |
| 305 | #define OMAP3_PADCONF_WAKEUPEVENT0 (1 << 15) | |
| 306 | #define OMAP3_PADCONF_WAKEUPENABLE0 (1 << 14) | |
| 307 | ||
| 80140786 RN |
308 | #define OMAP343X_SCRATCHPAD_ROM (OMAP343X_CTRL_BASE + 0x860) |
| 309 | #define OMAP343X_SCRATCHPAD (OMAP343X_CTRL_BASE + 0x910) | |
| 310 | #define OMAP343X_SCRATCHPAD_ROM_OFFSET 0x19C | |
| fe360e1c JP |
311 | #define OMAP343X_SCRATCHPAD_REGADDR(reg) OMAP2_L4_IO_ADDRESS(\ |
| 312 | OMAP343X_SCRATCHPAD + reg) | |
| 80140786 | 313 | |
| 05842a32 RL |
314 | /* AM35XX_CONTROL_IPSS_CLK_CTRL bits */ |
| 315 | #define AM35XX_USBOTG_VBUSP_CLK_SHIFT 0 | |
| 316 | #define AM35XX_CPGMAC_VBUSP_CLK_SHIFT 1 | |
| 317 | #define AM35XX_VPFE_VBUSP_CLK_SHIFT 2 | |
| 318 | #define AM35XX_HECC_VBUSP_CLK_SHIFT 3 | |
| 319 | #define AM35XX_USBOTG_FCLK_SHIFT 8 | |
| 320 | #define AM35XX_CPGMAC_FCLK_SHIFT 9 | |
| 321 | #define AM35XX_VPFE_FCLK_SHIFT 10 | |
| 322 | ||
| 07dcbd07 VH |
323 | /*AM35XX CONTROL_LVL_INTR_CLEAR bits*/ |
| 324 | #define AM35XX_CPGMAC_C0_MISC_PULSE_CLR BIT(0) | |
| 325 | #define AM35XX_CPGMAC_C0_RX_PULSE_CLR BIT(1) | |
| 326 | #define AM35XX_CPGMAC_C0_RX_THRESH_CLR BIT(2) | |
| 327 | #define AM35XX_CPGMAC_C0_TX_PULSE_CLR BIT(3) | |
| 328 | #define AM35XX_USBOTGSS_INT_CLR BIT(4) | |
| 329 | #define AM35XX_VPFE_CCDC_VD0_INT_CLR BIT(5) | |
| 330 | #define AM35XX_VPFE_CCDC_VD1_INT_CLR BIT(6) | |
| 331 | #define AM35XX_VPFE_CCDC_VD2_INT_CLR BIT(7) | |
| 332 | ||
| 333 | /*AM35XX CONTROL_IP_SW_RESET bits*/ | |
| 334 | #define AM35XX_USBOTGSS_SW_RST BIT(0) | |
| 335 | #define AM35XX_CPGMACSS_SW_RST BIT(1) | |
| 336 | #define AM35XX_VPFE_VBUSP_SW_RST BIT(2) | |
| 337 | #define AM35XX_HECC_SW_RST BIT(3) | |
| 338 | #define AM35XX_VPFE_PCLK_SW_RST BIT(4) | |
| 339 | ||
| fb3cfb1f AM |
340 | /* |
| 341 | * CONTROL AM33XX STATUS register | |
| 342 | */ | |
| 343 | #define AM33XX_CONTROL_STATUS 0x040 | |
| 344 | ||
| 8384ce07 SP |
345 | /* |
| 346 | * CONTROL OMAP STATUS register to identify OMAP3 features | |
| 347 | */ | |
| 348 | #define OMAP3_CONTROL_OMAP_STATUS 0x044c | |
| 349 | ||
| 350 | #define OMAP3_SGX_SHIFT 13 | |
| 351 | #define OMAP3_SGX_MASK (3 << OMAP3_SGX_SHIFT) | |
| 352 | #define FEAT_SGX_FULL 0 | |
| 353 | #define FEAT_SGX_HALF 1 | |
| 354 | #define FEAT_SGX_NONE 2 | |
| 355 | ||
| 356 | #define OMAP3_IVA_SHIFT 12 | |
| 4e012e5f | 357 | #define OMAP3_IVA_MASK (1 << OMAP3_IVA_SHIFT) |
| 8384ce07 SP |
358 | #define FEAT_IVA 0 |
| 359 | #define FEAT_IVA_NONE 1 | |
| 360 | ||
| 361 | #define OMAP3_L2CACHE_SHIFT 10 | |
| 362 | #define OMAP3_L2CACHE_MASK (3 << OMAP3_L2CACHE_SHIFT) | |
| 363 | #define FEAT_L2CACHE_NONE 0 | |
| 364 | #define FEAT_L2CACHE_64KB 1 | |
| 365 | #define FEAT_L2CACHE_128KB 2 | |
| 366 | #define FEAT_L2CACHE_256KB 3 | |
| 367 | ||
| 368 | #define OMAP3_ISP_SHIFT 5 | |
| 4814ced5 | 369 | #define OMAP3_ISP_MASK (1 << OMAP3_ISP_SHIFT) |
| 8384ce07 SP |
370 | #define FEAT_ISP 0 |
| 371 | #define FEAT_ISP_NONE 1 | |
| 372 | ||
| 373 | #define OMAP3_NEON_SHIFT 4 | |
| 4814ced5 | 374 | #define OMAP3_NEON_MASK (1 << OMAP3_NEON_SHIFT) |
| 8384ce07 SP |
375 | #define FEAT_NEON 0 |
| 376 | #define FEAT_NEON_NONE 1 | |
| 377 | ||
| 378 | ||
| 69d88a00 | 379 | #ifndef __ASSEMBLY__ |
| 140455fa | 380 | #ifdef CONFIG_ARCH_OMAP2PLUS |
| a58caad1 | 381 | extern void __iomem *omap_ctrl_base_get(void); |
| 69d88a00 PW |
382 | extern u8 omap_ctrl_readb(u16 offset); |
| 383 | extern u16 omap_ctrl_readw(u16 offset); | |
| 384 | extern u32 omap_ctrl_readl(u16 offset); | |
| 70ba71a2 | 385 | extern u32 omap4_ctrl_pad_readl(u16 offset); |
| 69d88a00 PW |
386 | extern void omap_ctrl_writeb(u8 val, u16 offset); |
| 387 | extern void omap_ctrl_writew(u16 val, u16 offset); | |
| 388 | extern void omap_ctrl_writel(u32 val, u16 offset); | |
| 70ba71a2 | 389 | extern void omap4_ctrl_pad_writel(u32 val, u16 offset); |
| 80140786 RN |
390 | |
| 391 | extern void omap3_save_scratchpad_contents(void); | |
| 392 | extern void omap3_clear_scratchpad_contents(void); | |
| 14c79bbe KH |
393 | extern void omap3_restore(void); |
| 394 | extern void omap3_restore_es3(void); | |
| 395 | extern void omap3_restore_3630(void); | |
| 80140786 | 396 | extern u32 omap3_arm_context[128]; |
| c96631e1 RN |
397 | extern void omap3_control_save_context(void); |
| 398 | extern void omap3_control_restore_context(void); | |
| 166353bd | 399 | extern void omap3_ctrl_write_boot_mode(u8 bootmode); |
| 458e999e | 400 | extern void omap3630_ctrl_disable_rta(void); |
| 596efe47 | 401 | extern int omap3_ctrl_save_padconf(void); |
| 69d88a00 | 402 | #else |
| 69d88a00 PW |
403 | #define omap_ctrl_base_get() 0 |
| 404 | #define omap_ctrl_readb(x) 0 | |
| 405 | #define omap_ctrl_readw(x) 0 | |
| 406 | #define omap_ctrl_readl(x) 0 | |
| 70ba71a2 | 407 | #define omap4_ctrl_pad_readl(x) 0 |
| 69d88a00 PW |
408 | #define omap_ctrl_writeb(x, y) WARN_ON(1) |
| 409 | #define omap_ctrl_writew(x, y) WARN_ON(1) | |
| 410 | #define omap_ctrl_writel(x, y) WARN_ON(1) | |
| 70ba71a2 | 411 | #define omap4_ctrl_pad_writel(x, y) WARN_ON(1) |
| 69d88a00 PW |
412 | #endif |
| 413 | #endif /* __ASSEMBLY__ */ | |
| 414 | ||
| 4814ced5 | 415 | #endif /* __ARCH_ARM_MACH_OMAP2_CONTROL_H */ |
| 69d88a00 | 416 |