Commit | Line | Data |
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99e6a4d2 RN |
1 | /* |
2 | * linux/arch/arm/mach-omap2/cpuidle34xx.c | |
3 | * | |
4 | * OMAP3 CPU IDLE Routines | |
5 | * | |
6 | * Copyright (C) 2008 Texas Instruments, Inc. | |
7 | * Rajendra Nayak <rnayak@ti.com> | |
8 | * | |
9 | * Copyright (C) 2007 Texas Instruments, Inc. | |
10 | * Karthik Dasu <karthik-dp@ti.com> | |
11 | * | |
12 | * Copyright (C) 2006 Nokia Corporation | |
13 | * Tony Lindgren <tony@atomide.com> | |
14 | * | |
15 | * Copyright (C) 2005 Texas Instruments, Inc. | |
16 | * Richard Woodruff <r-woodruff2@ti.com> | |
17 | * | |
18 | * Based on pm.c for omap2 | |
19 | * | |
20 | * This program is free software; you can redistribute it and/or modify | |
21 | * it under the terms of the GNU General Public License version 2 as | |
22 | * published by the Free Software Foundation. | |
23 | */ | |
24 | ||
cf22854c | 25 | #include <linux/sched.h> |
99e6a4d2 | 26 | #include <linux/cpuidle.h> |
5698eb4e | 27 | #include <linux/export.h> |
ff819da4 | 28 | #include <linux/cpu_pm.h> |
99e6a4d2 | 29 | |
72e06d08 | 30 | #include "powerdomain.h" |
1540f214 | 31 | #include "clockdomain.h" |
99e6a4d2 | 32 | |
c98e2230 | 33 | #include "pm.h" |
4814ced5 | 34 | #include "control.h" |
ba8bb18a | 35 | #include "common.h" |
c98e2230 | 36 | |
badc303a JP |
37 | /* Mach specific information to be recorded in the C-state driver_data */ |
38 | struct omap3_idle_statedata { | |
39 | u32 mpu_state; | |
40 | u32 core_state; | |
badc303a | 41 | }; |
0c2487f6 | 42 | |
9db316b6 PW |
43 | static struct powerdomain *mpu_pd, *core_pd, *per_pd, *cam_pd; |
44 | ||
97abc496 | 45 | static struct omap3_idle_statedata omap3_idle_data[] = { |
88c377dd DL |
46 | { |
47 | .mpu_state = PWRDM_POWER_ON, | |
48 | .core_state = PWRDM_POWER_ON, | |
49 | }, | |
50 | { | |
51 | .mpu_state = PWRDM_POWER_ON, | |
52 | .core_state = PWRDM_POWER_ON, | |
53 | }, | |
54 | { | |
55 | .mpu_state = PWRDM_POWER_RET, | |
56 | .core_state = PWRDM_POWER_ON, | |
57 | }, | |
58 | { | |
59 | .mpu_state = PWRDM_POWER_OFF, | |
60 | .core_state = PWRDM_POWER_ON, | |
61 | }, | |
62 | { | |
63 | .mpu_state = PWRDM_POWER_RET, | |
64 | .core_state = PWRDM_POWER_RET, | |
65 | }, | |
66 | { | |
67 | .mpu_state = PWRDM_POWER_OFF, | |
68 | .core_state = PWRDM_POWER_RET, | |
69 | }, | |
70 | { | |
71 | .mpu_state = PWRDM_POWER_OFF, | |
72 | .core_state = PWRDM_POWER_OFF, | |
73 | }, | |
74 | }; | |
badc303a | 75 | |
9db316b6 | 76 | /* Private functions */ |
bb4de3df | 77 | |
6da45dce | 78 | static int __omap3_enter_idle(struct cpuidle_device *dev, |
46bcfad7 | 79 | struct cpuidle_driver *drv, |
e978aa7d | 80 | int index) |
99e6a4d2 | 81 | { |
6622ac55 | 82 | struct omap3_idle_statedata *cx = &omap3_idle_data[index]; |
c98e2230 | 83 | u32 mpu_state = cx->mpu_state, core_state = cx->core_state; |
99e6a4d2 | 84 | |
99e6a4d2 RN |
85 | local_fiq_disable(); |
86 | ||
7139178e JH |
87 | pwrdm_set_next_pwrst(mpu_pd, mpu_state); |
88 | pwrdm_set_next_pwrst(core_pd, core_state); | |
20b01669 | 89 | |
cf22854c | 90 | if (omap_irq_pending() || need_resched()) |
20b01669 | 91 | goto return_sleep_time; |
99e6a4d2 | 92 | |
badc303a | 93 | /* Deny idle for C1 */ |
e978aa7d | 94 | if (index == 0) { |
05011f71 JP |
95 | clkdm_deny_idle(mpu_pd->pwrdm_clkdms[0]); |
96 | clkdm_deny_idle(core_pd->pwrdm_clkdms[0]); | |
06d8f065 PDS |
97 | } |
98 | ||
ff819da4 SS |
99 | /* |
100 | * Call idle CPU PM enter notifier chain so that | |
101 | * VFP context is saved. | |
102 | */ | |
103 | if (mpu_state == PWRDM_POWER_OFF) | |
104 | cpu_pm_enter(); | |
105 | ||
99e6a4d2 RN |
106 | /* Execute ARM wfi */ |
107 | omap_sram_idle(); | |
108 | ||
ff819da4 SS |
109 | /* |
110 | * Call idle CPU PM enter notifier chain to restore | |
111 | * VFP context. | |
112 | */ | |
113 | if (pwrdm_read_prev_pwrst(mpu_pd) == PWRDM_POWER_OFF) | |
114 | cpu_pm_exit(); | |
115 | ||
badc303a | 116 | /* Re-allow idle for C1 */ |
e978aa7d | 117 | if (index == 0) { |
05011f71 JP |
118 | clkdm_allow_idle(mpu_pd->pwrdm_clkdms[0]); |
119 | clkdm_allow_idle(core_pd->pwrdm_clkdms[0]); | |
06d8f065 PDS |
120 | } |
121 | ||
20b01669 | 122 | return_sleep_time: |
99e6a4d2 | 123 | |
99e6a4d2 RN |
124 | local_fiq_enable(); |
125 | ||
e978aa7d | 126 | return index; |
99e6a4d2 RN |
127 | } |
128 | ||
6da45dce RL |
129 | /** |
130 | * omap3_enter_idle - Programs OMAP3 to enter the specified state | |
131 | * @dev: cpuidle device | |
132 | * @drv: cpuidle driver | |
133 | * @index: the index of state to be entered | |
134 | * | |
135 | * Called from the CPUidle framework to program the device to the | |
136 | * specified target state selected by the governor. | |
137 | */ | |
138 | static inline int omap3_enter_idle(struct cpuidle_device *dev, | |
139 | struct cpuidle_driver *drv, | |
140 | int index) | |
141 | { | |
142 | return cpuidle_wrap_enter(dev, drv, index, __omap3_enter_idle); | |
143 | } | |
144 | ||
6af83b38 | 145 | /** |
04908918 | 146 | * next_valid_state - Find next valid C-state |
6af83b38 | 147 | * @dev: cpuidle device |
46bcfad7 | 148 | * @drv: cpuidle driver |
e978aa7d | 149 | * @index: Index of currently selected c-state |
6af83b38 | 150 | * |
e978aa7d DD |
151 | * If the state corresponding to index is valid, index is returned back |
152 | * to the caller. Else, this function searches for a lower c-state which is | |
153 | * still valid (as defined in omap3_power_states[]) and returns its index. | |
04908918 JP |
154 | * |
155 | * A state is valid if the 'valid' field is enabled and | |
156 | * if it satisfies the enable_off_mode condition. | |
6af83b38 | 157 | */ |
e978aa7d | 158 | static int next_valid_state(struct cpuidle_device *dev, |
e92a4586 | 159 | struct cpuidle_driver *drv, int index) |
6af83b38 | 160 | { |
6622ac55 | 161 | struct omap3_idle_statedata *cx = &omap3_idle_data[index]; |
04908918 JP |
162 | u32 mpu_deepest_state = PWRDM_POWER_RET; |
163 | u32 core_deepest_state = PWRDM_POWER_RET; | |
e92a4586 | 164 | int idx; |
063a5d01 | 165 | int next_index = 0; /* C1 is the default value */ |
04908918 JP |
166 | |
167 | if (enable_off_mode) { | |
168 | mpu_deepest_state = PWRDM_POWER_OFF; | |
169 | /* | |
170 | * Erratum i583: valable for ES rev < Es1.2 on 3630. | |
171 | * CORE OFF mode is not supported in a stable form, restrict | |
172 | * instead the CORE state to RET. | |
173 | */ | |
174 | if (!IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583)) | |
175 | core_deepest_state = PWRDM_POWER_OFF; | |
176 | } | |
6af83b38 SP |
177 | |
178 | /* Check if current state is valid */ | |
f79b5d8a | 179 | if ((cx->mpu_state >= mpu_deepest_state) && |
e92a4586 | 180 | (cx->core_state >= core_deepest_state)) |
e978aa7d | 181 | return index; |
6af83b38 | 182 | |
e92a4586 DL |
183 | /* |
184 | * Drop to next valid state. | |
185 | * Start search from the next (lower) state. | |
186 | */ | |
187 | for (idx = index - 1; idx >= 0; idx--) { | |
188 | cx = &omap3_idle_data[idx]; | |
189 | if ((cx->mpu_state >= mpu_deepest_state) && | |
190 | (cx->core_state >= core_deepest_state)) { | |
191 | next_index = idx; | |
192 | break; | |
6af83b38 | 193 | } |
6af83b38 SP |
194 | } |
195 | ||
e978aa7d | 196 | return next_index; |
6af83b38 SP |
197 | } |
198 | ||
99e6a4d2 RN |
199 | /** |
200 | * omap3_enter_idle_bm - Checks for any bus activity | |
201 | * @dev: cpuidle device | |
46bcfad7 | 202 | * @drv: cpuidle driver |
e978aa7d | 203 | * @index: array index of target state to be programmed |
99e6a4d2 | 204 | * |
badc303a JP |
205 | * This function checks for any pending activity and then programs |
206 | * the device to the specified or a safer state. | |
99e6a4d2 RN |
207 | */ |
208 | static int omap3_enter_idle_bm(struct cpuidle_device *dev, | |
13d65c89 | 209 | struct cpuidle_driver *drv, |
e978aa7d | 210 | int index) |
99e6a4d2 | 211 | { |
e978aa7d | 212 | int new_state_idx; |
13d65c89 | 213 | u32 core_next_state, per_next_state = 0, per_saved_state = 0; |
badc303a | 214 | struct omap3_idle_statedata *cx; |
e7410cf7 | 215 | int ret; |
0f724ed9 | 216 | |
e7410cf7 | 217 | /* |
13d65c89 | 218 | * Use only C1 if CAM is active. |
e7410cf7 KH |
219 | * CAM does not have wakeup capability in OMAP3. |
220 | */ | |
13d65c89 | 221 | if (pwrdm_read_pwrst(cam_pd) == PWRDM_POWER_ON) |
46bcfad7 | 222 | new_state_idx = drv->safe_state_index; |
13d65c89 JP |
223 | else |
224 | new_state_idx = next_valid_state(dev, drv, index); | |
e7410cf7 | 225 | |
c6cd91de JP |
226 | /* |
227 | * FIXME: we currently manage device-specific idle states | |
228 | * for PER and CORE in combination with CPU-specific | |
229 | * idle states. This is wrong, and device-specific | |
230 | * idle management needs to be separated out into | |
231 | * its own code. | |
232 | */ | |
233 | ||
13d65c89 JP |
234 | /* Program PER state */ |
235 | cx = &omap3_idle_data[new_state_idx]; | |
c6cd91de | 236 | core_next_state = cx->core_state; |
e7410cf7 | 237 | per_next_state = per_saved_state = pwrdm_read_next_pwrst(per_pd); |
13d65c89 JP |
238 | if (new_state_idx == 0) { |
239 | /* In C1 do not allow PER state lower than CORE state */ | |
240 | if (per_next_state < core_next_state) | |
241 | per_next_state = core_next_state; | |
242 | } else { | |
243 | /* | |
244 | * Prevent PER OFF if CORE is not in RETention or OFF as this | |
245 | * would disable PER wakeups completely. | |
246 | */ | |
247 | if ((per_next_state == PWRDM_POWER_OFF) && | |
248 | (core_next_state > PWRDM_POWER_RET)) | |
249 | per_next_state = PWRDM_POWER_RET; | |
250 | } | |
0f724ed9 | 251 | |
e7410cf7 KH |
252 | /* Are we changing PER target state? */ |
253 | if (per_next_state != per_saved_state) | |
254 | pwrdm_set_next_pwrst(per_pd, per_next_state); | |
255 | ||
46bcfad7 | 256 | ret = omap3_enter_idle(dev, drv, new_state_idx); |
e7410cf7 KH |
257 | |
258 | /* Restore original PER state if it was modified */ | |
259 | if (per_next_state != per_saved_state) | |
260 | pwrdm_set_next_pwrst(per_pd, per_saved_state); | |
261 | ||
262 | return ret; | |
99e6a4d2 RN |
263 | } |
264 | ||
9db316b6 | 265 | static DEFINE_PER_CPU(struct cpuidle_device, omap3_idle_dev); |
99e6a4d2 | 266 | |
9db316b6 PW |
267 | static struct cpuidle_driver omap3_idle_driver = { |
268 | .name = "omap3_idle", | |
269 | .owner = THIS_MODULE, | |
200dd520 DL |
270 | .states = { |
271 | { | |
13d65c89 | 272 | .enter = omap3_enter_idle_bm, |
200dd520 DL |
273 | .exit_latency = 2 + 2, |
274 | .target_residency = 5, | |
275 | .flags = CPUIDLE_FLAG_TIME_VALID, | |
276 | .name = "C1", | |
277 | .desc = "MPU ON + CORE ON", | |
278 | }, | |
279 | { | |
280 | .enter = omap3_enter_idle_bm, | |
281 | .exit_latency = 10 + 10, | |
282 | .target_residency = 30, | |
283 | .flags = CPUIDLE_FLAG_TIME_VALID, | |
284 | .name = "C2", | |
285 | .desc = "MPU ON + CORE ON", | |
286 | }, | |
287 | { | |
288 | .enter = omap3_enter_idle_bm, | |
289 | .exit_latency = 50 + 50, | |
290 | .target_residency = 300, | |
291 | .flags = CPUIDLE_FLAG_TIME_VALID, | |
292 | .name = "C3", | |
293 | .desc = "MPU RET + CORE ON", | |
294 | }, | |
295 | { | |
296 | .enter = omap3_enter_idle_bm, | |
297 | .exit_latency = 1500 + 1800, | |
298 | .target_residency = 4000, | |
299 | .flags = CPUIDLE_FLAG_TIME_VALID, | |
300 | .name = "C4", | |
301 | .desc = "MPU OFF + CORE ON", | |
302 | }, | |
303 | { | |
304 | .enter = omap3_enter_idle_bm, | |
305 | .exit_latency = 2500 + 7500, | |
306 | .target_residency = 12000, | |
307 | .flags = CPUIDLE_FLAG_TIME_VALID, | |
308 | .name = "C5", | |
309 | .desc = "MPU RET + CORE RET", | |
310 | }, | |
311 | { | |
312 | .enter = omap3_enter_idle_bm, | |
313 | .exit_latency = 3000 + 8500, | |
314 | .target_residency = 15000, | |
315 | .flags = CPUIDLE_FLAG_TIME_VALID, | |
316 | .name = "C6", | |
317 | .desc = "MPU OFF + CORE RET", | |
318 | }, | |
319 | { | |
320 | .enter = omap3_enter_idle_bm, | |
321 | .exit_latency = 10000 + 30000, | |
322 | .target_residency = 30000, | |
323 | .flags = CPUIDLE_FLAG_TIME_VALID, | |
324 | .name = "C7", | |
325 | .desc = "MPU OFF + CORE OFF", | |
326 | }, | |
327 | }, | |
88c377dd | 328 | .state_count = ARRAY_SIZE(omap3_idle_data), |
200dd520 | 329 | .safe_state_index = 0, |
99e6a4d2 RN |
330 | }; |
331 | ||
9db316b6 PW |
332 | /* Public functions */ |
333 | ||
99e6a4d2 RN |
334 | /** |
335 | * omap3_idle_init - Init routine for OMAP3 idle | |
336 | * | |
badc303a | 337 | * Registers the OMAP3 specific cpuidle driver to the cpuidle |
99e6a4d2 RN |
338 | * framework with the valid set of states. |
339 | */ | |
0343371e | 340 | int __init omap3_idle_init(void) |
99e6a4d2 | 341 | { |
99e6a4d2 RN |
342 | struct cpuidle_device *dev; |
343 | ||
344 | mpu_pd = pwrdm_lookup("mpu_pwrdm"); | |
20b01669 | 345 | core_pd = pwrdm_lookup("core_pwrdm"); |
e7410cf7 KH |
346 | per_pd = pwrdm_lookup("per_pwrdm"); |
347 | cam_pd = pwrdm_lookup("cam_pwrdm"); | |
99e6a4d2 | 348 | |
daa37cee DL |
349 | if (!mpu_pd || !core_pd || !per_pd || !cam_pd) |
350 | return -ENODEV; | |
351 | ||
6622ac55 | 352 | cpuidle_register_driver(&omap3_idle_driver); |
46bcfad7 | 353 | |
99e6a4d2 | 354 | dev = &per_cpu(omap3_idle_dev, smp_processor_id()); |
6622ac55 | 355 | dev->cpu = 0; |
46bcfad7 | 356 | |
99e6a4d2 RN |
357 | if (cpuidle_register_device(dev)) { |
358 | printk(KERN_ERR "%s: CPUidle register device failed\n", | |
359 | __func__); | |
360 | return -EIO; | |
361 | } | |
362 | ||
363 | return 0; | |
364 | } |