[deliverable/linux.git] / arch / arm / mach-omap2 / cpuidle34xx.c

/*
 * linux/arch/arm/mach-omap2/cpuidle34xx.c
 *
 * OMAP3 CPU IDLE Routines
 *
 * Copyright (C) 2008 Texas Instruments, Inc.
 * Rajendra Nayak <rnayak@ti.com>
 *
 * Copyright (C) 2007 Texas Instruments, Inc.
 * Karthik Dasu <karthik-dp@ti.com>
 *
 * Copyright (C) 2006 Nokia Corporation
 * Tony Lindgren <tony@atomide.com>
 *
 * Copyright (C) 2005 Texas Instruments, Inc.
 * Richard Woodruff <r-woodruff2@ti.com>
 *
 * Based on pm.c for omap2
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/sched.h>
#include <linux/cpuidle.h>
#include <linux/export.h>
#include <linux/cpu_pm.h>

#include "powerdomain.h"
#include "clockdomain.h"

#include "pm.h"
#include "control.h"
#include "common.h"

/* Mach specific information to be recorded in the C-state driver_data */
struct omap3_idle_statedata {
	u8 mpu_state;
	u8 core_state;
	u8 per_min_state;
	u8 flags;
};

static struct powerdomain *mpu_pd, *core_pd, *per_pd, *cam_pd;

/*
 * Possible flag bits for struct omap3_idle_statedata.flags:
 *
 * OMAP_CPUIDLE_CX_NO_CLKDM_IDLE: don't allow the MPU clockdomain to go
 *    inactive.  This in turn prevents the MPU DPLL from entering autoidle
 *    mode, so wakeup latency is greatly reduced, at the cost of additional
 *    energy consumption.  This also prevents the CORE clockdomain from
 *    entering idle.
 */
#define OMAP_CPUIDLE_CX_NO_CLKDM_IDLE		BIT(0)

/*
 * Prevent PER OFF if CORE is not in RETention or OFF as this would
 * disable PER wakeups completely.
 */
static struct omap3_idle_statedata omap3_idle_data[] = {
	{
		.mpu_state = PWRDM_POWER_ON,
		.core_state = PWRDM_POWER_ON,
		/* In C1 do not allow PER state lower than CORE state */
		.per_min_state = PWRDM_POWER_ON,
		.flags = OMAP_CPUIDLE_CX_NO_CLKDM_IDLE,
	},
	{
		.mpu_state = PWRDM_POWER_ON,
		.core_state = PWRDM_POWER_ON,
		.per_min_state = PWRDM_POWER_RET,
	},
	{
		.mpu_state = PWRDM_POWER_RET,
		.core_state = PWRDM_POWER_ON,
		.per_min_state = PWRDM_POWER_RET,
	},
	{
		.mpu_state = PWRDM_POWER_OFF,
		.core_state = PWRDM_POWER_ON,
		.per_min_state = PWRDM_POWER_RET,
	},
	{
		.mpu_state = PWRDM_POWER_RET,
		.core_state = PWRDM_POWER_RET,
		.per_min_state = PWRDM_POWER_OFF,
	},
	{
		.mpu_state = PWRDM_POWER_OFF,
		.core_state = PWRDM_POWER_RET,
		.per_min_state = PWRDM_POWER_OFF,
	},
	{
		.mpu_state = PWRDM_POWER_OFF,
		.core_state = PWRDM_POWER_OFF,
		.per_min_state = PWRDM_POWER_OFF,
	},
};

/* Private functions */

static int __omap3_enter_idle(struct cpuidle_device *dev,
				struct cpuidle_driver *drv,
				int index)
{
	struct omap3_idle_statedata *cx = &omap3_idle_data[index];

	local_fiq_disable();

	if (omap_irq_pending() || need_resched())
		goto return_sleep_time;

	/* Deny idle for C1 */
	if (cx->flags & OMAP_CPUIDLE_CX_NO_CLKDM_IDLE) {
		clkdm_deny_idle(mpu_pd->pwrdm_clkdms[0]);
	} else {
		pwrdm_set_next_pwrst(mpu_pd, cx->mpu_state);
		pwrdm_set_next_pwrst(core_pd, cx->core_state);
	}

	/*
	 * Call idle CPU PM enter notifier chain so that
	 * VFP context is saved.
	 */
	if (cx->mpu_state == PWRDM_POWER_OFF)
		cpu_pm_enter();

	/* Execute ARM wfi */
	omap_sram_idle();

	/*
	 * Call idle CPU PM enter notifier chain to restore
	 * VFP context.
	 */
	if (cx->mpu_state == PWRDM_POWER_OFF &&
	    pwrdm_read_prev_pwrst(mpu_pd) == PWRDM_POWER_OFF)
		cpu_pm_exit();

	/* Re-allow idle for C1 */
	if (cx->flags & OMAP_CPUIDLE_CX_NO_CLKDM_IDLE)
		clkdm_allow_idle(mpu_pd->pwrdm_clkdms[0]);

return_sleep_time:
	local_fiq_enable();

	return index;
}

/**
 * omap3_enter_idle - Programs OMAP3 to enter the specified state
 * @dev: cpuidle device
 * @drv: cpuidle driver
 * @index: the index of state to be entered
 *
 * Called from the CPUidle framework to program the device to the
 * specified target state selected by the governor.
 */
static inline int omap3_enter_idle(struct cpuidle_device *dev,
				struct cpuidle_driver *drv,
				int index)
{
	return cpuidle_wrap_enter(dev, drv, index, __omap3_enter_idle);
}

/**
 * next_valid_state - Find next valid C-state
 * @dev: cpuidle device
 * @drv: cpuidle driver
 * @index: Index of currently selected c-state
 *
 * If the state corresponding to index is valid, index is returned back
 * to the caller. Else, this function searches for a lower c-state which is
 * still valid (as defined in omap3_power_states[]) and returns its index.
 *
 * A state is valid if the 'valid' field is enabled and
 * if it satisfies the enable_off_mode condition.
 */
static int next_valid_state(struct cpuidle_device *dev,
			    struct cpuidle_driver *drv, int index)
{
	struct omap3_idle_statedata *cx = &omap3_idle_data[index];
	u32 mpu_deepest_state = PWRDM_POWER_RET;
	u32 core_deepest_state = PWRDM_POWER_RET;
	int idx;
	int next_index = 0; /* C1 is the default value */

	if (enable_off_mode) {
		mpu_deepest_state = PWRDM_POWER_OFF;
		/*
		 * Erratum i583: valable for ES rev < Es1.2 on 3630.
		 * CORE OFF mode is not supported in a stable form, restrict
		 * instead the CORE state to RET.
		 */
		if (!IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583))
			core_deepest_state = PWRDM_POWER_OFF;
	}

	/* Check if current state is valid */
	if ((cx->mpu_state >= mpu_deepest_state) &&
	    (cx->core_state >= core_deepest_state))
		return index;

	/*
	 * Drop to next valid state.
	 * Start search from the next (lower) state.
	 */
	for (idx = index - 1; idx >= 0; idx--) {
		cx = &omap3_idle_data[idx];
		if ((cx->mpu_state >= mpu_deepest_state) &&
		    (cx->core_state >= core_deepest_state)) {
			next_index = idx;
			break;
		}
	}

	return next_index;
}

/**
 * omap3_enter_idle_bm - Checks for any bus activity
 * @dev: cpuidle device
 * @drv: cpuidle driver
 * @index: array index of target state to be programmed
 *
 * This function checks for any pending activity and then programs
 * the device to the specified or a safer state.
 */
static int omap3_enter_idle_bm(struct cpuidle_device *dev,
			       struct cpuidle_driver *drv,
			       int index)
{
	int new_state_idx, ret;
	u8 per_next_state, per_saved_state;
	struct omap3_idle_statedata *cx;

	/*
	 * Use only C1 if CAM is active.
	 * CAM does not have wakeup capability in OMAP3.
	 */
	if (pwrdm_read_pwrst(cam_pd) == PWRDM_POWER_ON)
		new_state_idx = drv->safe_state_index;
	else
		new_state_idx = next_valid_state(dev, drv, index);

	/*
	 * FIXME: we currently manage device-specific idle states
	 *        for PER and CORE in combination with CPU-specific
	 *        idle states.  This is wrong, and device-specific
	 *        idle management needs to be separated out into
	 *        its own code.
	 */

	/* Program PER state */
	cx = &omap3_idle_data[new_state_idx];

	per_next_state = pwrdm_read_next_pwrst(per_pd);
	per_saved_state = per_next_state;
	if (per_next_state < cx->per_min_state) {
		per_next_state = cx->per_min_state;
		pwrdm_set_next_pwrst(per_pd, per_next_state);
	}

	ret = omap3_enter_idle(dev, drv, new_state_idx);

	/* Restore original PER state if it was modified */
	if (per_next_state != per_saved_state)
		pwrdm_set_next_pwrst(per_pd, per_saved_state);

	return ret;
}

static DEFINE_PER_CPU(struct cpuidle_device, omap3_idle_dev);

static struct cpuidle_driver omap3_idle_driver = {
	.name =		"omap3_idle",
	.owner =	THIS_MODULE,
	.states = {
		{
			.enter		  = omap3_enter_idle_bm,
			.exit_latency	  = 2 + 2,
			.target_residency = 5,
			.flags		  = CPUIDLE_FLAG_TIME_VALID,
			.name		  = "C1",
			.desc		  = "MPU ON + CORE ON",
		},
		{
			.enter		  = omap3_enter_idle_bm,
			.exit_latency	  = 10 + 10,
			.target_residency = 30,
			.flags		  = CPUIDLE_FLAG_TIME_VALID,
			.name		  = "C2",
			.desc		  = "MPU ON + CORE ON",
		},
		{
			.enter		  = omap3_enter_idle_bm,
			.exit_latency	  = 50 + 50,
			.target_residency = 300,
			.flags		  = CPUIDLE_FLAG_TIME_VALID,
			.name		  = "C3",
			.desc		  = "MPU RET + CORE ON",
		},
		{
			.enter		  = omap3_enter_idle_bm,
			.exit_latency	  = 1500 + 1800,
			.target_residency = 4000,
			.flags		  = CPUIDLE_FLAG_TIME_VALID,
			.name		  = "C4",
			.desc		  = "MPU OFF + CORE ON",
		},
		{
			.enter		  = omap3_enter_idle_bm,
			.exit_latency	  = 2500 + 7500,
			.target_residency = 12000,
			.flags		  = CPUIDLE_FLAG_TIME_VALID,
			.name		  = "C5",
			.desc		  = "MPU RET + CORE RET",
		},
		{
			.enter		  = omap3_enter_idle_bm,
			.exit_latency	  = 3000 + 8500,
			.target_residency = 15000,
			.flags		  = CPUIDLE_FLAG_TIME_VALID,
			.name		  = "C6",
			.desc		  = "MPU OFF + CORE RET",
		},
		{
			.enter		  = omap3_enter_idle_bm,
			.exit_latency	  = 10000 + 30000,
			.target_residency = 30000,
			.flags		  = CPUIDLE_FLAG_TIME_VALID,
			.name		  = "C7",
			.desc		  = "MPU OFF + CORE OFF",
		},
	},
	.state_count = ARRAY_SIZE(omap3_idle_data),
	.safe_state_index = 0,
};

/* Public functions */

/**
 * omap3_idle_init - Init routine for OMAP3 idle
 *
 * Registers the OMAP3 specific cpuidle driver to the cpuidle
 * framework with the valid set of states.
 */
int __init omap3_idle_init(void)
{
	struct cpuidle_device *dev;

	mpu_pd = pwrdm_lookup("mpu_pwrdm");
	core_pd = pwrdm_lookup("core_pwrdm");
	per_pd = pwrdm_lookup("per_pwrdm");
	cam_pd = pwrdm_lookup("cam_pwrdm");

	if (!mpu_pd || !core_pd || !per_pd || !cam_pd)
		return -ENODEV;

	cpuidle_register_driver(&omap3_idle_driver);

	dev = &per_cpu(omap3_idle_dev, smp_processor_id());
	dev->cpu = 0;

	if (cpuidle_register_device(dev)) {
		printk(KERN_ERR "%s: CPUidle register device failed\n",
		       __func__);
		return -EIO;
	}

	return 0;
}
Commit	Line	Data
99e6a4d2 RN	1	/*
	2	* linux/arch/arm/mach-omap2/cpuidle34xx.c
	3	*
	4	* OMAP3 CPU IDLE Routines
	5	*
	6	* Copyright (C) 2008 Texas Instruments, Inc.
	7	* Rajendra Nayak <rnayak@ti.com>
	8	*
	9	* Copyright (C) 2007 Texas Instruments, Inc.
	10	* Karthik Dasu <karthik-dp@ti.com>
	11	*
	12	* Copyright (C) 2006 Nokia Corporation
	13	* Tony Lindgren <tony@atomide.com>
	14	*
	15	* Copyright (C) 2005 Texas Instruments, Inc.
	16	* Richard Woodruff <r-woodruff2@ti.com>
	17	*
	18	* Based on pm.c for omap2
	19	*
	20	* This program is free software; you can redistribute it and/or modify
	21	* it under the terms of the GNU General Public License version 2 as
	22	* published by the Free Software Foundation.
	23	*/
	24
cf22854c	25	#include <linux/sched.h>
99e6a4d2	26	#include <linux/cpuidle.h>
5698eb4e	27	#include <linux/export.h>
ff819da4	28	#include <linux/cpu_pm.h>
99e6a4d2	29
72e06d08	30	#include "powerdomain.h"
1540f214	31	#include "clockdomain.h"
99e6a4d2	32
c98e2230	33	#include "pm.h"
4814ced5	34	#include "control.h"
ba8bb18a	35	#include "common.h"
c98e2230	36
badc303a JP	37	/* Mach specific information to be recorded in the C-state driver_data */
badc303a JP	38	struct omap3_idle_statedata {
fd6b42a5 PW	39	u8 mpu_state;
	40	u8 core_state;
	41	u8 per_min_state;
1cd96478	42	u8 flags;
badc303a	43	};
0c2487f6	44
9db316b6 PW	45	static struct powerdomain mpu_pd, core_pd, per_pd, cam_pd;
9db316b6 PW	46
1cd96478 PW	47	/*
	48	* Possible flag bits for struct omap3_idle_statedata.flags:
	49	*
	50	* OMAP_CPUIDLE_CX_NO_CLKDM_IDLE: don't allow the MPU clockdomain to go
	51	* inactive. This in turn prevents the MPU DPLL from entering autoidle
	52	* mode, so wakeup latency is greatly reduced, at the cost of additional
	53	* energy consumption. This also prevents the CORE clockdomain from
	54	* entering idle.
	55	*/
	56	#define OMAP_CPUIDLE_CX_NO_CLKDM_IDLE BIT(0)
	57
fd6b42a5 PW	58	/*
	59	* Prevent PER OFF if CORE is not in RETention or OFF as this would
	60	* disable PER wakeups completely.
	61	*/
97abc496	62	static struct omap3_idle_statedata omap3_idle_data[] = {
88c377dd DL	63	{
	64	.mpu_state = PWRDM_POWER_ON,
	65	.core_state = PWRDM_POWER_ON,
fd6b42a5 PW	66	/* In C1 do not allow PER state lower than CORE state */
fd6b42a5 PW	67	.per_min_state = PWRDM_POWER_ON,
1cd96478	68	.flags = OMAP_CPUIDLE_CX_NO_CLKDM_IDLE,
88c377dd DL	69	},
	70	{
	71	.mpu_state = PWRDM_POWER_ON,
	72	.core_state = PWRDM_POWER_ON,
fd6b42a5	73	.per_min_state = PWRDM_POWER_RET,
88c377dd DL	74	},
	75	{
	76	.mpu_state = PWRDM_POWER_RET,
	77	.core_state = PWRDM_POWER_ON,
fd6b42a5	78	.per_min_state = PWRDM_POWER_RET,
88c377dd DL	79	},
	80	{
	81	.mpu_state = PWRDM_POWER_OFF,
	82	.core_state = PWRDM_POWER_ON,
fd6b42a5	83	.per_min_state = PWRDM_POWER_RET,
88c377dd DL	84	},
	85	{
	86	.mpu_state = PWRDM_POWER_RET,
	87	.core_state = PWRDM_POWER_RET,
fd6b42a5	88	.per_min_state = PWRDM_POWER_OFF,
88c377dd DL	89	},
	90	{
	91	.mpu_state = PWRDM_POWER_OFF,
	92	.core_state = PWRDM_POWER_RET,
fd6b42a5	93	.per_min_state = PWRDM_POWER_OFF,
88c377dd DL	94	},
	95	{
	96	.mpu_state = PWRDM_POWER_OFF,
	97	.core_state = PWRDM_POWER_OFF,
fd6b42a5	98	.per_min_state = PWRDM_POWER_OFF,
88c377dd DL	99	},
88c377dd DL	100	};
badc303a	101
9db316b6	102	/* Private functions */
bb4de3df	103
6da45dce	104	static int __omap3_enter_idle(struct cpuidle_device *dev,
46bcfad7	105	struct cpuidle_driver *drv,
e978aa7d	106	int index)
99e6a4d2	107	{
6622ac55	108	struct omap3_idle_statedata *cx = &omap3_idle_data[index];
99e6a4d2	109
99e6a4d2 RN	110	local_fiq_disable();
99e6a4d2 RN	111
cf22854c	112	if (omap_irq_pending() \|\| need_resched())
20b01669	113	goto return_sleep_time;
99e6a4d2	114
badc303a	115	/* Deny idle for C1 */
1cd96478	116	if (cx->flags & OMAP_CPUIDLE_CX_NO_CLKDM_IDLE) {
05011f71	117	clkdm_deny_idle(mpu_pd->pwrdm_clkdms[0]);
1cd96478 PW	118	} else {
	119	pwrdm_set_next_pwrst(mpu_pd, cx->mpu_state);
	120	pwrdm_set_next_pwrst(core_pd, cx->core_state);
06d8f065 PDS	121	}
06d8f065 PDS	122
ff819da4 SS	123	/*
	124	* Call idle CPU PM enter notifier chain so that
	125	* VFP context is saved.
	126	*/
1cd96478	127	if (cx->mpu_state == PWRDM_POWER_OFF)
ff819da4 SS	128	cpu_pm_enter();
ff819da4 SS	129
99e6a4d2 RN	130	/* Execute ARM wfi */
	131	omap_sram_idle();
	132
ff819da4 SS	133	/*
	134	* Call idle CPU PM enter notifier chain to restore
	135	* VFP context.
	136	*/
1cd96478 PW	137	if (cx->mpu_state == PWRDM_POWER_OFF &&
1cd96478 PW	138	pwrdm_read_prev_pwrst(mpu_pd) == PWRDM_POWER_OFF)
ff819da4 SS	139	cpu_pm_exit();
ff819da4 SS	140
badc303a	141	/* Re-allow idle for C1 */
1cd96478	142	if (cx->flags & OMAP_CPUIDLE_CX_NO_CLKDM_IDLE)
05011f71	143	clkdm_allow_idle(mpu_pd->pwrdm_clkdms[0]);
06d8f065	144
20b01669	145	return_sleep_time:
99e6a4d2 RN	146	local_fiq_enable();
99e6a4d2 RN	147
e978aa7d	148	return index;
99e6a4d2 RN	149	}
99e6a4d2 RN	150
6da45dce RL	151	/**
	152	* omap3_enter_idle - Programs OMAP3 to enter the specified state
	153	* @dev: cpuidle device
	154	* @drv: cpuidle driver
	155	* @index: the index of state to be entered
	156	*
	157	* Called from the CPUidle framework to program the device to the
	158	* specified target state selected by the governor.
	159	*/
	160	static inline int omap3_enter_idle(struct cpuidle_device *dev,
	161	struct cpuidle_driver *drv,
	162	int index)
	163	{
	164	return cpuidle_wrap_enter(dev, drv, index, __omap3_enter_idle);
	165	}
	166
6af83b38	167	/**
04908918	168	* next_valid_state - Find next valid C-state
6af83b38	169	* @dev: cpuidle device
46bcfad7	170	* @drv: cpuidle driver
e978aa7d	171	* @index: Index of currently selected c-state
6af83b38	172	*
e978aa7d DD	173	* If the state corresponding to index is valid, index is returned back
	174	* to the caller. Else, this function searches for a lower c-state which is
	175	* still valid (as defined in omap3_power_states[]) and returns its index.
04908918 JP	176	*
	177	* A state is valid if the 'valid' field is enabled and
	178	* if it satisfies the enable_off_mode condition.
6af83b38	179	*/
e978aa7d	180	static int next_valid_state(struct cpuidle_device *dev,
e92a4586	181	struct cpuidle_driver *drv, int index)
6af83b38	182	{
6622ac55	183	struct omap3_idle_statedata *cx = &omap3_idle_data[index];
04908918 JP	184	u32 mpu_deepest_state = PWRDM_POWER_RET;
04908918 JP	185	u32 core_deepest_state = PWRDM_POWER_RET;
e92a4586	186	int idx;
063a5d01	187	int next_index = 0; /* C1 is the default value */
04908918 JP	188
	189	if (enable_off_mode) {
	190	mpu_deepest_state = PWRDM_POWER_OFF;
	191	/*
	192	* Erratum i583: valable for ES rev < Es1.2 on 3630.
	193	* CORE OFF mode is not supported in a stable form, restrict
	194	* instead the CORE state to RET.
	195	*/
	196	if (!IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583))
	197	core_deepest_state = PWRDM_POWER_OFF;
	198	}
6af83b38 SP	199
6af83b38 SP	200	/* Check if current state is valid */
f79b5d8a	201	if ((cx->mpu_state >= mpu_deepest_state) &&
e92a4586	202	(cx->core_state >= core_deepest_state))
e978aa7d	203	return index;
6af83b38	204
e92a4586 DL	205	/*
	206	* Drop to next valid state.
	207	* Start search from the next (lower) state.
	208	*/
	209	for (idx = index - 1; idx >= 0; idx--) {
1cd96478	210	cx = &omap3_idle_data[idx];
e92a4586 DL	211	if ((cx->mpu_state >= mpu_deepest_state) &&
	212	(cx->core_state >= core_deepest_state)) {
	213	next_index = idx;
	214	break;
6af83b38	215	}
6af83b38 SP	216	}
6af83b38 SP	217
e978aa7d	218	return next_index;
6af83b38 SP	219	}
6af83b38 SP	220
99e6a4d2 RN	221	/**
	222	* omap3_enter_idle_bm - Checks for any bus activity
	223	* @dev: cpuidle device
46bcfad7	224	* @drv: cpuidle driver
e978aa7d	225	* @index: array index of target state to be programmed
99e6a4d2	226	*
badc303a JP	227	* This function checks for any pending activity and then programs
badc303a JP	228	* the device to the specified or a safer state.
99e6a4d2 RN	229	*/
99e6a4d2 RN	230	static int omap3_enter_idle_bm(struct cpuidle_device *dev,
13d65c89	231	struct cpuidle_driver *drv,
e978aa7d	232	int index)
99e6a4d2	233	{
fd6b42a5 PW	234	int new_state_idx, ret;
fd6b42a5 PW	235	u8 per_next_state, per_saved_state;
badc303a	236	struct omap3_idle_statedata *cx;
0f724ed9	237
e7410cf7	238	/*
13d65c89	239	* Use only C1 if CAM is active.
e7410cf7 KH	240	* CAM does not have wakeup capability in OMAP3.
e7410cf7 KH	241	*/
13d65c89	242	if (pwrdm_read_pwrst(cam_pd) == PWRDM_POWER_ON)
46bcfad7	243	new_state_idx = drv->safe_state_index;
13d65c89 JP	244	else
13d65c89 JP	245	new_state_idx = next_valid_state(dev, drv, index);
e7410cf7	246
c6cd91de JP	247	/*
	248	* FIXME: we currently manage device-specific idle states
	249	* for PER and CORE in combination with CPU-specific
	250	* idle states. This is wrong, and device-specific
	251	* idle management needs to be separated out into
	252	* its own code.
	253	*/
	254
13d65c89 JP	255	/* Program PER state */
13d65c89 JP	256	cx = &omap3_idle_data[new_state_idx];
0f724ed9	257
fd6b42a5 PW	258	per_next_state = pwrdm_read_next_pwrst(per_pd);
	259	per_saved_state = per_next_state;
	260	if (per_next_state < cx->per_min_state) {
	261	per_next_state = cx->per_min_state;
e7410cf7	262	pwrdm_set_next_pwrst(per_pd, per_next_state);
fd6b42a5	263	}
e7410cf7	264
46bcfad7	265	ret = omap3_enter_idle(dev, drv, new_state_idx);
e7410cf7 KH	266
	267	/* Restore original PER state if it was modified */
	268	if (per_next_state != per_saved_state)
	269	pwrdm_set_next_pwrst(per_pd, per_saved_state);
	270
	271	return ret;
99e6a4d2 RN	272	}
99e6a4d2 RN	273
9db316b6	274	static DEFINE_PER_CPU(struct cpuidle_device, omap3_idle_dev);
99e6a4d2	275
9db316b6 PW	276	static struct cpuidle_driver omap3_idle_driver = {
	277	.name = "omap3_idle",
	278	.owner = THIS_MODULE,
200dd520 DL	279	.states = {
200dd520 DL	280	{
13d65c89	281	.enter = omap3_enter_idle_bm,
200dd520 DL	282	.exit_latency = 2 + 2,
	283	.target_residency = 5,
	284	.flags = CPUIDLE_FLAG_TIME_VALID,
	285	.name = "C1",
	286	.desc = "MPU ON + CORE ON",
	287	},
	288	{
	289	.enter = omap3_enter_idle_bm,
	290	.exit_latency = 10 + 10,
	291	.target_residency = 30,
	292	.flags = CPUIDLE_FLAG_TIME_VALID,
	293	.name = "C2",
	294	.desc = "MPU ON + CORE ON",
	295	},
	296	{
	297	.enter = omap3_enter_idle_bm,
	298	.exit_latency = 50 + 50,
	299	.target_residency = 300,
	300	.flags = CPUIDLE_FLAG_TIME_VALID,
	301	.name = "C3",
	302	.desc = "MPU RET + CORE ON",
	303	},
	304	{
	305	.enter = omap3_enter_idle_bm,
	306	.exit_latency = 1500 + 1800,
	307	.target_residency = 4000,
	308	.flags = CPUIDLE_FLAG_TIME_VALID,
	309	.name = "C4",
	310	.desc = "MPU OFF + CORE ON",
	311	},
	312	{
	313	.enter = omap3_enter_idle_bm,
	314	.exit_latency = 2500 + 7500,
	315	.target_residency = 12000,
	316	.flags = CPUIDLE_FLAG_TIME_VALID,
	317	.name = "C5",
	318	.desc = "MPU RET + CORE RET",
	319	},
	320	{
	321	.enter = omap3_enter_idle_bm,
	322	.exit_latency = 3000 + 8500,
	323	.target_residency = 15000,
	324	.flags = CPUIDLE_FLAG_TIME_VALID,
	325	.name = "C6",
	326	.desc = "MPU OFF + CORE RET",
	327	},
	328	{
	329	.enter = omap3_enter_idle_bm,
	330	.exit_latency = 10000 + 30000,
	331	.target_residency = 30000,
	332	.flags = CPUIDLE_FLAG_TIME_VALID,
	333	.name = "C7",
	334	.desc = "MPU OFF + CORE OFF",
	335	},
	336	},
88c377dd	337	.state_count = ARRAY_SIZE(omap3_idle_data),
200dd520	338	.safe_state_index = 0,
99e6a4d2 RN	339	};
99e6a4d2 RN	340
9db316b6 PW	341	/* Public functions */
9db316b6 PW	342
99e6a4d2 RN	343	/**
	344	* omap3_idle_init - Init routine for OMAP3 idle
	345	*
badc303a	346	* Registers the OMAP3 specific cpuidle driver to the cpuidle
99e6a4d2 RN	347	* framework with the valid set of states.
99e6a4d2 RN	348	*/
0343371e	349	int __init omap3_idle_init(void)
99e6a4d2	350	{
99e6a4d2 RN	351	struct cpuidle_device *dev;
	352
	353	mpu_pd = pwrdm_lookup("mpu_pwrdm");
20b01669	354	core_pd = pwrdm_lookup("core_pwrdm");
e7410cf7 KH	355	per_pd = pwrdm_lookup("per_pwrdm");
e7410cf7 KH	356	cam_pd = pwrdm_lookup("cam_pwrdm");
99e6a4d2	357
daa37cee DL	358	if (!mpu_pd \|\| !core_pd \|\| !per_pd \|\| !cam_pd)
	359	return -ENODEV;
	360
6622ac55	361	cpuidle_register_driver(&omap3_idle_driver);
46bcfad7	362
99e6a4d2	363	dev = &per_cpu(omap3_idle_dev, smp_processor_id());
6622ac55	364	dev->cpu = 0;
46bcfad7	365
99e6a4d2 RN	366	if (cpuidle_register_device(dev)) {
	367	printk(KERN_ERR "%s: CPUidle register device failed\n",
	368	__func__);
	369	return -EIO;
	370	}
	371
	372	return 0;
	373	}