[deliverable/linux.git] / arch / arm / mach-omap2 / cpuidle34xx.c

/*
 * linux/arch/arm/mach-omap2/cpuidle34xx.c
 *
 * OMAP3 CPU IDLE Routines
 *
 * Copyright (C) 2008 Texas Instruments, Inc.
 * Rajendra Nayak <rnayak@ti.com>
 *
 * Copyright (C) 2007 Texas Instruments, Inc.
 * Karthik Dasu <karthik-dp@ti.com>
 *
 * Copyright (C) 2006 Nokia Corporation
 * Tony Lindgren <tony@atomide.com>
 *
 * Copyright (C) 2005 Texas Instruments, Inc.
 * Richard Woodruff <r-woodruff2@ti.com>
 *
 * Based on pm.c for omap2
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/sched.h>
#include <linux/cpuidle.h>
#include <linux/export.h>
#include <linux/cpu_pm.h>

#include <plat/prcm.h>
#include "powerdomain.h"
#include "clockdomain.h"

#include "pm.h"
#include "control.h"
#include "common.h"

/* Mach specific information to be recorded in the C-state driver_data */
struct omap3_idle_statedata {
	u32 mpu_state;
	u32 core_state;
};

static struct omap3_idle_statedata omap3_idle_data[] = {
	{
		.mpu_state = PWRDM_POWER_ON,
		.core_state = PWRDM_POWER_ON,
	},
	{
		.mpu_state = PWRDM_POWER_ON,
		.core_state = PWRDM_POWER_ON,
	},
	{
		.mpu_state = PWRDM_POWER_RET,
		.core_state = PWRDM_POWER_ON,
	},
	{
		.mpu_state = PWRDM_POWER_OFF,
		.core_state = PWRDM_POWER_ON,
	},
	{
		.mpu_state = PWRDM_POWER_RET,
		.core_state = PWRDM_POWER_RET,
	},
	{
		.mpu_state = PWRDM_POWER_OFF,
		.core_state = PWRDM_POWER_RET,
	},
	{
		.mpu_state = PWRDM_POWER_OFF,
		.core_state = PWRDM_POWER_OFF,
	},
};

static struct powerdomain *mpu_pd, *core_pd, *per_pd, *cam_pd;

static int __omap3_enter_idle(struct cpuidle_device *dev,
				struct cpuidle_driver *drv,
				int index)
{
	struct omap3_idle_statedata *cx = &omap3_idle_data[index];
	u32 mpu_state = cx->mpu_state, core_state = cx->core_state;

	local_fiq_disable();

	pwrdm_set_next_pwrst(mpu_pd, mpu_state);
	pwrdm_set_next_pwrst(core_pd, core_state);

	if (omap_irq_pending() || need_resched())
		goto return_sleep_time;

	/* Deny idle for C1 */
	if (index == 0) {
		clkdm_deny_idle(mpu_pd->pwrdm_clkdms[0]);
		clkdm_deny_idle(core_pd->pwrdm_clkdms[0]);
	}

	/*
	 * Call idle CPU PM enter notifier chain so that
	 * VFP context is saved.
	 */
	if (mpu_state == PWRDM_POWER_OFF)
		cpu_pm_enter();

	/* Execute ARM wfi */
	omap_sram_idle();

	/*
	 * Call idle CPU PM enter notifier chain to restore
	 * VFP context.
	 */
	if (pwrdm_read_prev_pwrst(mpu_pd) == PWRDM_POWER_OFF)
		cpu_pm_exit();

	/* Re-allow idle for C1 */
	if (index == 0) {
		clkdm_allow_idle(mpu_pd->pwrdm_clkdms[0]);
		clkdm_allow_idle(core_pd->pwrdm_clkdms[0]);
	}

return_sleep_time:

	local_fiq_enable();

	return index;
}

/**
 * omap3_enter_idle - Programs OMAP3 to enter the specified state
 * @dev: cpuidle device
 * @drv: cpuidle driver
 * @index: the index of state to be entered
 *
 * Called from the CPUidle framework to program the device to the
 * specified target state selected by the governor.
 */
static inline int omap3_enter_idle(struct cpuidle_device *dev,
				struct cpuidle_driver *drv,
				int index)
{
	return cpuidle_wrap_enter(dev, drv, index, __omap3_enter_idle);
}

/**
 * next_valid_state - Find next valid C-state
 * @dev: cpuidle device
 * @drv: cpuidle driver
 * @index: Index of currently selected c-state
 *
 * If the state corresponding to index is valid, index is returned back
 * to the caller. Else, this function searches for a lower c-state which is
 * still valid (as defined in omap3_power_states[]) and returns its index.
 *
 * A state is valid if the 'valid' field is enabled and
 * if it satisfies the enable_off_mode condition.
 */
static int next_valid_state(struct cpuidle_device *dev,
			    struct cpuidle_driver *drv, int index)
{
	struct omap3_idle_statedata *cx = &omap3_idle_data[index];
	u32 mpu_deepest_state = PWRDM_POWER_RET;
	u32 core_deepest_state = PWRDM_POWER_RET;
	int idx;
	int next_index = 0; /* C1 is the default value */

	if (enable_off_mode) {
		mpu_deepest_state = PWRDM_POWER_OFF;
		/*
		 * Erratum i583: valable for ES rev < Es1.2 on 3630.
		 * CORE OFF mode is not supported in a stable form, restrict
		 * instead the CORE state to RET.
		 */
		if (!IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583))
			core_deepest_state = PWRDM_POWER_OFF;
	}

	/* Check if current state is valid */
	if ((cx->mpu_state >= mpu_deepest_state) &&
	    (cx->core_state >= core_deepest_state))
		return index;

	/*
	 * Drop to next valid state.
	 * Start search from the next (lower) state.
	 */
	for (idx = index - 1; idx >= 0; idx--) {
		cx =  &omap3_idle_data[idx];
		if ((cx->mpu_state >= mpu_deepest_state) &&
		    (cx->core_state >= core_deepest_state)) {
			next_index = idx;
			break;
		}
	}

	return next_index;
}

/**
 * omap3_enter_idle_bm - Checks for any bus activity
 * @dev: cpuidle device
 * @drv: cpuidle driver
 * @index: array index of target state to be programmed
 *
 * This function checks for any pending activity and then programs
 * the device to the specified or a safer state.
 */
static int omap3_enter_idle_bm(struct cpuidle_device *dev,
			       struct cpuidle_driver *drv,
			       int index)
{
	int new_state_idx;
	u32 core_next_state, per_next_state = 0, per_saved_state = 0;
	struct omap3_idle_statedata *cx;
	int ret;

	/*
	 * Use only C1 if CAM is active.
	 * CAM does not have wakeup capability in OMAP3.
	 */
	if (pwrdm_read_pwrst(cam_pd) == PWRDM_POWER_ON)
		new_state_idx = drv->safe_state_index;
	else
		new_state_idx = next_valid_state(dev, drv, index);

	/*
	 * FIXME: we currently manage device-specific idle states
	 *        for PER and CORE in combination with CPU-specific
	 *        idle states.  This is wrong, and device-specific
	 *        idle management needs to be separated out into
	 *        its own code.
	 */

	/* Program PER state */
	cx = &omap3_idle_data[new_state_idx];
	core_next_state = cx->core_state;
	per_next_state = per_saved_state = pwrdm_read_next_pwrst(per_pd);
	if (new_state_idx == 0) {
		/* In C1 do not allow PER state lower than CORE state */
		if (per_next_state < core_next_state)
			per_next_state = core_next_state;
	} else {
		/*
		 * Prevent PER OFF if CORE is not in RETention or OFF as this
		 * would disable PER wakeups completely.
		 */
		if ((per_next_state == PWRDM_POWER_OFF) &&
		    (core_next_state > PWRDM_POWER_RET))
			per_next_state = PWRDM_POWER_RET;
	}

	/* Are we changing PER target state? */
	if (per_next_state != per_saved_state)
		pwrdm_set_next_pwrst(per_pd, per_next_state);

	ret = omap3_enter_idle(dev, drv, new_state_idx);

	/* Restore original PER state if it was modified */
	if (per_next_state != per_saved_state)
		pwrdm_set_next_pwrst(per_pd, per_saved_state);

	return ret;
}

DEFINE_PER_CPU(struct cpuidle_device, omap3_idle_dev);

struct cpuidle_driver omap3_idle_driver = {
	.name = 	"omap3_idle",
	.owner = 	THIS_MODULE,
	.states = {
		{
			.enter		  = omap3_enter_idle_bm,
			.exit_latency	  = 2 + 2,
			.target_residency = 5,
			.flags		  = CPUIDLE_FLAG_TIME_VALID,
			.name		  = "C1",
			.desc		  = "MPU ON + CORE ON",
		},
		{
			.enter		  = omap3_enter_idle_bm,
			.exit_latency	  = 10 + 10,
			.target_residency = 30,
			.flags		  = CPUIDLE_FLAG_TIME_VALID,
			.name		  = "C2",
			.desc		  = "MPU ON + CORE ON",
		},
		{
			.enter		  = omap3_enter_idle_bm,
			.exit_latency	  = 50 + 50,
			.target_residency = 300,
			.flags		  = CPUIDLE_FLAG_TIME_VALID,
			.name		  = "C3",
			.desc		  = "MPU RET + CORE ON",
		},
		{
			.enter		  = omap3_enter_idle_bm,
			.exit_latency	  = 1500 + 1800,
			.target_residency = 4000,
			.flags		  = CPUIDLE_FLAG_TIME_VALID,
			.name		  = "C4",
			.desc		  = "MPU OFF + CORE ON",
		},
		{
			.enter		  = omap3_enter_idle_bm,
			.exit_latency	  = 2500 + 7500,
			.target_residency = 12000,
			.flags		  = CPUIDLE_FLAG_TIME_VALID,
			.name		  = "C5",
			.desc		  = "MPU RET + CORE RET",
		},
		{
			.enter		  = omap3_enter_idle_bm,
			.exit_latency	  = 3000 + 8500,
			.target_residency = 15000,
			.flags		  = CPUIDLE_FLAG_TIME_VALID,
			.name		  = "C6",
			.desc		  = "MPU OFF + CORE RET",
		},
		{
			.enter		  = omap3_enter_idle_bm,
			.exit_latency	  = 10000 + 30000,
			.target_residency = 30000,
			.flags		  = CPUIDLE_FLAG_TIME_VALID,
			.name		  = "C7",
			.desc		  = "MPU OFF + CORE OFF",
		},
	},
	.state_count = ARRAY_SIZE(omap3_idle_data),
	.safe_state_index = 0,
};

/**
 * omap3_idle_init - Init routine for OMAP3 idle
 *
 * Registers the OMAP3 specific cpuidle driver to the cpuidle
 * framework with the valid set of states.
 */
int __init omap3_idle_init(void)
{
	struct cpuidle_device *dev;

	mpu_pd = pwrdm_lookup("mpu_pwrdm");
	core_pd = pwrdm_lookup("core_pwrdm");
	per_pd = pwrdm_lookup("per_pwrdm");
	cam_pd = pwrdm_lookup("cam_pwrdm");

	if (!mpu_pd || !core_pd || !per_pd || !cam_pd)
		return -ENODEV;

	cpuidle_register_driver(&omap3_idle_driver);

	dev = &per_cpu(omap3_idle_dev, smp_processor_id());
	dev->cpu = 0;

	if (cpuidle_register_device(dev)) {
		printk(KERN_ERR "%s: CPUidle register device failed\n",
		       __func__);
		return -EIO;
	}

	return 0;
}
Commit	Line	Data
99e6a4d2 RN	1	/*
	2	* linux/arch/arm/mach-omap2/cpuidle34xx.c
	3	*
	4	* OMAP3 CPU IDLE Routines
	5	*
	6	* Copyright (C) 2008 Texas Instruments, Inc.
	7	* Rajendra Nayak <rnayak@ti.com>
	8	*
	9	* Copyright (C) 2007 Texas Instruments, Inc.
	10	* Karthik Dasu <karthik-dp@ti.com>
	11	*
	12	* Copyright (C) 2006 Nokia Corporation
	13	* Tony Lindgren <tony@atomide.com>
	14	*
	15	* Copyright (C) 2005 Texas Instruments, Inc.
	16	* Richard Woodruff <r-woodruff2@ti.com>
	17	*
	18	* Based on pm.c for omap2
	19	*
	20	* This program is free software; you can redistribute it and/or modify
	21	* it under the terms of the GNU General Public License version 2 as
	22	* published by the Free Software Foundation.
	23	*/
	24
cf22854c	25	#include <linux/sched.h>
99e6a4d2	26	#include <linux/cpuidle.h>
5698eb4e	27	#include <linux/export.h>
ff819da4	28	#include <linux/cpu_pm.h>
99e6a4d2 RN	29
99e6a4d2 RN	30	#include <plat/prcm.h>
72e06d08	31	#include "powerdomain.h"
1540f214	32	#include "clockdomain.h"
99e6a4d2	33
c98e2230	34	#include "pm.h"
4814ced5	35	#include "control.h"
ba8bb18a	36	#include "common.h"
c98e2230	37
badc303a JP	38	/* Mach specific information to be recorded in the C-state driver_data */
	39	struct omap3_idle_statedata {
	40	u32 mpu_state;
	41	u32 core_state;
badc303a	42	};
0c2487f6	43
97abc496	44	static struct omap3_idle_statedata omap3_idle_data[] = {
88c377dd DL	45	{
	46	.mpu_state = PWRDM_POWER_ON,
	47	.core_state = PWRDM_POWER_ON,
	48	},
	49	{
	50	.mpu_state = PWRDM_POWER_ON,
	51	.core_state = PWRDM_POWER_ON,
	52	},
	53	{
	54	.mpu_state = PWRDM_POWER_RET,
	55	.core_state = PWRDM_POWER_ON,
	56	},
	57	{
	58	.mpu_state = PWRDM_POWER_OFF,
	59	.core_state = PWRDM_POWER_ON,
	60	},
	61	{
	62	.mpu_state = PWRDM_POWER_RET,
	63	.core_state = PWRDM_POWER_RET,
	64	},
	65	{
	66	.mpu_state = PWRDM_POWER_OFF,
	67	.core_state = PWRDM_POWER_RET,
	68	},
	69	{
	70	.mpu_state = PWRDM_POWER_OFF,
	71	.core_state = PWRDM_POWER_OFF,
	72	},
	73	};
badc303a	74
34fd57bf	75	static struct powerdomain mpu_pd, core_pd, per_pd, cam_pd;
bb4de3df	76
6da45dce	77	static int __omap3_enter_idle(struct cpuidle_device *dev,
46bcfad7	78	struct cpuidle_driver *drv,
e978aa7d	79	int index)
99e6a4d2	80	{
6622ac55	81	struct omap3_idle_statedata *cx = &omap3_idle_data[index];
c98e2230	82	u32 mpu_state = cx->mpu_state, core_state = cx->core_state;
99e6a4d2	83
99e6a4d2 RN	84	local_fiq_disable();
99e6a4d2 RN	85
7139178e JH	86	pwrdm_set_next_pwrst(mpu_pd, mpu_state);
7139178e JH	87	pwrdm_set_next_pwrst(core_pd, core_state);
20b01669	88
cf22854c	89	if (omap_irq_pending() \|\| need_resched())
20b01669	90	goto return_sleep_time;
99e6a4d2	91
badc303a	92	/* Deny idle for C1 */
e978aa7d	93	if (index == 0) {
05011f71 JP	94	clkdm_deny_idle(mpu_pd->pwrdm_clkdms[0]);
05011f71 JP	95	clkdm_deny_idle(core_pd->pwrdm_clkdms[0]);
06d8f065 PDS	96	}
06d8f065 PDS	97
ff819da4 SS	98	/*
	99	* Call idle CPU PM enter notifier chain so that
	100	* VFP context is saved.
	101	*/
	102	if (mpu_state == PWRDM_POWER_OFF)
	103	cpu_pm_enter();
	104
99e6a4d2 RN	105	/* Execute ARM wfi */
	106	omap_sram_idle();
	107
ff819da4 SS	108	/*
	109	* Call idle CPU PM enter notifier chain to restore
	110	* VFP context.
	111	*/
	112	if (pwrdm_read_prev_pwrst(mpu_pd) == PWRDM_POWER_OFF)
	113	cpu_pm_exit();
	114
badc303a	115	/* Re-allow idle for C1 */
e978aa7d	116	if (index == 0) {
05011f71 JP	117	clkdm_allow_idle(mpu_pd->pwrdm_clkdms[0]);
05011f71 JP	118	clkdm_allow_idle(core_pd->pwrdm_clkdms[0]);
06d8f065 PDS	119	}
06d8f065 PDS	120
20b01669	121	return_sleep_time:
99e6a4d2	122
99e6a4d2 RN	123	local_fiq_enable();
99e6a4d2 RN	124
e978aa7d	125	return index;
99e6a4d2 RN	126	}
99e6a4d2 RN	127
6da45dce RL	128	/**
	129	* omap3_enter_idle - Programs OMAP3 to enter the specified state
	130	* @dev: cpuidle device
	131	* @drv: cpuidle driver
	132	* @index: the index of state to be entered
	133	*
	134	* Called from the CPUidle framework to program the device to the
	135	* specified target state selected by the governor.
	136	*/
	137	static inline int omap3_enter_idle(struct cpuidle_device *dev,
	138	struct cpuidle_driver *drv,
	139	int index)
	140	{
	141	return cpuidle_wrap_enter(dev, drv, index, __omap3_enter_idle);
	142	}
	143
6af83b38	144	/**
04908918	145	* next_valid_state - Find next valid C-state
6af83b38	146	* @dev: cpuidle device
46bcfad7	147	* @drv: cpuidle driver
e978aa7d	148	* @index: Index of currently selected c-state
6af83b38	149	*
e978aa7d DD	150	* If the state corresponding to index is valid, index is returned back
	151	* to the caller. Else, this function searches for a lower c-state which is
	152	* still valid (as defined in omap3_power_states[]) and returns its index.
04908918 JP	153	*
	154	* A state is valid if the 'valid' field is enabled and
	155	* if it satisfies the enable_off_mode condition.
6af83b38	156	*/
e978aa7d	157	static int next_valid_state(struct cpuidle_device *dev,
e92a4586	158	struct cpuidle_driver *drv, int index)
6af83b38	159	{
6622ac55	160	struct omap3_idle_statedata *cx = &omap3_idle_data[index];
04908918 JP	161	u32 mpu_deepest_state = PWRDM_POWER_RET;
04908918 JP	162	u32 core_deepest_state = PWRDM_POWER_RET;
e92a4586	163	int idx;
063a5d01	164	int next_index = 0; /* C1 is the default value */
04908918 JP	165
	166	if (enable_off_mode) {
	167	mpu_deepest_state = PWRDM_POWER_OFF;
	168	/*
	169	* Erratum i583: valable for ES rev < Es1.2 on 3630.
	170	* CORE OFF mode is not supported in a stable form, restrict
	171	* instead the CORE state to RET.
	172	*/
	173	if (!IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583))
	174	core_deepest_state = PWRDM_POWER_OFF;
	175	}
6af83b38 SP	176
6af83b38 SP	177	/* Check if current state is valid */
f79b5d8a	178	if ((cx->mpu_state >= mpu_deepest_state) &&
e92a4586	179	(cx->core_state >= core_deepest_state))
e978aa7d	180	return index;
6af83b38	181
e92a4586 DL	182	/*
	183	* Drop to next valid state.
	184	* Start search from the next (lower) state.
	185	*/
	186	for (idx = index - 1; idx >= 0; idx--) {
	187	cx = &omap3_idle_data[idx];
	188	if ((cx->mpu_state >= mpu_deepest_state) &&
	189	(cx->core_state >= core_deepest_state)) {
	190	next_index = idx;
	191	break;
6af83b38	192	}
6af83b38 SP	193	}
6af83b38 SP	194
e978aa7d	195	return next_index;
6af83b38 SP	196	}
6af83b38 SP	197
99e6a4d2 RN	198	/**
	199	* omap3_enter_idle_bm - Checks for any bus activity
	200	* @dev: cpuidle device
46bcfad7	201	* @drv: cpuidle driver
e978aa7d	202	* @index: array index of target state to be programmed
99e6a4d2	203	*
badc303a JP	204	* This function checks for any pending activity and then programs
badc303a JP	205	* the device to the specified or a safer state.
99e6a4d2 RN	206	*/
99e6a4d2 RN	207	static int omap3_enter_idle_bm(struct cpuidle_device *dev,
13d65c89	208	struct cpuidle_driver *drv,
e978aa7d	209	int index)
99e6a4d2	210	{
e978aa7d	211	int new_state_idx;
13d65c89	212	u32 core_next_state, per_next_state = 0, per_saved_state = 0;
badc303a	213	struct omap3_idle_statedata *cx;
e7410cf7	214	int ret;
0f724ed9	215
e7410cf7	216	/*
13d65c89	217	* Use only C1 if CAM is active.
e7410cf7 KH	218	* CAM does not have wakeup capability in OMAP3.
e7410cf7 KH	219	*/
13d65c89	220	if (pwrdm_read_pwrst(cam_pd) == PWRDM_POWER_ON)
46bcfad7	221	new_state_idx = drv->safe_state_index;
13d65c89 JP	222	else
13d65c89 JP	223	new_state_idx = next_valid_state(dev, drv, index);
e7410cf7	224
c6cd91de JP	225	/*
	226	* FIXME: we currently manage device-specific idle states
	227	* for PER and CORE in combination with CPU-specific
	228	* idle states. This is wrong, and device-specific
	229	* idle management needs to be separated out into
	230	* its own code.
	231	*/
	232
13d65c89 JP	233	/* Program PER state */
13d65c89 JP	234	cx = &omap3_idle_data[new_state_idx];
c6cd91de	235	core_next_state = cx->core_state;
e7410cf7	236	per_next_state = per_saved_state = pwrdm_read_next_pwrst(per_pd);
13d65c89 JP	237	if (new_state_idx == 0) {
	238	/* In C1 do not allow PER state lower than CORE state */
	239	if (per_next_state < core_next_state)
	240	per_next_state = core_next_state;
	241	} else {
	242	/*
	243	* Prevent PER OFF if CORE is not in RETention or OFF as this
	244	* would disable PER wakeups completely.
	245	*/
	246	if ((per_next_state == PWRDM_POWER_OFF) &&
	247	(core_next_state > PWRDM_POWER_RET))
	248	per_next_state = PWRDM_POWER_RET;
	249	}
0f724ed9	250
e7410cf7 KH	251	/* Are we changing PER target state? */
	252	if (per_next_state != per_saved_state)
	253	pwrdm_set_next_pwrst(per_pd, per_next_state);
	254
46bcfad7	255	ret = omap3_enter_idle(dev, drv, new_state_idx);
e7410cf7 KH	256
	257	/* Restore original PER state if it was modified */
	258	if (per_next_state != per_saved_state)
	259	pwrdm_set_next_pwrst(per_pd, per_saved_state);
	260
	261	return ret;
99e6a4d2 RN	262	}
	263
	264	DEFINE_PER_CPU(struct cpuidle_device, omap3_idle_dev);
	265
99e6a4d2 RN	266	struct cpuidle_driver omap3_idle_driver = {
	267	.name = "omap3_idle",
	268	.owner = THIS_MODULE,
200dd520 DL	269	.states = {
200dd520 DL	270	{
13d65c89	271	.enter = omap3_enter_idle_bm,
200dd520 DL	272	.exit_latency = 2 + 2,
	273	.target_residency = 5,
	274	.flags = CPUIDLE_FLAG_TIME_VALID,
	275	.name = "C1",
	276	.desc = "MPU ON + CORE ON",
	277	},
	278	{
	279	.enter = omap3_enter_idle_bm,
	280	.exit_latency = 10 + 10,
	281	.target_residency = 30,
	282	.flags = CPUIDLE_FLAG_TIME_VALID,
	283	.name = "C2",
	284	.desc = "MPU ON + CORE ON",
	285	},
	286	{
	287	.enter = omap3_enter_idle_bm,
	288	.exit_latency = 50 + 50,
	289	.target_residency = 300,
	290	.flags = CPUIDLE_FLAG_TIME_VALID,
	291	.name = "C3",
	292	.desc = "MPU RET + CORE ON",
	293	},
	294	{
	295	.enter = omap3_enter_idle_bm,
	296	.exit_latency = 1500 + 1800,
	297	.target_residency = 4000,
	298	.flags = CPUIDLE_FLAG_TIME_VALID,
	299	.name = "C4",
	300	.desc = "MPU OFF + CORE ON",
	301	},
	302	{
	303	.enter = omap3_enter_idle_bm,
	304	.exit_latency = 2500 + 7500,
	305	.target_residency = 12000,
	306	.flags = CPUIDLE_FLAG_TIME_VALID,
	307	.name = "C5",
	308	.desc = "MPU RET + CORE RET",
	309	},
	310	{
	311	.enter = omap3_enter_idle_bm,
	312	.exit_latency = 3000 + 8500,
	313	.target_residency = 15000,
	314	.flags = CPUIDLE_FLAG_TIME_VALID,
	315	.name = "C6",
	316	.desc = "MPU OFF + CORE RET",
	317	},
	318	{
	319	.enter = omap3_enter_idle_bm,
	320	.exit_latency = 10000 + 30000,
	321	.target_residency = 30000,
	322	.flags = CPUIDLE_FLAG_TIME_VALID,
	323	.name = "C7",
	324	.desc = "MPU OFF + CORE OFF",
	325	},
	326	},
88c377dd	327	.state_count = ARRAY_SIZE(omap3_idle_data),
200dd520	328	.safe_state_index = 0,
99e6a4d2 RN	329	};
	330
	331	/**
	332	* omap3_idle_init - Init routine for OMAP3 idle
	333	*
badc303a	334	* Registers the OMAP3 specific cpuidle driver to the cpuidle
99e6a4d2 RN	335	* framework with the valid set of states.
99e6a4d2 RN	336	*/
0343371e	337	int __init omap3_idle_init(void)
99e6a4d2	338	{
99e6a4d2 RN	339	struct cpuidle_device *dev;
	340
	341	mpu_pd = pwrdm_lookup("mpu_pwrdm");
20b01669	342	core_pd = pwrdm_lookup("core_pwrdm");
e7410cf7 KH	343	per_pd = pwrdm_lookup("per_pwrdm");
e7410cf7 KH	344	cam_pd = pwrdm_lookup("cam_pwrdm");
99e6a4d2	345
daa37cee DL	346	if (!mpu_pd \|\| !core_pd \|\| !per_pd \|\| !cam_pd)
	347	return -ENODEV;
	348
6622ac55	349	cpuidle_register_driver(&omap3_idle_driver);
46bcfad7	350
99e6a4d2	351	dev = &per_cpu(omap3_idle_dev, smp_processor_id());
6622ac55	352	dev->cpu = 0;
46bcfad7	353
99e6a4d2 RN	354	if (cpuidle_register_device(dev)) {
	355	printk(KERN_ERR "%s: CPUidle register device failed\n",
	356	__func__);
	357	return -EIO;
	358	}
	359
	360	return 0;
	361	}