[deliverable/linux.git] / arch / arm / mach-omap2 / cpuidle34xx.c

/*
 * linux/arch/arm/mach-omap2/cpuidle34xx.c
 *
 * OMAP3 CPU IDLE Routines
 *
 * Copyright (C) 2008 Texas Instruments, Inc.
 * Rajendra Nayak <rnayak@ti.com>
 *
 * Copyright (C) 2007 Texas Instruments, Inc.
 * Karthik Dasu <karthik-dp@ti.com>
 *
 * Copyright (C) 2006 Nokia Corporation
 * Tony Lindgren <tony@atomide.com>
 *
 * Copyright (C) 2005 Texas Instruments, Inc.
 * Richard Woodruff <r-woodruff2@ti.com>
 *
 * Based on pm.c for omap2
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/sched.h>
#include <linux/cpuidle.h>
#include <linux/export.h>
#include <linux/cpu_pm.h>

#include <plat/prcm.h>
#include <plat/irqs.h>
#include "powerdomain.h"
#include "clockdomain.h"

#include "pm.h"
#include "control.h"
#include "common.h"

#ifdef CONFIG_CPU_IDLE

/* Mach specific information to be recorded in the C-state driver_data */
struct omap3_idle_statedata {
	u32 mpu_state;
	u32 core_state;
};

#define OMAP3_NUM_STATES 7

struct omap3_idle_statedata omap3_idle_data[OMAP3_NUM_STATES];

struct powerdomain *mpu_pd, *core_pd, *per_pd, *cam_pd;

static int _cpuidle_allow_idle(struct powerdomain *pwrdm,
				struct clockdomain *clkdm)
{
	clkdm_allow_idle(clkdm);
	return 0;
}

static int _cpuidle_deny_idle(struct powerdomain *pwrdm,
				struct clockdomain *clkdm)
{
	clkdm_deny_idle(clkdm);
	return 0;
}

static int __omap3_enter_idle(struct cpuidle_device *dev,
				struct cpuidle_driver *drv,
				int index)
{
	struct omap3_idle_statedata *cx =
			cpuidle_get_statedata(&dev->states_usage[index]);
	u32 mpu_state = cx->mpu_state, core_state = cx->core_state;

	local_fiq_disable();

	pwrdm_set_next_pwrst(mpu_pd, mpu_state);
	pwrdm_set_next_pwrst(core_pd, core_state);

	if (omap_irq_pending() || need_resched())
		goto return_sleep_time;

	/* Deny idle for C1 */
	if (index == 0) {
		pwrdm_for_each_clkdm(mpu_pd, _cpuidle_deny_idle);
		pwrdm_for_each_clkdm(core_pd, _cpuidle_deny_idle);
	}

	/*
	 * Call idle CPU PM enter notifier chain so that
	 * VFP context is saved.
	 */
	if (mpu_state == PWRDM_POWER_OFF)
		cpu_pm_enter();

	/* Execute ARM wfi */
	omap_sram_idle();

	/*
	 * Call idle CPU PM enter notifier chain to restore
	 * VFP context.
	 */
	if (pwrdm_read_prev_pwrst(mpu_pd) == PWRDM_POWER_OFF)
		cpu_pm_exit();

	/* Re-allow idle for C1 */
	if (index == 0) {
		pwrdm_for_each_clkdm(mpu_pd, _cpuidle_allow_idle);
		pwrdm_for_each_clkdm(core_pd, _cpuidle_allow_idle);
	}

return_sleep_time:

	local_fiq_enable();

	return index;
}

/**
 * omap3_enter_idle - Programs OMAP3 to enter the specified state
 * @dev: cpuidle device
 * @drv: cpuidle driver
 * @index: the index of state to be entered
 *
 * Called from the CPUidle framework to program the device to the
 * specified target state selected by the governor.
 */
static inline int omap3_enter_idle(struct cpuidle_device *dev,
				struct cpuidle_driver *drv,
				int index)
{
	return cpuidle_wrap_enter(dev, drv, index, __omap3_enter_idle);
}

/**
 * next_valid_state - Find next valid C-state
 * @dev: cpuidle device
 * @drv: cpuidle driver
 * @index: Index of currently selected c-state
 *
 * If the state corresponding to index is valid, index is returned back
 * to the caller. Else, this function searches for a lower c-state which is
 * still valid (as defined in omap3_power_states[]) and returns its index.
 *
 * A state is valid if the 'valid' field is enabled and
 * if it satisfies the enable_off_mode condition.
 */
static int next_valid_state(struct cpuidle_device *dev,
			struct cpuidle_driver *drv,
				int index)
{
	struct cpuidle_state_usage *curr_usage = &dev->states_usage[index];
	struct cpuidle_state *curr = &drv->states[index];
	struct omap3_idle_statedata *cx = cpuidle_get_statedata(curr_usage);
	u32 mpu_deepest_state = PWRDM_POWER_RET;
	u32 core_deepest_state = PWRDM_POWER_RET;
	int next_index = -1;

	if (enable_off_mode) {
		mpu_deepest_state = PWRDM_POWER_OFF;
		/*
		 * Erratum i583: valable for ES rev < Es1.2 on 3630.
		 * CORE OFF mode is not supported in a stable form, restrict
		 * instead the CORE state to RET.
		 */
		if (!IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583))
			core_deepest_state = PWRDM_POWER_OFF;
	}

	/* Check if current state is valid */
	if ((cx->mpu_state >= mpu_deepest_state) &&
	    (cx->core_state >= core_deepest_state)) {
		return index;
	} else {
		int idx = OMAP3_NUM_STATES - 1;

		/* Reach the current state starting at highest C-state */
		for (; idx >= 0; idx--) {
			if (&drv->states[idx] == curr) {
				next_index = idx;
				break;
			}
		}

		/* Should never hit this condition */
		WARN_ON(next_index == -1);

		/*
		 * Drop to next valid state.
		 * Start search from the next (lower) state.
		 */
		idx--;
		for (; idx >= 0; idx--) {
			cx = cpuidle_get_statedata(&dev->states_usage[idx]);
			if ((cx->mpu_state >= mpu_deepest_state) &&
			    (cx->core_state >= core_deepest_state)) {
				next_index = idx;
				break;
			}
		}
		/*
		 * C1 is always valid.
		 * So, no need to check for 'next_index == -1' outside
		 * this loop.
		 */
	}

	return next_index;
}

/**
 * omap3_enter_idle_bm - Checks for any bus activity
 * @dev: cpuidle device
 * @drv: cpuidle driver
 * @index: array index of target state to be programmed
 *
 * This function checks for any pending activity and then programs
 * the device to the specified or a safer state.
 */
static int omap3_enter_idle_bm(struct cpuidle_device *dev,
				struct cpuidle_driver *drv,
			       int index)
{
	int new_state_idx;
	u32 core_next_state, per_next_state = 0, per_saved_state = 0, cam_state;
	struct omap3_idle_statedata *cx;
	int ret;

	/*
	 * Prevent idle completely if CAM is active.
	 * CAM does not have wakeup capability in OMAP3.
	 */
	cam_state = pwrdm_read_pwrst(cam_pd);
	if (cam_state == PWRDM_POWER_ON) {
		new_state_idx = drv->safe_state_index;
		goto select_state;
	}

	/*
	 * FIXME: we currently manage device-specific idle states
	 *        for PER and CORE in combination with CPU-specific
	 *        idle states.  This is wrong, and device-specific
	 *        idle management needs to be separated out into
	 *        its own code.
	 */

	/*
	 * Prevent PER off if CORE is not in retention or off as this
	 * would disable PER wakeups completely.
	 */
	cx = cpuidle_get_statedata(&dev->states_usage[index]);
	core_next_state = cx->core_state;
	per_next_state = per_saved_state = pwrdm_read_next_pwrst(per_pd);
	if ((per_next_state == PWRDM_POWER_OFF) &&
	    (core_next_state > PWRDM_POWER_RET))
		per_next_state = PWRDM_POWER_RET;

	/* Are we changing PER target state? */
	if (per_next_state != per_saved_state)
		pwrdm_set_next_pwrst(per_pd, per_next_state);

	new_state_idx = next_valid_state(dev, drv, index);

select_state:
	ret = omap3_enter_idle(dev, drv, new_state_idx);

	/* Restore original PER state if it was modified */
	if (per_next_state != per_saved_state)
		pwrdm_set_next_pwrst(per_pd, per_saved_state);

	return ret;
}

DEFINE_PER_CPU(struct cpuidle_device, omap3_idle_dev);

struct cpuidle_driver omap3_idle_driver = {
	.name = 	"omap3_idle",
	.owner = 	THIS_MODULE,
	.states = {
		{
			.enter		  = omap3_enter_idle,
			.exit_latency	  = 2 + 2,
			.target_residency = 5,
			.flags		  = CPUIDLE_FLAG_TIME_VALID,
			.name		  = "C1",
			.desc		  = "MPU ON + CORE ON",
		},
		{
			.enter		  = omap3_enter_idle_bm,
			.exit_latency	  = 10 + 10,
			.target_residency = 30,
			.flags		  = CPUIDLE_FLAG_TIME_VALID,
			.name		  = "C2",
			.desc		  = "MPU ON + CORE ON",
		},
		{
			.enter		  = omap3_enter_idle_bm,
			.exit_latency	  = 50 + 50,
			.target_residency = 300,
			.flags		  = CPUIDLE_FLAG_TIME_VALID,
			.name		  = "C3",
			.desc		  = "MPU RET + CORE ON",
		},
		{
			.enter		  = omap3_enter_idle_bm,
			.exit_latency	  = 1500 + 1800,
			.target_residency = 4000,
			.flags		  = CPUIDLE_FLAG_TIME_VALID,
			.name		  = "C4",
			.desc		  = "MPU OFF + CORE ON",
		},
		{
			.enter		  = omap3_enter_idle_bm,
			.exit_latency	  = 2500 + 7500,
			.target_residency = 12000,
			.flags		  = CPUIDLE_FLAG_TIME_VALID,
			.name		  = "C5",
			.desc		  = "MPU RET + CORE RET",
		},
		{
			.enter		  = omap3_enter_idle_bm,
			.exit_latency	  = 3000 + 8500,
			.target_residency = 15000,
			.flags		  = CPUIDLE_FLAG_TIME_VALID,
			.name		  = "C6",
			.desc		  = "MPU OFF + CORE RET",
		},
		{
			.enter		  = omap3_enter_idle_bm,
			.exit_latency	  = 10000 + 30000,
			.target_residency = 30000,
			.flags		  = CPUIDLE_FLAG_TIME_VALID,
			.name		  = "C7",
			.desc		  = "MPU OFF + CORE OFF",
		},
	},
	.state_count = OMAP3_NUM_STATES,
	.safe_state_index = 0,
};

/* Helper to register the driver_data */
static inline struct omap3_idle_statedata *_fill_cstate_usage(
					struct cpuidle_device *dev,
					int idx)
{
	struct omap3_idle_statedata *cx = &omap3_idle_data[idx];
	struct cpuidle_state_usage *state_usage = &dev->states_usage[idx];

	cpuidle_set_statedata(state_usage, cx);

	return cx;
}

/**
 * omap3_idle_init - Init routine for OMAP3 idle
 *
 * Registers the OMAP3 specific cpuidle driver to the cpuidle
 * framework with the valid set of states.
 */
int __init omap3_idle_init(void)
{
	struct cpuidle_device *dev;
	struct omap3_idle_statedata *cx;

	mpu_pd = pwrdm_lookup("mpu_pwrdm");
	core_pd = pwrdm_lookup("core_pwrdm");
	per_pd = pwrdm_lookup("per_pwrdm");
	cam_pd = pwrdm_lookup("cam_pwrdm");


	dev = &per_cpu(omap3_idle_dev, smp_processor_id());

	/* C1 . MPU WFI + Core active */
	cx = _fill_cstate_usage(dev, 0);
	cx->mpu_state = PWRDM_POWER_ON;
	cx->core_state = PWRDM_POWER_ON;

	/* C2 . MPU WFI + Core inactive */
	cx = _fill_cstate_usage(dev, 1);
	cx->mpu_state = PWRDM_POWER_ON;
	cx->core_state = PWRDM_POWER_ON;

	/* C3 . MPU CSWR + Core inactive */
	cx = _fill_cstate_usage(dev, 2);
	cx->mpu_state = PWRDM_POWER_RET;
	cx->core_state = PWRDM_POWER_ON;

	/* C4 . MPU OFF + Core inactive */
	cx = _fill_cstate_usage(dev, 3);
	cx->mpu_state = PWRDM_POWER_OFF;
	cx->core_state = PWRDM_POWER_ON;

	/* C5 . MPU RET + Core RET */
	cx = _fill_cstate_usage(dev, 4);
	cx->mpu_state = PWRDM_POWER_RET;
	cx->core_state = PWRDM_POWER_RET;

	/* C6 . MPU OFF + Core RET */
	cx = _fill_cstate_usage(dev, 5);
	cx->mpu_state = PWRDM_POWER_OFF;
	cx->core_state = PWRDM_POWER_RET;

	/* C7 . MPU OFF + Core OFF */
	cx = _fill_cstate_usage(dev, 6);
	cx->mpu_state = PWRDM_POWER_OFF;
	cx->core_state = PWRDM_POWER_OFF;

	cpuidle_register_driver(&omap3_idle_driver);

	if (cpuidle_register_device(dev)) {
		printk(KERN_ERR "%s: CPUidle register device failed\n",
		       __func__);
		return -EIO;
	}

	return 0;
}
#else
int __init omap3_idle_init(void)
{
	return 0;
}
#endif /* CONFIG_CPU_IDLE */
Commit	Line	Data
99e6a4d2 RN	1	/*
	2	* linux/arch/arm/mach-omap2/cpuidle34xx.c
	3	*
	4	* OMAP3 CPU IDLE Routines
	5	*
	6	* Copyright (C) 2008 Texas Instruments, Inc.
	7	* Rajendra Nayak <rnayak@ti.com>
	8	*
	9	* Copyright (C) 2007 Texas Instruments, Inc.
	10	* Karthik Dasu <karthik-dp@ti.com>
	11	*
	12	* Copyright (C) 2006 Nokia Corporation
	13	* Tony Lindgren <tony@atomide.com>
	14	*
	15	* Copyright (C) 2005 Texas Instruments, Inc.
	16	* Richard Woodruff <r-woodruff2@ti.com>
	17	*
	18	* Based on pm.c for omap2
	19	*
	20	* This program is free software; you can redistribute it and/or modify
	21	* it under the terms of the GNU General Public License version 2 as
	22	* published by the Free Software Foundation.
	23	*/
	24
cf22854c	25	#include <linux/sched.h>
99e6a4d2	26	#include <linux/cpuidle.h>
5698eb4e	27	#include <linux/export.h>
ff819da4	28	#include <linux/cpu_pm.h>
99e6a4d2 RN	29
99e6a4d2 RN	30	#include <plat/prcm.h>
20b01669	31	#include <plat/irqs.h>
72e06d08	32	#include "powerdomain.h"
1540f214	33	#include "clockdomain.h"
99e6a4d2	34
c98e2230	35	#include "pm.h"
4814ced5	36	#include "control.h"
ba8bb18a	37	#include "common.h"
c98e2230	38
99e6a4d2 RN	39	#ifdef CONFIG_CPU_IDLE
99e6a4d2 RN	40
badc303a JP	41	/* Mach specific information to be recorded in the C-state driver_data */
	42	struct omap3_idle_statedata {
	43	u32 mpu_state;
	44	u32 core_state;
badc303a	45	};
0c2487f6 DL	46
	47	#define OMAP3_NUM_STATES 7
	48
badc303a JP	49	struct omap3_idle_statedata omap3_idle_data[OMAP3_NUM_STATES];
	50
	51	struct powerdomain mpu_pd, core_pd, per_pd, cam_pd;
bb4de3df	52
06d8f065 PDS	53	static int _cpuidle_allow_idle(struct powerdomain *pwrdm,
	54	struct clockdomain *clkdm)
	55	{
5cd1937b	56	clkdm_allow_idle(clkdm);
06d8f065 PDS	57	return 0;
	58	}
	59
	60	static int _cpuidle_deny_idle(struct powerdomain *pwrdm,
	61	struct clockdomain *clkdm)
	62	{
5cd1937b	63	clkdm_deny_idle(clkdm);
06d8f065 PDS	64	return 0;
	65	}
	66
6da45dce	67	static int __omap3_enter_idle(struct cpuidle_device *dev,
46bcfad7	68	struct cpuidle_driver *drv,
e978aa7d	69	int index)
99e6a4d2	70	{
e978aa7d	71	struct omap3_idle_statedata *cx =
4202735e	72	cpuidle_get_statedata(&dev->states_usage[index]);
c98e2230	73	u32 mpu_state = cx->mpu_state, core_state = cx->core_state;
99e6a4d2	74
99e6a4d2 RN	75	local_fiq_disable();
99e6a4d2 RN	76
7139178e JH	77	pwrdm_set_next_pwrst(mpu_pd, mpu_state);
7139178e JH	78	pwrdm_set_next_pwrst(core_pd, core_state);
20b01669	79
cf22854c	80	if (omap_irq_pending() \|\| need_resched())
20b01669	81	goto return_sleep_time;
99e6a4d2	82
badc303a	83	/* Deny idle for C1 */
e978aa7d	84	if (index == 0) {
06d8f065 PDS	85	pwrdm_for_each_clkdm(mpu_pd, _cpuidle_deny_idle);
	86	pwrdm_for_each_clkdm(core_pd, _cpuidle_deny_idle);
	87	}
	88
ff819da4 SS	89	/*
	90	* Call idle CPU PM enter notifier chain so that
	91	* VFP context is saved.
	92	*/
	93	if (mpu_state == PWRDM_POWER_OFF)
	94	cpu_pm_enter();
	95
99e6a4d2 RN	96	/* Execute ARM wfi */
	97	omap_sram_idle();
	98
ff819da4 SS	99	/*
	100	* Call idle CPU PM enter notifier chain to restore
	101	* VFP context.
	102	*/
	103	if (pwrdm_read_prev_pwrst(mpu_pd) == PWRDM_POWER_OFF)
	104	cpu_pm_exit();
	105
badc303a	106	/* Re-allow idle for C1 */
e978aa7d	107	if (index == 0) {
06d8f065 PDS	108	pwrdm_for_each_clkdm(mpu_pd, _cpuidle_allow_idle);
	109	pwrdm_for_each_clkdm(core_pd, _cpuidle_allow_idle);
	110	}
	111
20b01669	112	return_sleep_time:
99e6a4d2	113
99e6a4d2 RN	114	local_fiq_enable();
99e6a4d2 RN	115
e978aa7d	116	return index;
99e6a4d2 RN	117	}
99e6a4d2 RN	118
6da45dce RL	119	/**
	120	* omap3_enter_idle - Programs OMAP3 to enter the specified state
	121	* @dev: cpuidle device
	122	* @drv: cpuidle driver
	123	* @index: the index of state to be entered
	124	*
	125	* Called from the CPUidle framework to program the device to the
	126	* specified target state selected by the governor.
	127	*/
	128	static inline int omap3_enter_idle(struct cpuidle_device *dev,
	129	struct cpuidle_driver *drv,
	130	int index)
	131	{
	132	return cpuidle_wrap_enter(dev, drv, index, __omap3_enter_idle);
	133	}
	134
6af83b38	135	/**
04908918	136	* next_valid_state - Find next valid C-state
6af83b38	137	* @dev: cpuidle device
46bcfad7	138	* @drv: cpuidle driver
e978aa7d	139	* @index: Index of currently selected c-state
6af83b38	140	*
e978aa7d DD	141	* If the state corresponding to index is valid, index is returned back
	142	* to the caller. Else, this function searches for a lower c-state which is
	143	* still valid (as defined in omap3_power_states[]) and returns its index.
04908918 JP	144	*
	145	* A state is valid if the 'valid' field is enabled and
	146	* if it satisfies the enable_off_mode condition.
6af83b38	147	*/
e978aa7d	148	static int next_valid_state(struct cpuidle_device *dev,
46bcfad7	149	struct cpuidle_driver *drv,
e978aa7d	150	int index)
6af83b38	151	{
4202735e	152	struct cpuidle_state_usage *curr_usage = &dev->states_usage[index];
46bcfad7	153	struct cpuidle_state *curr = &drv->states[index];
4202735e	154	struct omap3_idle_statedata *cx = cpuidle_get_statedata(curr_usage);
04908918 JP	155	u32 mpu_deepest_state = PWRDM_POWER_RET;
04908918 JP	156	u32 core_deepest_state = PWRDM_POWER_RET;
e978aa7d	157	int next_index = -1;
04908918 JP	158
	159	if (enable_off_mode) {
	160	mpu_deepest_state = PWRDM_POWER_OFF;
	161	/*
	162	* Erratum i583: valable for ES rev < Es1.2 on 3630.
	163	* CORE OFF mode is not supported in a stable form, restrict
	164	* instead the CORE state to RET.
	165	*/
	166	if (!IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583))
	167	core_deepest_state = PWRDM_POWER_OFF;
	168	}
6af83b38 SP	169
6af83b38 SP	170	/* Check if current state is valid */
f79b5d8a	171	if ((cx->mpu_state >= mpu_deepest_state) &&
04908918	172	(cx->core_state >= core_deepest_state)) {
e978aa7d	173	return index;
6af83b38	174	} else {
badc303a	175	int idx = OMAP3_NUM_STATES - 1;
6af83b38	176
c6cd91de	177	/* Reach the current state starting at highest C-state */
badc303a	178	for (; idx >= 0; idx--) {
46bcfad7	179	if (&drv->states[idx] == curr) {
e978aa7d	180	next_index = idx;
6af83b38 SP	181	break;
	182	}
	183	}
	184
c6cd91de	185	/* Should never hit this condition */
e978aa7d	186	WARN_ON(next_index == -1);
6af83b38 SP	187
	188	/*
	189	* Drop to next valid state.
	190	* Start search from the next (lower) state.
	191	*/
	192	idx--;
badc303a	193	for (; idx >= 0; idx--) {
4202735e	194	cx = cpuidle_get_statedata(&dev->states_usage[idx]);
f79b5d8a	195	if ((cx->mpu_state >= mpu_deepest_state) &&
04908918	196	(cx->core_state >= core_deepest_state)) {
e978aa7d	197	next_index = idx;
6af83b38 SP	198	break;
	199	}
	200	}
	201	/*
badc303a	202	* C1 is always valid.
e978aa7d DD	203	* So, no need to check for 'next_index == -1' outside
e978aa7d DD	204	* this loop.
6af83b38 SP	205	*/
	206	}
	207
e978aa7d	208	return next_index;
6af83b38 SP	209	}
6af83b38 SP	210
99e6a4d2 RN	211	/**
	212	* omap3_enter_idle_bm - Checks for any bus activity
	213	* @dev: cpuidle device
46bcfad7	214	* @drv: cpuidle driver
e978aa7d	215	* @index: array index of target state to be programmed
99e6a4d2	216	*
badc303a JP	217	* This function checks for any pending activity and then programs
badc303a JP	218	* the device to the specified or a safer state.
99e6a4d2 RN	219	*/
99e6a4d2 RN	220	static int omap3_enter_idle_bm(struct cpuidle_device *dev,
46bcfad7	221	struct cpuidle_driver *drv,
e978aa7d	222	int index)
99e6a4d2	223	{
e978aa7d	224	int new_state_idx;
c6cd91de	225	u32 core_next_state, per_next_state = 0, per_saved_state = 0, cam_state;
badc303a	226	struct omap3_idle_statedata *cx;
e7410cf7	227	int ret;
0f724ed9	228
e7410cf7 KH	229	/*
	230	* Prevent idle completely if CAM is active.
	231	* CAM does not have wakeup capability in OMAP3.
	232	*/
	233	cam_state = pwrdm_read_pwrst(cam_pd);
	234	if (cam_state == PWRDM_POWER_ON) {
46bcfad7	235	new_state_idx = drv->safe_state_index;
e7410cf7 KH	236	goto select_state;
	237	}
	238
c6cd91de JP	239	/*
	240	* FIXME: we currently manage device-specific idle states
	241	* for PER and CORE in combination with CPU-specific
	242	* idle states. This is wrong, and device-specific
	243	* idle management needs to be separated out into
	244	* its own code.
	245	*/
	246
e7410cf7 KH	247	/*
	248	* Prevent PER off if CORE is not in retention or off as this
	249	* would disable PER wakeups completely.
	250	*/
4202735e	251	cx = cpuidle_get_statedata(&dev->states_usage[index]);
c6cd91de	252	core_next_state = cx->core_state;
e7410cf7 KH	253	per_next_state = per_saved_state = pwrdm_read_next_pwrst(per_pd);
e7410cf7 KH	254	if ((per_next_state == PWRDM_POWER_OFF) &&
65707fb3	255	(core_next_state > PWRDM_POWER_RET))
e7410cf7	256	per_next_state = PWRDM_POWER_RET;
0f724ed9	257
e7410cf7 KH	258	/* Are we changing PER target state? */
	259	if (per_next_state != per_saved_state)
	260	pwrdm_set_next_pwrst(per_pd, per_next_state);
	261
46bcfad7	262	new_state_idx = next_valid_state(dev, drv, index);
c6cd91de	263
e7410cf7	264	select_state:
46bcfad7	265	ret = omap3_enter_idle(dev, drv, new_state_idx);
e7410cf7 KH	266
	267	/* Restore original PER state if it was modified */
	268	if (per_next_state != per_saved_state)
	269	pwrdm_set_next_pwrst(per_pd, per_saved_state);
	270
	271	return ret;
99e6a4d2 RN	272	}
	273
	274	DEFINE_PER_CPU(struct cpuidle_device, omap3_idle_dev);
	275
99e6a4d2 RN	276	struct cpuidle_driver omap3_idle_driver = {
	277	.name = "omap3_idle",
	278	.owner = THIS_MODULE,
200dd520 DL	279	.states = {
	280	{
	281	.enter = omap3_enter_idle,
	282	.exit_latency = 2 + 2,
	283	.target_residency = 5,
	284	.flags = CPUIDLE_FLAG_TIME_VALID,
	285	.name = "C1",
	286	.desc = "MPU ON + CORE ON",
	287	},
	288	{
	289	.enter = omap3_enter_idle_bm,
	290	.exit_latency = 10 + 10,
	291	.target_residency = 30,
	292	.flags = CPUIDLE_FLAG_TIME_VALID,
	293	.name = "C2",
	294	.desc = "MPU ON + CORE ON",
	295	},
	296	{
	297	.enter = omap3_enter_idle_bm,
	298	.exit_latency = 50 + 50,
	299	.target_residency = 300,
	300	.flags = CPUIDLE_FLAG_TIME_VALID,
	301	.name = "C3",
	302	.desc = "MPU RET + CORE ON",
	303	},
	304	{
	305	.enter = omap3_enter_idle_bm,
	306	.exit_latency = 1500 + 1800,
	307	.target_residency = 4000,
	308	.flags = CPUIDLE_FLAG_TIME_VALID,
	309	.name = "C4",
	310	.desc = "MPU OFF + CORE ON",
	311	},
	312	{
	313	.enter = omap3_enter_idle_bm,
	314	.exit_latency = 2500 + 7500,
	315	.target_residency = 12000,
	316	.flags = CPUIDLE_FLAG_TIME_VALID,
	317	.name = "C5",
	318	.desc = "MPU RET + CORE RET",
	319	},
	320	{
	321	.enter = omap3_enter_idle_bm,
	322	.exit_latency = 3000 + 8500,
	323	.target_residency = 15000,
	324	.flags = CPUIDLE_FLAG_TIME_VALID,
	325	.name = "C6",
	326	.desc = "MPU OFF + CORE RET",
	327	},
	328	{
	329	.enter = omap3_enter_idle_bm,
	330	.exit_latency = 10000 + 30000,
	331	.target_residency = 30000,
	332	.flags = CPUIDLE_FLAG_TIME_VALID,
	333	.name = "C7",
	334	.desc = "MPU OFF + CORE OFF",
	335	},
	336	},
	337	.state_count = OMAP3_NUM_STATES,
	338	.safe_state_index = 0,
99e6a4d2 RN	339	};
99e6a4d2 RN	340
46bcfad7 DD	341	/* Helper to register the driver_data */
	342	static inline struct omap3_idle_statedata *_fill_cstate_usage(
	343	struct cpuidle_device *dev,
	344	int idx)
	345	{
	346	struct omap3_idle_statedata *cx = &omap3_idle_data[idx];
	347	struct cpuidle_state_usage *state_usage = &dev->states_usage[idx];
	348
4202735e	349	cpuidle_set_statedata(state_usage, cx);
badc303a JP	350
	351	return cx;
	352	}
	353
99e6a4d2 RN	354	/**
	355	* omap3_idle_init - Init routine for OMAP3 idle
	356	*
badc303a	357	* Registers the OMAP3 specific cpuidle driver to the cpuidle
99e6a4d2 RN	358	* framework with the valid set of states.
99e6a4d2 RN	359	*/
0343371e	360	int __init omap3_idle_init(void)
99e6a4d2	361	{
99e6a4d2	362	struct cpuidle_device *dev;
badc303a	363	struct omap3_idle_statedata *cx;
99e6a4d2 RN	364
99e6a4d2 RN	365	mpu_pd = pwrdm_lookup("mpu_pwrdm");
20b01669	366	core_pd = pwrdm_lookup("core_pwrdm");
e7410cf7 KH	367	per_pd = pwrdm_lookup("per_pwrdm");
e7410cf7 KH	368	cam_pd = pwrdm_lookup("cam_pwrdm");
99e6a4d2	369
46bcfad7	370
99e6a4d2 RN	371	dev = &per_cpu(omap3_idle_dev, smp_processor_id());
99e6a4d2 RN	372
badc303a	373	/* C1 . MPU WFI + Core active */
46bcfad7	374	cx = _fill_cstate_usage(dev, 0);
badc303a JP	375	cx->mpu_state = PWRDM_POWER_ON;
	376	cx->core_state = PWRDM_POWER_ON;
	377
	378	/* C2 . MPU WFI + Core inactive */
46bcfad7	379	cx = _fill_cstate_usage(dev, 1);
badc303a JP	380	cx->mpu_state = PWRDM_POWER_ON;
	381	cx->core_state = PWRDM_POWER_ON;
	382
	383	/* C3 . MPU CSWR + Core inactive */
46bcfad7	384	cx = _fill_cstate_usage(dev, 2);
badc303a JP	385	cx->mpu_state = PWRDM_POWER_RET;
	386	cx->core_state = PWRDM_POWER_ON;
	387
	388	/* C4 . MPU OFF + Core inactive */
46bcfad7	389	cx = _fill_cstate_usage(dev, 3);
badc303a JP	390	cx->mpu_state = PWRDM_POWER_OFF;
	391	cx->core_state = PWRDM_POWER_ON;
	392
	393	/* C5 . MPU RET + Core RET */
46bcfad7	394	cx = _fill_cstate_usage(dev, 4);
badc303a JP	395	cx->mpu_state = PWRDM_POWER_RET;
badc303a JP	396	cx->core_state = PWRDM_POWER_RET;
99e6a4d2	397
badc303a	398	/* C6 . MPU OFF + Core RET */
46bcfad7	399	cx = _fill_cstate_usage(dev, 5);
badc303a JP	400	cx->mpu_state = PWRDM_POWER_OFF;
	401	cx->core_state = PWRDM_POWER_RET;
	402
	403	/* C7 . MPU OFF + Core OFF */
46bcfad7	404	cx = _fill_cstate_usage(dev, 6);
badc303a JP	405	cx->mpu_state = PWRDM_POWER_OFF;
badc303a JP	406	cx->core_state = PWRDM_POWER_OFF;
99e6a4d2	407
46bcfad7 DD	408	cpuidle_register_driver(&omap3_idle_driver);
46bcfad7 DD	409
99e6a4d2 RN	410	if (cpuidle_register_device(dev)) {
	411	printk(KERN_ERR "%s: CPUidle register device failed\n",
	412	__func__);
	413	return -EIO;
	414	}
	415
	416	return 0;
	417	}
0343371e KJ	418	#else
	419	int __init omap3_idle_init(void)
	420	{
	421	return 0;
	422	}
99e6a4d2	423	#endif /* CONFIG_CPU_IDLE */