[deliverable/linux.git] / arch / arm / mach-omap2 / cpuidle34xx.c

/*
 * linux/arch/arm/mach-omap2/cpuidle34xx.c
 *
 * OMAP3 CPU IDLE Routines
 *
 * Copyright (C) 2008 Texas Instruments, Inc.
 * Rajendra Nayak <rnayak@ti.com>
 *
 * Copyright (C) 2007 Texas Instruments, Inc.
 * Karthik Dasu <karthik-dp@ti.com>
 *
 * Copyright (C) 2006 Nokia Corporation
 * Tony Lindgren <tony@atomide.com>
 *
 * Copyright (C) 2005 Texas Instruments, Inc.
 * Richard Woodruff <r-woodruff2@ti.com>
 *
 * Based on pm.c for omap2
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/sched.h>
#include <linux/cpuidle.h>
#include <linux/export.h>
#include <linux/cpu_pm.h>

#include <plat/prcm.h>
#include <plat/irqs.h>
#include "powerdomain.h"
#include "clockdomain.h"

#include "pm.h"
#include "control.h"
#include "common.h"

/* Mach specific information to be recorded in the C-state driver_data */
struct omap3_idle_statedata {
	u32 mpu_state;
	u32 core_state;
};

static struct omap3_idle_statedata omap3_idle_data[] = {
	{
		.mpu_state = PWRDM_POWER_ON,
		.core_state = PWRDM_POWER_ON,
	},
	{
		.mpu_state = PWRDM_POWER_ON,
		.core_state = PWRDM_POWER_ON,
	},
	{
		.mpu_state = PWRDM_POWER_RET,
		.core_state = PWRDM_POWER_ON,
	},
	{
		.mpu_state = PWRDM_POWER_OFF,
		.core_state = PWRDM_POWER_ON,
	},
	{
		.mpu_state = PWRDM_POWER_RET,
		.core_state = PWRDM_POWER_RET,
	},
	{
		.mpu_state = PWRDM_POWER_OFF,
		.core_state = PWRDM_POWER_RET,
	},
	{
		.mpu_state = PWRDM_POWER_OFF,
		.core_state = PWRDM_POWER_OFF,
	},
};

static struct powerdomain *mpu_pd, *core_pd, *per_pd, *cam_pd;

static int _cpuidle_allow_idle(struct powerdomain *pwrdm,
				struct clockdomain *clkdm)
{
	clkdm_allow_idle(clkdm);
	return 0;
}

static int _cpuidle_deny_idle(struct powerdomain *pwrdm,
				struct clockdomain *clkdm)
{
	clkdm_deny_idle(clkdm);
	return 0;
}

static int __omap3_enter_idle(struct cpuidle_device *dev,
				struct cpuidle_driver *drv,
				int index)
{
	struct omap3_idle_statedata *cx = &omap3_idle_data[index];
	u32 mpu_state = cx->mpu_state, core_state = cx->core_state;

	local_fiq_disable();

	pwrdm_set_next_pwrst(mpu_pd, mpu_state);
	pwrdm_set_next_pwrst(core_pd, core_state);

	if (omap_irq_pending() || need_resched())
		goto return_sleep_time;

	/* Deny idle for C1 */
	if (index == 0) {
		pwrdm_for_each_clkdm(mpu_pd, _cpuidle_deny_idle);
		pwrdm_for_each_clkdm(core_pd, _cpuidle_deny_idle);
	}

	/*
	 * Call idle CPU PM enter notifier chain so that
	 * VFP context is saved.
	 */
	if (mpu_state == PWRDM_POWER_OFF)
		cpu_pm_enter();

	/* Execute ARM wfi */
	omap_sram_idle();

	/*
	 * Call idle CPU PM enter notifier chain to restore
	 * VFP context.
	 */
	if (pwrdm_read_prev_pwrst(mpu_pd) == PWRDM_POWER_OFF)
		cpu_pm_exit();

	/* Re-allow idle for C1 */
	if (index == 0) {
		pwrdm_for_each_clkdm(mpu_pd, _cpuidle_allow_idle);
		pwrdm_for_each_clkdm(core_pd, _cpuidle_allow_idle);
	}

return_sleep_time:

	local_fiq_enable();

	return index;
}

/**
 * omap3_enter_idle - Programs OMAP3 to enter the specified state
 * @dev: cpuidle device
 * @drv: cpuidle driver
 * @index: the index of state to be entered
 *
 * Called from the CPUidle framework to program the device to the
 * specified target state selected by the governor.
 */
static inline int omap3_enter_idle(struct cpuidle_device *dev,
				struct cpuidle_driver *drv,
				int index)
{
	return cpuidle_wrap_enter(dev, drv, index, __omap3_enter_idle);
}

/**
 * next_valid_state - Find next valid C-state
 * @dev: cpuidle device
 * @drv: cpuidle driver
 * @index: Index of currently selected c-state
 *
 * If the state corresponding to index is valid, index is returned back
 * to the caller. Else, this function searches for a lower c-state which is
 * still valid (as defined in omap3_power_states[]) and returns its index.
 *
 * A state is valid if the 'valid' field is enabled and
 * if it satisfies the enable_off_mode condition.
 */
static int next_valid_state(struct cpuidle_device *dev,
			    struct cpuidle_driver *drv, int index)
{
	struct omap3_idle_statedata *cx = &omap3_idle_data[index];
	u32 mpu_deepest_state = PWRDM_POWER_RET;
	u32 core_deepest_state = PWRDM_POWER_RET;
	int idx;
	int next_index = -1;

	if (enable_off_mode) {
		mpu_deepest_state = PWRDM_POWER_OFF;
		/*
		 * Erratum i583: valable for ES rev < Es1.2 on 3630.
		 * CORE OFF mode is not supported in a stable form, restrict
		 * instead the CORE state to RET.
		 */
		if (!IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583))
			core_deepest_state = PWRDM_POWER_OFF;
	}

	/* Check if current state is valid */
	if ((cx->mpu_state >= mpu_deepest_state) &&
	    (cx->core_state >= core_deepest_state))
		return index;

	/*
	 * Drop to next valid state.
	 * Start search from the next (lower) state.
	 */
	for (idx = index - 1; idx >= 0; idx--) {
		cx =  &omap3_idle_data[idx];
		if ((cx->mpu_state >= mpu_deepest_state) &&
		    (cx->core_state >= core_deepest_state)) {
			next_index = idx;
			break;
		}
	}

	/*
	 * C1 is always valid.
	 * So, no need to check for 'next_index == -1' outside
	 * this loop.
	 */

	return next_index;
}

/**
 * omap3_enter_idle_bm - Checks for any bus activity
 * @dev: cpuidle device
 * @drv: cpuidle driver
 * @index: array index of target state to be programmed
 *
 * This function checks for any pending activity and then programs
 * the device to the specified or a safer state.
 */
static int omap3_enter_idle_bm(struct cpuidle_device *dev,
				struct cpuidle_driver *drv,
			       int index)
{
	int new_state_idx;
	u32 core_next_state, per_next_state = 0, per_saved_state = 0, cam_state;
	struct omap3_idle_statedata *cx;
	int ret;

	/*
	 * Prevent idle completely if CAM is active.
	 * CAM does not have wakeup capability in OMAP3.
	 */
	cam_state = pwrdm_read_pwrst(cam_pd);
	if (cam_state == PWRDM_POWER_ON) {
		new_state_idx = drv->safe_state_index;
		goto select_state;
	}

	/*
	 * FIXME: we currently manage device-specific idle states
	 *        for PER and CORE in combination with CPU-specific
	 *        idle states.  This is wrong, and device-specific
	 *        idle management needs to be separated out into
	 *        its own code.
	 */

	/*
	 * Prevent PER off if CORE is not in retention or off as this
	 * would disable PER wakeups completely.
	 */
	cx = &omap3_idle_data[index];
	core_next_state = cx->core_state;
	per_next_state = per_saved_state = pwrdm_read_next_pwrst(per_pd);
	if ((per_next_state == PWRDM_POWER_OFF) &&
	    (core_next_state > PWRDM_POWER_RET))
		per_next_state = PWRDM_POWER_RET;

	/* Are we changing PER target state? */
	if (per_next_state != per_saved_state)
		pwrdm_set_next_pwrst(per_pd, per_next_state);

	new_state_idx = next_valid_state(dev, drv, index);

select_state:
	ret = omap3_enter_idle(dev, drv, new_state_idx);

	/* Restore original PER state if it was modified */
	if (per_next_state != per_saved_state)
		pwrdm_set_next_pwrst(per_pd, per_saved_state);

	return ret;
}

DEFINE_PER_CPU(struct cpuidle_device, omap3_idle_dev);

struct cpuidle_driver omap3_idle_driver = {
	.name = 	"omap3_idle",
	.owner = 	THIS_MODULE,
	.states = {
		{
			.enter		  = omap3_enter_idle,
			.exit_latency	  = 2 + 2,
			.target_residency = 5,
			.flags		  = CPUIDLE_FLAG_TIME_VALID,
			.name		  = "C1",
			.desc		  = "MPU ON + CORE ON",
		},
		{
			.enter		  = omap3_enter_idle_bm,
			.exit_latency	  = 10 + 10,
			.target_residency = 30,
			.flags		  = CPUIDLE_FLAG_TIME_VALID,
			.name		  = "C2",
			.desc		  = "MPU ON + CORE ON",
		},
		{
			.enter		  = omap3_enter_idle_bm,
			.exit_latency	  = 50 + 50,
			.target_residency = 300,
			.flags		  = CPUIDLE_FLAG_TIME_VALID,
			.name		  = "C3",
			.desc		  = "MPU RET + CORE ON",
		},
		{
			.enter		  = omap3_enter_idle_bm,
			.exit_latency	  = 1500 + 1800,
			.target_residency = 4000,
			.flags		  = CPUIDLE_FLAG_TIME_VALID,
			.name		  = "C4",
			.desc		  = "MPU OFF + CORE ON",
		},
		{
			.enter		  = omap3_enter_idle_bm,
			.exit_latency	  = 2500 + 7500,
			.target_residency = 12000,
			.flags		  = CPUIDLE_FLAG_TIME_VALID,
			.name		  = "C5",
			.desc		  = "MPU RET + CORE RET",
		},
		{
			.enter		  = omap3_enter_idle_bm,
			.exit_latency	  = 3000 + 8500,
			.target_residency = 15000,
			.flags		  = CPUIDLE_FLAG_TIME_VALID,
			.name		  = "C6",
			.desc		  = "MPU OFF + CORE RET",
		},
		{
			.enter		  = omap3_enter_idle_bm,
			.exit_latency	  = 10000 + 30000,
			.target_residency = 30000,
			.flags		  = CPUIDLE_FLAG_TIME_VALID,
			.name		  = "C7",
			.desc		  = "MPU OFF + CORE OFF",
		},
	},
	.state_count = ARRAY_SIZE(omap3_idle_data),
	.safe_state_index = 0,
};

/**
 * omap3_idle_init - Init routine for OMAP3 idle
 *
 * Registers the OMAP3 specific cpuidle driver to the cpuidle
 * framework with the valid set of states.
 */
int __init omap3_idle_init(void)
{
	struct cpuidle_device *dev;

	mpu_pd = pwrdm_lookup("mpu_pwrdm");
	core_pd = pwrdm_lookup("core_pwrdm");
	per_pd = pwrdm_lookup("per_pwrdm");
	cam_pd = pwrdm_lookup("cam_pwrdm");

	if (!mpu_pd || !core_pd || !per_pd || !cam_pd)
		return -ENODEV;

	cpuidle_register_driver(&omap3_idle_driver);

	dev = &per_cpu(omap3_idle_dev, smp_processor_id());
	dev->cpu = 0;

	if (cpuidle_register_device(dev)) {
		printk(KERN_ERR "%s: CPUidle register device failed\n",
		       __func__);
		return -EIO;
	}

	return 0;
}
Commit	Line	Data
99e6a4d2 RN	1	/*
	2	* linux/arch/arm/mach-omap2/cpuidle34xx.c
	3	*
	4	* OMAP3 CPU IDLE Routines
	5	*
	6	* Copyright (C) 2008 Texas Instruments, Inc.
	7	* Rajendra Nayak <rnayak@ti.com>
	8	*
	9	* Copyright (C) 2007 Texas Instruments, Inc.
	10	* Karthik Dasu <karthik-dp@ti.com>
	11	*
	12	* Copyright (C) 2006 Nokia Corporation
	13	* Tony Lindgren <tony@atomide.com>
	14	*
	15	* Copyright (C) 2005 Texas Instruments, Inc.
	16	* Richard Woodruff <r-woodruff2@ti.com>
	17	*
	18	* Based on pm.c for omap2
	19	*
	20	* This program is free software; you can redistribute it and/or modify
	21	* it under the terms of the GNU General Public License version 2 as
	22	* published by the Free Software Foundation.
	23	*/
	24
cf22854c	25	#include <linux/sched.h>
99e6a4d2	26	#include <linux/cpuidle.h>
5698eb4e	27	#include <linux/export.h>
ff819da4	28	#include <linux/cpu_pm.h>
99e6a4d2 RN	29
99e6a4d2 RN	30	#include <plat/prcm.h>
20b01669	31	#include <plat/irqs.h>
72e06d08	32	#include "powerdomain.h"
1540f214	33	#include "clockdomain.h"
99e6a4d2	34
c98e2230	35	#include "pm.h"
4814ced5	36	#include "control.h"
ba8bb18a	37	#include "common.h"
c98e2230	38
badc303a JP	39	/* Mach specific information to be recorded in the C-state driver_data */
	40	struct omap3_idle_statedata {
	41	u32 mpu_state;
	42	u32 core_state;
badc303a	43	};
0c2487f6	44
97abc496	45	static struct omap3_idle_statedata omap3_idle_data[] = {
88c377dd DL	46	{
	47	.mpu_state = PWRDM_POWER_ON,
	48	.core_state = PWRDM_POWER_ON,
	49	},
	50	{
	51	.mpu_state = PWRDM_POWER_ON,
	52	.core_state = PWRDM_POWER_ON,
	53	},
	54	{
	55	.mpu_state = PWRDM_POWER_RET,
	56	.core_state = PWRDM_POWER_ON,
	57	},
	58	{
	59	.mpu_state = PWRDM_POWER_OFF,
	60	.core_state = PWRDM_POWER_ON,
	61	},
	62	{
	63	.mpu_state = PWRDM_POWER_RET,
	64	.core_state = PWRDM_POWER_RET,
	65	},
	66	{
	67	.mpu_state = PWRDM_POWER_OFF,
	68	.core_state = PWRDM_POWER_RET,
	69	},
	70	{
	71	.mpu_state = PWRDM_POWER_OFF,
	72	.core_state = PWRDM_POWER_OFF,
	73	},
	74	};
badc303a	75
34fd57bf	76	static struct powerdomain mpu_pd, core_pd, per_pd, cam_pd;
bb4de3df	77
06d8f065 PDS	78	static int _cpuidle_allow_idle(struct powerdomain *pwrdm,
	79	struct clockdomain *clkdm)
	80	{
5cd1937b	81	clkdm_allow_idle(clkdm);
06d8f065 PDS	82	return 0;
	83	}
	84
	85	static int _cpuidle_deny_idle(struct powerdomain *pwrdm,
	86	struct clockdomain *clkdm)
	87	{
5cd1937b	88	clkdm_deny_idle(clkdm);
06d8f065 PDS	89	return 0;
	90	}
	91
6da45dce	92	static int __omap3_enter_idle(struct cpuidle_device *dev,
46bcfad7	93	struct cpuidle_driver *drv,
e978aa7d	94	int index)
99e6a4d2	95	{
6622ac55	96	struct omap3_idle_statedata *cx = &omap3_idle_data[index];
c98e2230	97	u32 mpu_state = cx->mpu_state, core_state = cx->core_state;
99e6a4d2	98
99e6a4d2 RN	99	local_fiq_disable();
99e6a4d2 RN	100
7139178e JH	101	pwrdm_set_next_pwrst(mpu_pd, mpu_state);
7139178e JH	102	pwrdm_set_next_pwrst(core_pd, core_state);
20b01669	103
cf22854c	104	if (omap_irq_pending() \|\| need_resched())
20b01669	105	goto return_sleep_time;
99e6a4d2	106
badc303a	107	/* Deny idle for C1 */
e978aa7d	108	if (index == 0) {
06d8f065 PDS	109	pwrdm_for_each_clkdm(mpu_pd, _cpuidle_deny_idle);
	110	pwrdm_for_each_clkdm(core_pd, _cpuidle_deny_idle);
	111	}
	112
ff819da4 SS	113	/*
	114	* Call idle CPU PM enter notifier chain so that
	115	* VFP context is saved.
	116	*/
	117	if (mpu_state == PWRDM_POWER_OFF)
	118	cpu_pm_enter();
	119
99e6a4d2 RN	120	/* Execute ARM wfi */
	121	omap_sram_idle();
	122
ff819da4 SS	123	/*
	124	* Call idle CPU PM enter notifier chain to restore
	125	* VFP context.
	126	*/
	127	if (pwrdm_read_prev_pwrst(mpu_pd) == PWRDM_POWER_OFF)
	128	cpu_pm_exit();
	129
badc303a	130	/* Re-allow idle for C1 */
e978aa7d	131	if (index == 0) {
06d8f065 PDS	132	pwrdm_for_each_clkdm(mpu_pd, _cpuidle_allow_idle);
	133	pwrdm_for_each_clkdm(core_pd, _cpuidle_allow_idle);
	134	}
	135
20b01669	136	return_sleep_time:
99e6a4d2	137
99e6a4d2 RN	138	local_fiq_enable();
99e6a4d2 RN	139
e978aa7d	140	return index;
99e6a4d2 RN	141	}
99e6a4d2 RN	142
6da45dce RL	143	/**
	144	* omap3_enter_idle - Programs OMAP3 to enter the specified state
	145	* @dev: cpuidle device
	146	* @drv: cpuidle driver
	147	* @index: the index of state to be entered
	148	*
	149	* Called from the CPUidle framework to program the device to the
	150	* specified target state selected by the governor.
	151	*/
	152	static inline int omap3_enter_idle(struct cpuidle_device *dev,
	153	struct cpuidle_driver *drv,
	154	int index)
	155	{
	156	return cpuidle_wrap_enter(dev, drv, index, __omap3_enter_idle);
	157	}
	158
6af83b38	159	/**
04908918	160	* next_valid_state - Find next valid C-state
6af83b38	161	* @dev: cpuidle device
46bcfad7	162	* @drv: cpuidle driver
e978aa7d	163	* @index: Index of currently selected c-state
6af83b38	164	*
e978aa7d DD	165	* If the state corresponding to index is valid, index is returned back
	166	* to the caller. Else, this function searches for a lower c-state which is
	167	* still valid (as defined in omap3_power_states[]) and returns its index.
04908918 JP	168	*
	169	* A state is valid if the 'valid' field is enabled and
	170	* if it satisfies the enable_off_mode condition.
6af83b38	171	*/
e978aa7d	172	static int next_valid_state(struct cpuidle_device *dev,
e92a4586	173	struct cpuidle_driver *drv, int index)
6af83b38	174	{
6622ac55	175	struct omap3_idle_statedata *cx = &omap3_idle_data[index];
04908918 JP	176	u32 mpu_deepest_state = PWRDM_POWER_RET;
04908918 JP	177	u32 core_deepest_state = PWRDM_POWER_RET;
e92a4586	178	int idx;
e978aa7d	179	int next_index = -1;
04908918 JP	180
	181	if (enable_off_mode) {
	182	mpu_deepest_state = PWRDM_POWER_OFF;
	183	/*
	184	* Erratum i583: valable for ES rev < Es1.2 on 3630.
	185	* CORE OFF mode is not supported in a stable form, restrict
	186	* instead the CORE state to RET.
	187	*/
	188	if (!IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583))
	189	core_deepest_state = PWRDM_POWER_OFF;
	190	}
6af83b38 SP	191
6af83b38 SP	192	/* Check if current state is valid */
f79b5d8a	193	if ((cx->mpu_state >= mpu_deepest_state) &&
e92a4586	194	(cx->core_state >= core_deepest_state))
e978aa7d	195	return index;
6af83b38	196
e92a4586 DL	197	/*
	198	* Drop to next valid state.
	199	* Start search from the next (lower) state.
	200	*/
	201	for (idx = index - 1; idx >= 0; idx--) {
	202	cx = &omap3_idle_data[idx];
	203	if ((cx->mpu_state >= mpu_deepest_state) &&
	204	(cx->core_state >= core_deepest_state)) {
	205	next_index = idx;
	206	break;
6af83b38	207	}
6af83b38 SP	208	}
6af83b38 SP	209
e92a4586 DL	210	/*
	211	* C1 is always valid.
	212	* So, no need to check for 'next_index == -1' outside
	213	* this loop.
	214	*/
	215
e978aa7d	216	return next_index;
6af83b38 SP	217	}
6af83b38 SP	218
99e6a4d2 RN	219	/**
	220	* omap3_enter_idle_bm - Checks for any bus activity
	221	* @dev: cpuidle device
46bcfad7	222	* @drv: cpuidle driver
e978aa7d	223	* @index: array index of target state to be programmed
99e6a4d2	224	*
badc303a JP	225	* This function checks for any pending activity and then programs
badc303a JP	226	* the device to the specified or a safer state.
99e6a4d2 RN	227	*/
99e6a4d2 RN	228	static int omap3_enter_idle_bm(struct cpuidle_device *dev,
46bcfad7	229	struct cpuidle_driver *drv,
e978aa7d	230	int index)
99e6a4d2	231	{
e978aa7d	232	int new_state_idx;
c6cd91de	233	u32 core_next_state, per_next_state = 0, per_saved_state = 0, cam_state;
badc303a	234	struct omap3_idle_statedata *cx;
e7410cf7	235	int ret;
0f724ed9	236
e7410cf7 KH	237	/*
	238	* Prevent idle completely if CAM is active.
	239	* CAM does not have wakeup capability in OMAP3.
	240	*/
	241	cam_state = pwrdm_read_pwrst(cam_pd);
	242	if (cam_state == PWRDM_POWER_ON) {
46bcfad7	243	new_state_idx = drv->safe_state_index;
e7410cf7 KH	244	goto select_state;
	245	}
	246
c6cd91de JP	247	/*
	248	* FIXME: we currently manage device-specific idle states
	249	* for PER and CORE in combination with CPU-specific
	250	* idle states. This is wrong, and device-specific
	251	* idle management needs to be separated out into
	252	* its own code.
	253	*/
	254
e7410cf7 KH	255	/*
	256	* Prevent PER off if CORE is not in retention or off as this
	257	* would disable PER wakeups completely.
	258	*/
6622ac55	259	cx = &omap3_idle_data[index];
c6cd91de	260	core_next_state = cx->core_state;
e7410cf7 KH	261	per_next_state = per_saved_state = pwrdm_read_next_pwrst(per_pd);
e7410cf7 KH	262	if ((per_next_state == PWRDM_POWER_OFF) &&
65707fb3	263	(core_next_state > PWRDM_POWER_RET))
e7410cf7	264	per_next_state = PWRDM_POWER_RET;
0f724ed9	265
e7410cf7 KH	266	/* Are we changing PER target state? */
	267	if (per_next_state != per_saved_state)
	268	pwrdm_set_next_pwrst(per_pd, per_next_state);
	269
46bcfad7	270	new_state_idx = next_valid_state(dev, drv, index);
c6cd91de	271
e7410cf7	272	select_state:
46bcfad7	273	ret = omap3_enter_idle(dev, drv, new_state_idx);
e7410cf7 KH	274
	275	/* Restore original PER state if it was modified */
	276	if (per_next_state != per_saved_state)
	277	pwrdm_set_next_pwrst(per_pd, per_saved_state);
	278
	279	return ret;
99e6a4d2 RN	280	}
	281
	282	DEFINE_PER_CPU(struct cpuidle_device, omap3_idle_dev);
	283
99e6a4d2 RN	284	struct cpuidle_driver omap3_idle_driver = {
	285	.name = "omap3_idle",
	286	.owner = THIS_MODULE,
200dd520 DL	287	.states = {
	288	{
	289	.enter = omap3_enter_idle,
	290	.exit_latency = 2 + 2,
	291	.target_residency = 5,
	292	.flags = CPUIDLE_FLAG_TIME_VALID,
	293	.name = "C1",
	294	.desc = "MPU ON + CORE ON",
	295	},
	296	{
	297	.enter = omap3_enter_idle_bm,
	298	.exit_latency = 10 + 10,
	299	.target_residency = 30,
	300	.flags = CPUIDLE_FLAG_TIME_VALID,
	301	.name = "C2",
	302	.desc = "MPU ON + CORE ON",
	303	},
	304	{
	305	.enter = omap3_enter_idle_bm,
	306	.exit_latency = 50 + 50,
	307	.target_residency = 300,
	308	.flags = CPUIDLE_FLAG_TIME_VALID,
	309	.name = "C3",
	310	.desc = "MPU RET + CORE ON",
	311	},
	312	{
	313	.enter = omap3_enter_idle_bm,
	314	.exit_latency = 1500 + 1800,
	315	.target_residency = 4000,
	316	.flags = CPUIDLE_FLAG_TIME_VALID,
	317	.name = "C4",
	318	.desc = "MPU OFF + CORE ON",
	319	},
	320	{
	321	.enter = omap3_enter_idle_bm,
	322	.exit_latency = 2500 + 7500,
	323	.target_residency = 12000,
	324	.flags = CPUIDLE_FLAG_TIME_VALID,
	325	.name = "C5",
	326	.desc = "MPU RET + CORE RET",
	327	},
	328	{
	329	.enter = omap3_enter_idle_bm,
	330	.exit_latency = 3000 + 8500,
	331	.target_residency = 15000,
	332	.flags = CPUIDLE_FLAG_TIME_VALID,
	333	.name = "C6",
	334	.desc = "MPU OFF + CORE RET",
	335	},
	336	{
	337	.enter = omap3_enter_idle_bm,
	338	.exit_latency = 10000 + 30000,
	339	.target_residency = 30000,
	340	.flags = CPUIDLE_FLAG_TIME_VALID,
	341	.name = "C7",
	342	.desc = "MPU OFF + CORE OFF",
	343	},
	344	},
88c377dd	345	.state_count = ARRAY_SIZE(omap3_idle_data),
200dd520	346	.safe_state_index = 0,
99e6a4d2 RN	347	};
	348
	349	/**
	350	* omap3_idle_init - Init routine for OMAP3 idle
	351	*
badc303a	352	* Registers the OMAP3 specific cpuidle driver to the cpuidle
99e6a4d2 RN	353	* framework with the valid set of states.
99e6a4d2 RN	354	*/
0343371e	355	int __init omap3_idle_init(void)
99e6a4d2	356	{
99e6a4d2 RN	357	struct cpuidle_device *dev;
	358
	359	mpu_pd = pwrdm_lookup("mpu_pwrdm");
20b01669	360	core_pd = pwrdm_lookup("core_pwrdm");
e7410cf7 KH	361	per_pd = pwrdm_lookup("per_pwrdm");
e7410cf7 KH	362	cam_pd = pwrdm_lookup("cam_pwrdm");
99e6a4d2	363
daa37cee DL	364	if (!mpu_pd \|\| !core_pd \|\| !per_pd \|\| !cam_pd)
	365	return -ENODEV;
	366
6622ac55	367	cpuidle_register_driver(&omap3_idle_driver);
46bcfad7	368
99e6a4d2	369	dev = &per_cpu(omap3_idle_dev, smp_processor_id());
6622ac55	370	dev->cpu = 0;
46bcfad7	371
99e6a4d2 RN	372	if (cpuidle_register_device(dev)) {
	373	printk(KERN_ERR "%s: CPUidle register device failed\n",
	374	__func__);
	375	return -EIO;
	376	}
	377
	378	return 0;
	379	}