[deliverable/linux.git] / arch / arm / mach-omap2 / cpuidle34xx.c

/*
 * linux/arch/arm/mach-omap2/cpuidle34xx.c
 *
 * OMAP3 CPU IDLE Routines
 *
 * Copyright (C) 2008 Texas Instruments, Inc.
 * Rajendra Nayak <rnayak@ti.com>
 *
 * Copyright (C) 2007 Texas Instruments, Inc.
 * Karthik Dasu <karthik-dp@ti.com>
 *
 * Copyright (C) 2006 Nokia Corporation
 * Tony Lindgren <tony@atomide.com>
 *
 * Copyright (C) 2005 Texas Instruments, Inc.
 * Richard Woodruff <r-woodruff2@ti.com>
 *
 * Based on pm.c for omap2
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/cpuidle.h>

#include <plat/prcm.h>
#include <plat/powerdomain.h>
#include <plat/irqs.h>
#include <plat/control.h>

#ifdef CONFIG_CPU_IDLE

#define OMAP3_MAX_STATES 7
#define OMAP3_STATE_C1 1 /* C1 - MPU WFI + Core active */
#define OMAP3_STATE_C2 2 /* C2 - MPU CSWR + Core active */
#define OMAP3_STATE_C3 3 /* C3 - MPU OFF + Core active */
#define OMAP3_STATE_C4 4 /* C4 - MPU RET + Core RET */
#define OMAP3_STATE_C5 5 /* C5 - MPU OFF + Core RET */
#define OMAP3_STATE_C6 6 /* C6 - MPU OFF + Core OFF */

struct omap3_processor_cx {
	u8 valid;
	u8 type;
	u32 sleep_latency;
	u32 wakeup_latency;
	u32 mpu_state;
	u32 core_state;
	u32 threshold;
	u32 flags;
};

struct omap3_processor_cx omap3_power_states[OMAP3_MAX_STATES];
struct omap3_processor_cx current_cx_state;
struct powerdomain *mpu_pd, *core_pd;

static int omap3_idle_bm_check(void)
{
	if (!omap3_can_sleep())
		return 1;
	return 0;
}

/**
 * omap3_enter_idle - Programs OMAP3 to enter the specified state
 * @dev: cpuidle device
 * @state: The target state to be programmed
 *
 * Called from the CPUidle framework to program the device to the
 * specified target state selected by the governor.
 */
static int omap3_enter_idle(struct cpuidle_device *dev,
			struct cpuidle_state *state)
{
	struct omap3_processor_cx *cx = cpuidle_get_statedata(state);
	struct timespec ts_preidle, ts_postidle, ts_idle;

	current_cx_state = *cx;

	/* Used to keep track of the total time in idle */
	getnstimeofday(&ts_preidle);

	local_irq_disable();
	local_fiq_disable();

	set_pwrdm_state(mpu_pd, cx->mpu_state);
	set_pwrdm_state(core_pd, cx->core_state);

	if (omap_irq_pending())
		goto return_sleep_time;

	/* Execute ARM wfi */
	omap_sram_idle();

return_sleep_time:
	getnstimeofday(&ts_postidle);
	ts_idle = timespec_sub(ts_postidle, ts_preidle);

	local_irq_enable();
	local_fiq_enable();

	return (u32)timespec_to_ns(&ts_idle)/1000;
}

/**
 * omap3_enter_idle_bm - Checks for any bus activity
 * @dev: cpuidle device
 * @state: The target state to be programmed
 *
 * Used for C states with CPUIDLE_FLAG_CHECK_BM flag set. This
 * function checks for any pending activity and then programs the
 * device to the specified or a safer state.
 */
static int omap3_enter_idle_bm(struct cpuidle_device *dev,
			       struct cpuidle_state *state)
{
	if ((state->flags & CPUIDLE_FLAG_CHECK_BM) && omap3_idle_bm_check()) {
		if (dev->safe_state)
			return dev->safe_state->enter(dev, dev->safe_state);
	}
	return omap3_enter_idle(dev, state);
}

DEFINE_PER_CPU(struct cpuidle_device, omap3_idle_dev);

/* omap3_init_power_states - Initialises the OMAP3 specific C states.
 *
 * Below is the desciption of each C state.
 *	C1 . MPU WFI + Core active
 *	C2 . MPU CSWR + Core active
 *	C3 . MPU OFF + Core active
 *	C4 . MPU CSWR + Core CSWR
 *	C5 . MPU OFF + Core CSWR
 *	C6 . MPU OFF + Core OFF
 */
void omap_init_power_states(void)
{
	/* C1 . MPU WFI + Core active */
	omap3_power_states[OMAP3_STATE_C1].valid = 1;
	omap3_power_states[OMAP3_STATE_C1].type = OMAP3_STATE_C1;
	omap3_power_states[OMAP3_STATE_C1].sleep_latency = 10;
	omap3_power_states[OMAP3_STATE_C1].wakeup_latency = 10;
	omap3_power_states[OMAP3_STATE_C1].threshold = 30;
	omap3_power_states[OMAP3_STATE_C1].mpu_state = PWRDM_POWER_ON;
	omap3_power_states[OMAP3_STATE_C1].core_state = PWRDM_POWER_ON;
	omap3_power_states[OMAP3_STATE_C1].flags = CPUIDLE_FLAG_TIME_VALID;

	/* C2 . MPU CSWR + Core active */
	omap3_power_states[OMAP3_STATE_C2].valid = 1;
	omap3_power_states[OMAP3_STATE_C2].type = OMAP3_STATE_C2;
	omap3_power_states[OMAP3_STATE_C2].sleep_latency = 50;
	omap3_power_states[OMAP3_STATE_C2].wakeup_latency = 50;
	omap3_power_states[OMAP3_STATE_C2].threshold = 300;
	omap3_power_states[OMAP3_STATE_C2].mpu_state = PWRDM_POWER_RET;
	omap3_power_states[OMAP3_STATE_C2].core_state = PWRDM_POWER_ON;
	omap3_power_states[OMAP3_STATE_C2].flags = CPUIDLE_FLAG_TIME_VALID;

	/* C3 . MPU OFF + Core active */
	omap3_power_states[OMAP3_STATE_C3].valid = 1;
	omap3_power_states[OMAP3_STATE_C3].type = OMAP3_STATE_C3;
	omap3_power_states[OMAP3_STATE_C3].sleep_latency = 1500;
	omap3_power_states[OMAP3_STATE_C3].wakeup_latency = 1800;
	omap3_power_states[OMAP3_STATE_C3].threshold = 4000;
	omap3_power_states[OMAP3_STATE_C3].mpu_state = PWRDM_POWER_OFF;
	omap3_power_states[OMAP3_STATE_C3].core_state = PWRDM_POWER_ON;
	omap3_power_states[OMAP3_STATE_C3].flags = CPUIDLE_FLAG_TIME_VALID;

	/* C4 . MPU CSWR + Core CSWR*/
	omap3_power_states[OMAP3_STATE_C4].valid = 1;
	omap3_power_states[OMAP3_STATE_C4].type = OMAP3_STATE_C4;
	omap3_power_states[OMAP3_STATE_C4].sleep_latency = 2500;
	omap3_power_states[OMAP3_STATE_C4].wakeup_latency = 7500;
	omap3_power_states[OMAP3_STATE_C4].threshold = 12000;
	omap3_power_states[OMAP3_STATE_C4].mpu_state = PWRDM_POWER_RET;
	omap3_power_states[OMAP3_STATE_C4].core_state = PWRDM_POWER_RET;
	omap3_power_states[OMAP3_STATE_C4].flags = CPUIDLE_FLAG_TIME_VALID |
				CPUIDLE_FLAG_CHECK_BM;

	/* C5 . MPU OFF + Core CSWR */
	omap3_power_states[OMAP3_STATE_C5].valid = 1;
	omap3_power_states[OMAP3_STATE_C5].type = OMAP3_STATE_C5;
	omap3_power_states[OMAP3_STATE_C5].sleep_latency = 3000;
	omap3_power_states[OMAP3_STATE_C5].wakeup_latency = 8500;
	omap3_power_states[OMAP3_STATE_C5].threshold = 15000;
	omap3_power_states[OMAP3_STATE_C5].mpu_state = PWRDM_POWER_OFF;
	omap3_power_states[OMAP3_STATE_C5].core_state = PWRDM_POWER_RET;
	omap3_power_states[OMAP3_STATE_C5].flags = CPUIDLE_FLAG_TIME_VALID |
				CPUIDLE_FLAG_CHECK_BM;

	/* C6 . MPU OFF + Core OFF */
	omap3_power_states[OMAP3_STATE_C6].valid = 0;
	omap3_power_states[OMAP3_STATE_C6].type = OMAP3_STATE_C6;
	omap3_power_states[OMAP3_STATE_C6].sleep_latency = 10000;
	omap3_power_states[OMAP3_STATE_C6].wakeup_latency = 30000;
	omap3_power_states[OMAP3_STATE_C6].threshold = 300000;
	omap3_power_states[OMAP3_STATE_C6].mpu_state = PWRDM_POWER_OFF;
	omap3_power_states[OMAP3_STATE_C6].core_state = PWRDM_POWER_OFF;
	omap3_power_states[OMAP3_STATE_C6].flags = CPUIDLE_FLAG_TIME_VALID |
				CPUIDLE_FLAG_CHECK_BM;
}

struct cpuidle_driver omap3_idle_driver = {
	.name = 	"omap3_idle",
	.owner = 	THIS_MODULE,
};

/**
 * omap3_idle_init - Init routine for OMAP3 idle
 *
 * Registers the OMAP3 specific cpuidle driver with the cpuidle
 * framework with the valid set of states.
 */
int omap3_idle_init(void)
{
	int i, count = 0;
	struct omap3_processor_cx *cx;
	struct cpuidle_state *state;
	struct cpuidle_device *dev;

	mpu_pd = pwrdm_lookup("mpu_pwrdm");
	core_pd = pwrdm_lookup("core_pwrdm");

	omap_init_power_states();
	cpuidle_register_driver(&omap3_idle_driver);

	dev = &per_cpu(omap3_idle_dev, smp_processor_id());

	for (i = 1; i < OMAP3_MAX_STATES; i++) {
		cx = &omap3_power_states[i];
		state = &dev->states[count];

		if (!cx->valid)
			continue;
		cpuidle_set_statedata(state, cx);
		state->exit_latency = cx->sleep_latency + cx->wakeup_latency;
		state->target_residency = cx->threshold;
		state->flags = cx->flags;
		state->enter = (state->flags & CPUIDLE_FLAG_CHECK_BM) ?
			omap3_enter_idle_bm : omap3_enter_idle;
		if (cx->type == OMAP3_STATE_C1)
			dev->safe_state = state;
		sprintf(state->name, "C%d", count+1);
		count++;
	}

	if (!count)
		return -EINVAL;
	dev->state_count = count;

	if (cpuidle_register_device(dev)) {
		printk(KERN_ERR "%s: CPUidle register device failed\n",
		       __func__);
		return -EIO;
	}

	return 0;
}
device_initcall(omap3_idle_init);
#endif /* CONFIG_CPU_IDLE */
Commit	Line	Data
99e6a4d2 RN	1	/*
	2	* linux/arch/arm/mach-omap2/cpuidle34xx.c
	3	*
	4	* OMAP3 CPU IDLE Routines
	5	*
	6	* Copyright (C) 2008 Texas Instruments, Inc.
	7	* Rajendra Nayak <rnayak@ti.com>
	8	*
	9	* Copyright (C) 2007 Texas Instruments, Inc.
	10	* Karthik Dasu <karthik-dp@ti.com>
	11	*
	12	* Copyright (C) 2006 Nokia Corporation
	13	* Tony Lindgren <tony@atomide.com>
	14	*
	15	* Copyright (C) 2005 Texas Instruments, Inc.
	16	* Richard Woodruff <r-woodruff2@ti.com>
	17	*
	18	* Based on pm.c for omap2
	19	*
	20	* This program is free software; you can redistribute it and/or modify
	21	* it under the terms of the GNU General Public License version 2 as
	22	* published by the Free Software Foundation.
	23	*/
	24
	25	#include <linux/cpuidle.h>
	26
	27	#include <plat/prcm.h>
	28	#include <plat/powerdomain.h>
20b01669 RN	29	#include <plat/irqs.h>
20b01669 RN	30	#include <plat/control.h>
99e6a4d2 RN	31
	32	#ifdef CONFIG_CPU_IDLE
	33
	34	#define OMAP3_MAX_STATES 7
	35	#define OMAP3_STATE_C1 1 /* C1 - MPU WFI + Core active */
	36	#define OMAP3_STATE_C2 2 /* C2 - MPU CSWR + Core active */
	37	#define OMAP3_STATE_C3 3 /* C3 - MPU OFF + Core active */
	38	#define OMAP3_STATE_C4 4 /* C4 - MPU RET + Core RET */
	39	#define OMAP3_STATE_C5 5 /* C5 - MPU OFF + Core RET */
	40	#define OMAP3_STATE_C6 6 /* C6 - MPU OFF + Core OFF */
	41
	42	struct omap3_processor_cx {
	43	u8 valid;
	44	u8 type;
	45	u32 sleep_latency;
	46	u32 wakeup_latency;
	47	u32 mpu_state;
	48	u32 core_state;
	49	u32 threshold;
	50	u32 flags;
	51	};
	52
	53	struct omap3_processor_cx omap3_power_states[OMAP3_MAX_STATES];
	54	struct omap3_processor_cx current_cx_state;
20b01669	55	struct powerdomain mpu_pd, core_pd;
99e6a4d2 RN	56
	57	static int omap3_idle_bm_check(void)
	58	{
20b01669 RN	59	if (!omap3_can_sleep())
20b01669 RN	60	return 1;
99e6a4d2 RN	61	return 0;
	62	}
	63
	64	/**
	65	* omap3_enter_idle - Programs OMAP3 to enter the specified state
	66	* @dev: cpuidle device
	67	* @state: The target state to be programmed
	68	*
	69	* Called from the CPUidle framework to program the device to the
	70	* specified target state selected by the governor.
	71	*/
	72	static int omap3_enter_idle(struct cpuidle_device *dev,
	73	struct cpuidle_state *state)
	74	{
	75	struct omap3_processor_cx *cx = cpuidle_get_statedata(state);
	76	struct timespec ts_preidle, ts_postidle, ts_idle;
	77
	78	current_cx_state = *cx;
	79
	80	/* Used to keep track of the total time in idle */
	81	getnstimeofday(&ts_preidle);
	82
	83	local_irq_disable();
	84	local_fiq_disable();
	85
20b01669 RN	86	set_pwrdm_state(mpu_pd, cx->mpu_state);
	87	set_pwrdm_state(core_pd, cx->core_state);
	88
	89	if (omap_irq_pending())
	90	goto return_sleep_time;
99e6a4d2 RN	91
	92	/* Execute ARM wfi */
	93	omap_sram_idle();
	94
20b01669	95	return_sleep_time:
99e6a4d2 RN	96	getnstimeofday(&ts_postidle);
	97	ts_idle = timespec_sub(ts_postidle, ts_preidle);
	98
	99	local_irq_enable();
	100	local_fiq_enable();
	101
20b01669	102	return (u32)timespec_to_ns(&ts_idle)/1000;
99e6a4d2 RN	103	}
	104
	105	/**
	106	* omap3_enter_idle_bm - Checks for any bus activity
	107	* @dev: cpuidle device
	108	* @state: The target state to be programmed
	109	*
	110	* Used for C states with CPUIDLE_FLAG_CHECK_BM flag set. This
	111	* function checks for any pending activity and then programs the
	112	* device to the specified or a safer state.
	113	*/
	114	static int omap3_enter_idle_bm(struct cpuidle_device *dev,
	115	struct cpuidle_state *state)
	116	{
	117	if ((state->flags & CPUIDLE_FLAG_CHECK_BM) && omap3_idle_bm_check()) {
	118	if (dev->safe_state)
	119	return dev->safe_state->enter(dev, dev->safe_state);
	120	}
	121	return omap3_enter_idle(dev, state);
	122	}
	123
	124	DEFINE_PER_CPU(struct cpuidle_device, omap3_idle_dev);
	125
	126	/* omap3_init_power_states - Initialises the OMAP3 specific C states.
	127	*
	128	* Below is the desciption of each C state.
	129	* C1 . MPU WFI + Core active
	130	* C2 . MPU CSWR + Core active
	131	* C3 . MPU OFF + Core active
	132	* C4 . MPU CSWR + Core CSWR
	133	* C5 . MPU OFF + Core CSWR
	134	* C6 . MPU OFF + Core OFF
	135	*/
	136	void omap_init_power_states(void)
	137	{
	138	/* C1 . MPU WFI + Core active */
	139	omap3_power_states[OMAP3_STATE_C1].valid = 1;
	140	omap3_power_states[OMAP3_STATE_C1].type = OMAP3_STATE_C1;
	141	omap3_power_states[OMAP3_STATE_C1].sleep_latency = 10;
	142	omap3_power_states[OMAP3_STATE_C1].wakeup_latency = 10;
	143	omap3_power_states[OMAP3_STATE_C1].threshold = 30;
	144	omap3_power_states[OMAP3_STATE_C1].mpu_state = PWRDM_POWER_ON;
	145	omap3_power_states[OMAP3_STATE_C1].core_state = PWRDM_POWER_ON;
	146	omap3_power_states[OMAP3_STATE_C1].flags = CPUIDLE_FLAG_TIME_VALID;
	147
	148	/* C2 . MPU CSWR + Core active */
	149	omap3_power_states[OMAP3_STATE_C2].valid = 1;
	150	omap3_power_states[OMAP3_STATE_C2].type = OMAP3_STATE_C2;
	151	omap3_power_states[OMAP3_STATE_C2].sleep_latency = 50;
	152	omap3_power_states[OMAP3_STATE_C2].wakeup_latency = 50;
	153	omap3_power_states[OMAP3_STATE_C2].threshold = 300;
	154	omap3_power_states[OMAP3_STATE_C2].mpu_state = PWRDM_POWER_RET;
	155	omap3_power_states[OMAP3_STATE_C2].core_state = PWRDM_POWER_ON;
	156	omap3_power_states[OMAP3_STATE_C2].flags = CPUIDLE_FLAG_TIME_VALID;
	157
	158	/* C3 . MPU OFF + Core active */
20b01669	159	omap3_power_states[OMAP3_STATE_C3].valid = 1;
99e6a4d2 RN	160	omap3_power_states[OMAP3_STATE_C3].type = OMAP3_STATE_C3;
	161	omap3_power_states[OMAP3_STATE_C3].sleep_latency = 1500;
	162	omap3_power_states[OMAP3_STATE_C3].wakeup_latency = 1800;
	163	omap3_power_states[OMAP3_STATE_C3].threshold = 4000;
	164	omap3_power_states[OMAP3_STATE_C3].mpu_state = PWRDM_POWER_OFF;
	165	omap3_power_states[OMAP3_STATE_C3].core_state = PWRDM_POWER_ON;
	166	omap3_power_states[OMAP3_STATE_C3].flags = CPUIDLE_FLAG_TIME_VALID;
	167
	168	/* C4 . MPU CSWR + Core CSWR*/
20b01669	169	omap3_power_states[OMAP3_STATE_C4].valid = 1;
99e6a4d2 RN	170	omap3_power_states[OMAP3_STATE_C4].type = OMAP3_STATE_C4;
	171	omap3_power_states[OMAP3_STATE_C4].sleep_latency = 2500;
	172	omap3_power_states[OMAP3_STATE_C4].wakeup_latency = 7500;
	173	omap3_power_states[OMAP3_STATE_C4].threshold = 12000;
	174	omap3_power_states[OMAP3_STATE_C4].mpu_state = PWRDM_POWER_RET;
	175	omap3_power_states[OMAP3_STATE_C4].core_state = PWRDM_POWER_RET;
	176	omap3_power_states[OMAP3_STATE_C4].flags = CPUIDLE_FLAG_TIME_VALID \|
	177	CPUIDLE_FLAG_CHECK_BM;
	178
	179	/* C5 . MPU OFF + Core CSWR */
20b01669	180	omap3_power_states[OMAP3_STATE_C5].valid = 1;
99e6a4d2 RN	181	omap3_power_states[OMAP3_STATE_C5].type = OMAP3_STATE_C5;
	182	omap3_power_states[OMAP3_STATE_C5].sleep_latency = 3000;
	183	omap3_power_states[OMAP3_STATE_C5].wakeup_latency = 8500;
	184	omap3_power_states[OMAP3_STATE_C5].threshold = 15000;
	185	omap3_power_states[OMAP3_STATE_C5].mpu_state = PWRDM_POWER_OFF;
	186	omap3_power_states[OMAP3_STATE_C5].core_state = PWRDM_POWER_RET;
	187	omap3_power_states[OMAP3_STATE_C5].flags = CPUIDLE_FLAG_TIME_VALID \|
	188	CPUIDLE_FLAG_CHECK_BM;
	189
	190	/* C6 . MPU OFF + Core OFF */
	191	omap3_power_states[OMAP3_STATE_C6].valid = 0;
	192	omap3_power_states[OMAP3_STATE_C6].type = OMAP3_STATE_C6;
	193	omap3_power_states[OMAP3_STATE_C6].sleep_latency = 10000;
	194	omap3_power_states[OMAP3_STATE_C6].wakeup_latency = 30000;
	195	omap3_power_states[OMAP3_STATE_C6].threshold = 300000;
	196	omap3_power_states[OMAP3_STATE_C6].mpu_state = PWRDM_POWER_OFF;
	197	omap3_power_states[OMAP3_STATE_C6].core_state = PWRDM_POWER_OFF;
	198	omap3_power_states[OMAP3_STATE_C6].flags = CPUIDLE_FLAG_TIME_VALID \|
	199	CPUIDLE_FLAG_CHECK_BM;
	200	}
	201
	202	struct cpuidle_driver omap3_idle_driver = {
	203	.name = "omap3_idle",
	204	.owner = THIS_MODULE,
	205	};
	206
	207	/**
	208	* omap3_idle_init - Init routine for OMAP3 idle
	209	*
	210	* Registers the OMAP3 specific cpuidle driver with the cpuidle
	211	* framework with the valid set of states.
	212	*/
	213	int omap3_idle_init(void)
	214	{
	215	int i, count = 0;
	216	struct omap3_processor_cx *cx;
	217	struct cpuidle_state *state;
	218	struct cpuidle_device *dev;
	219
	220	mpu_pd = pwrdm_lookup("mpu_pwrdm");
20b01669	221	core_pd = pwrdm_lookup("core_pwrdm");
99e6a4d2 RN	222
	223	omap_init_power_states();
	224	cpuidle_register_driver(&omap3_idle_driver);
	225
	226	dev = &per_cpu(omap3_idle_dev, smp_processor_id());
	227
	228	for (i = 1; i < OMAP3_MAX_STATES; i++) {
	229	cx = &omap3_power_states[i];
	230	state = &dev->states[count];
	231
	232	if (!cx->valid)
	233	continue;
	234	cpuidle_set_statedata(state, cx);
	235	state->exit_latency = cx->sleep_latency + cx->wakeup_latency;
	236	state->target_residency = cx->threshold;
	237	state->flags = cx->flags;
	238	state->enter = (state->flags & CPUIDLE_FLAG_CHECK_BM) ?
	239	omap3_enter_idle_bm : omap3_enter_idle;
	240	if (cx->type == OMAP3_STATE_C1)
	241	dev->safe_state = state;
	242	sprintf(state->name, "C%d", count+1);
	243	count++;
	244	}
	245
	246	if (!count)
	247	return -EINVAL;
	248	dev->state_count = count;
	249
	250	if (cpuidle_register_device(dev)) {
	251	printk(KERN_ERR "%s: CPUidle register device failed\n",
	252	__func__);
	253	return -EIO;
	254	}
	255
	256	return 0;
	257	}
	258	device_initcall(omap3_idle_init);
	259	#endif /* CONFIG_CPU_IDLE */