[deliverable/linux.git] / arch / arm / mach-omap2 / cpuidle34xx.c

/*
 * linux/arch/arm/mach-omap2/cpuidle34xx.c
 *
 * OMAP3 CPU IDLE Routines
 *
 * Copyright (C) 2008 Texas Instruments, Inc.
 * Rajendra Nayak <rnayak@ti.com>
 *
 * Copyright (C) 2007 Texas Instruments, Inc.
 * Karthik Dasu <karthik-dp@ti.com>
 *
 * Copyright (C) 2006 Nokia Corporation
 * Tony Lindgren <tony@atomide.com>
 *
 * Copyright (C) 2005 Texas Instruments, Inc.
 * Richard Woodruff <r-woodruff2@ti.com>
 *
 * Based on pm.c for omap2
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/sched.h>
#include <linux/cpuidle.h>

#include <plat/prcm.h>
#include <plat/irqs.h>
#include "powerdomain.h"
#include "clockdomain.h"
#include <plat/serial.h>

#include "pm.h"
#include "control.h"

#ifdef CONFIG_CPU_IDLE

/*
 * The latencies/thresholds for various C states have
 * to be configured from the respective board files.
 * These are some default values (which might not provide
 * the best power savings) used on boards which do not
 * pass these details from the board file.
 */
static struct cpuidle_params cpuidle_params_table[] = {
	/* C1 */
	{2 + 2, 5, 1},
	/* C2 */
	{10 + 10, 30, 1},
	/* C3 */
	{50 + 50, 300, 1},
	/* C4 */
	{1500 + 1800, 4000, 1},
	/* C5 */
	{2500 + 7500, 12000, 1},
	/* C6 */
	{3000 + 8500, 15000, 1},
	/* C7 */
	{10000 + 30000, 300000, 1},
};
#define OMAP3_NUM_STATES ARRAY_SIZE(cpuidle_params_table)

/* Mach specific information to be recorded in the C-state driver_data */
struct omap3_idle_statedata {
	u32 mpu_state;
	u32 core_state;
	u8 valid;
};
struct omap3_idle_statedata omap3_idle_data[OMAP3_NUM_STATES];

struct powerdomain *mpu_pd, *core_pd, *per_pd, *cam_pd;

static int _cpuidle_allow_idle(struct powerdomain *pwrdm,
				struct clockdomain *clkdm)
{
	clkdm_allow_idle(clkdm);
	return 0;
}

static int _cpuidle_deny_idle(struct powerdomain *pwrdm,
				struct clockdomain *clkdm)
{
	clkdm_deny_idle(clkdm);
	return 0;
}

/**
 * omap3_enter_idle - Programs OMAP3 to enter the specified state
 * @dev: cpuidle device
 * @index: the index of state to be entered
 *
 * Called from the CPUidle framework to program the device to the
 * specified target state selected by the governor.
 */
static int omap3_enter_idle(struct cpuidle_device *dev,
				int index)
{
	struct omap3_idle_statedata *cx =
			cpuidle_get_statedata(&dev->states_usage[index]);
	struct timespec ts_preidle, ts_postidle, ts_idle;
	u32 mpu_state = cx->mpu_state, core_state = cx->core_state;
	int idle_time;

	/* Used to keep track of the total time in idle */
	getnstimeofday(&ts_preidle);

	local_irq_disable();
	local_fiq_disable();

	pwrdm_set_next_pwrst(mpu_pd, mpu_state);
	pwrdm_set_next_pwrst(core_pd, core_state);

	if (omap_irq_pending() || need_resched())
		goto return_sleep_time;

	/* Deny idle for C1 */
	if (index == 0) {
		pwrdm_for_each_clkdm(mpu_pd, _cpuidle_deny_idle);
		pwrdm_for_each_clkdm(core_pd, _cpuidle_deny_idle);
	}

	/* Execute ARM wfi */
	omap_sram_idle();

	/* Re-allow idle for C1 */
	if (index == 0) {
		pwrdm_for_each_clkdm(mpu_pd, _cpuidle_allow_idle);
		pwrdm_for_each_clkdm(core_pd, _cpuidle_allow_idle);
	}

return_sleep_time:
	getnstimeofday(&ts_postidle);
	ts_idle = timespec_sub(ts_postidle, ts_preidle);

	local_irq_enable();
	local_fiq_enable();

	idle_time = ts_idle.tv_nsec / NSEC_PER_USEC + ts_idle.tv_sec * \
								USEC_PER_SEC;

	/* Update cpuidle counters */
	dev->last_residency = idle_time;

	return index;
}

/**
 * next_valid_state - Find next valid C-state
 * @dev: cpuidle device
 * @index: Index of currently selected c-state
 *
 * If the state corresponding to index is valid, index is returned back
 * to the caller. Else, this function searches for a lower c-state which is
 * still valid (as defined in omap3_power_states[]) and returns its index.
 *
 * A state is valid if the 'valid' field is enabled and
 * if it satisfies the enable_off_mode condition.
 */
static int next_valid_state(struct cpuidle_device *dev,
				int index)
{
	struct cpuidle_state_usage *curr_usage = &dev->states_usage[index];
	struct cpuidle_state *curr = &dev->states[index];
	struct omap3_idle_statedata *cx = cpuidle_get_statedata(curr_usage);
	u32 mpu_deepest_state = PWRDM_POWER_RET;
	u32 core_deepest_state = PWRDM_POWER_RET;
	int next_index = -1;

	if (enable_off_mode) {
		mpu_deepest_state = PWRDM_POWER_OFF;
		/*
		 * Erratum i583: valable for ES rev < Es1.2 on 3630.
		 * CORE OFF mode is not supported in a stable form, restrict
		 * instead the CORE state to RET.
		 */
		if (!IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583))
			core_deepest_state = PWRDM_POWER_OFF;
	}

	/* Check if current state is valid */
	if ((cx->valid) &&
	    (cx->mpu_state >= mpu_deepest_state) &&
	    (cx->core_state >= core_deepest_state)) {
		return index;
	} else {
		int idx = OMAP3_NUM_STATES - 1;

		/* Reach the current state starting at highest C-state */
		for (; idx >= 0; idx--) {
			if (&dev->states[idx] == curr) {
				next_index = idx;
				break;
			}
		}

		/* Should never hit this condition */
		WARN_ON(next_index == -1);

		/*
		 * Drop to next valid state.
		 * Start search from the next (lower) state.
		 */
		idx--;
		for (; idx >= 0; idx--) {
			cx = cpuidle_get_statedata(&dev->states_usage[idx]);
			if ((cx->valid) &&
			    (cx->mpu_state >= mpu_deepest_state) &&
			    (cx->core_state >= core_deepest_state)) {
				next_index = idx;
				break;
			}
		}
		/*
		 * C1 is always valid.
		 * So, no need to check for 'next_index == -1' outside
		 * this loop.
		 */
	}

	return next_index;
}

/**
 * omap3_enter_idle_bm - Checks for any bus activity
 * @dev: cpuidle device
 * @index: array index of target state to be programmed
 *
 * This function checks for any pending activity and then programs
 * the device to the specified or a safer state.
 */
static int omap3_enter_idle_bm(struct cpuidle_device *dev,
			       int index)
{
	int new_state_idx;
	u32 core_next_state, per_next_state = 0, per_saved_state = 0, cam_state;
	struct omap3_idle_statedata *cx;
	int ret;

	if (!omap3_can_sleep()) {
		new_state_idx = dev->safe_state_index;
		goto select_state;
	}

	/*
	 * Prevent idle completely if CAM is active.
	 * CAM does not have wakeup capability in OMAP3.
	 */
	cam_state = pwrdm_read_pwrst(cam_pd);
	if (cam_state == PWRDM_POWER_ON) {
		new_state_idx = dev->safe_state_index;
		goto select_state;
	}

	/*
	 * FIXME: we currently manage device-specific idle states
	 *        for PER and CORE in combination with CPU-specific
	 *        idle states.  This is wrong, and device-specific
	 *        idle management needs to be separated out into
	 *        its own code.
	 */

	/*
	 * Prevent PER off if CORE is not in retention or off as this
	 * would disable PER wakeups completely.
	 */
	cx = cpuidle_get_statedata(&dev->states_usage[index]);
	core_next_state = cx->core_state;
	per_next_state = per_saved_state = pwrdm_read_next_pwrst(per_pd);
	if ((per_next_state == PWRDM_POWER_OFF) &&
	    (core_next_state > PWRDM_POWER_RET))
		per_next_state = PWRDM_POWER_RET;

	/* Are we changing PER target state? */
	if (per_next_state != per_saved_state)
		pwrdm_set_next_pwrst(per_pd, per_next_state);

	new_state_idx = next_valid_state(dev, index);

select_state:
	ret = omap3_enter_idle(dev, new_state_idx);

	/* Restore original PER state if it was modified */
	if (per_next_state != per_saved_state)
		pwrdm_set_next_pwrst(per_pd, per_saved_state);

	return ret;
}

DEFINE_PER_CPU(struct cpuidle_device, omap3_idle_dev);

void omap3_pm_init_cpuidle(struct cpuidle_params *cpuidle_board_params)
{
	int i;

	if (!cpuidle_board_params)
		return;

	for (i = 0; i < OMAP3_NUM_STATES; i++) {
		cpuidle_params_table[i].valid =	cpuidle_board_params[i].valid;
		cpuidle_params_table[i].exit_latency =
			cpuidle_board_params[i].exit_latency;
		cpuidle_params_table[i].target_residency =
			cpuidle_board_params[i].target_residency;
	}
	return;
}

struct cpuidle_driver omap3_idle_driver = {
	.name = 	"omap3_idle",
	.owner = 	THIS_MODULE,
};

/* Helper to fill the C-state common data and register the driver_data */
static inline struct omap3_idle_statedata *_fill_cstate(
					struct cpuidle_device *dev,
					int idx, const char *descr)
{
	struct omap3_idle_statedata *cx = &omap3_idle_data[idx];
	struct cpuidle_state *state = &dev->states[idx];
	struct cpuidle_state_usage *state_usage = &dev->states_usage[idx];

	state->exit_latency	= cpuidle_params_table[idx].exit_latency;
	state->target_residency	= cpuidle_params_table[idx].target_residency;
	state->flags		= CPUIDLE_FLAG_TIME_VALID;
	state->enter		= omap3_enter_idle_bm;
	cx->valid		= cpuidle_params_table[idx].valid;
	sprintf(state->name, "C%d", idx + 1);
	strncpy(state->desc, descr, CPUIDLE_DESC_LEN);
	cpuidle_set_statedata(state_usage, cx);

	return cx;
}

/**
 * omap3_idle_init - Init routine for OMAP3 idle
 *
 * Registers the OMAP3 specific cpuidle driver to the cpuidle
 * framework with the valid set of states.
 */
int __init omap3_idle_init(void)
{
	struct cpuidle_device *dev;
	struct omap3_idle_statedata *cx;

	mpu_pd = pwrdm_lookup("mpu_pwrdm");
	core_pd = pwrdm_lookup("core_pwrdm");
	per_pd = pwrdm_lookup("per_pwrdm");
	cam_pd = pwrdm_lookup("cam_pwrdm");

	cpuidle_register_driver(&omap3_idle_driver);
	dev = &per_cpu(omap3_idle_dev, smp_processor_id());
	dev->safe_state_index = -1;

	/* C1 . MPU WFI + Core active */
	cx = _fill_cstate(dev, 0, "MPU ON + CORE ON");
	(&dev->states[0])->enter = omap3_enter_idle;
	dev->safe_state_index = 0;
	cx->valid = 1;	/* C1 is always valid */
	cx->mpu_state = PWRDM_POWER_ON;
	cx->core_state = PWRDM_POWER_ON;

	/* C2 . MPU WFI + Core inactive */
	cx = _fill_cstate(dev, 1, "MPU ON + CORE ON");
	cx->mpu_state = PWRDM_POWER_ON;
	cx->core_state = PWRDM_POWER_ON;

	/* C3 . MPU CSWR + Core inactive */
	cx = _fill_cstate(dev, 2, "MPU RET + CORE ON");
	cx->mpu_state = PWRDM_POWER_RET;
	cx->core_state = PWRDM_POWER_ON;

	/* C4 . MPU OFF + Core inactive */
	cx = _fill_cstate(dev, 3, "MPU OFF + CORE ON");
	cx->mpu_state = PWRDM_POWER_OFF;
	cx->core_state = PWRDM_POWER_ON;

	/* C5 . MPU RET + Core RET */
	cx = _fill_cstate(dev, 4, "MPU RET + CORE RET");
	cx->mpu_state = PWRDM_POWER_RET;
	cx->core_state = PWRDM_POWER_RET;

	/* C6 . MPU OFF + Core RET */
	cx = _fill_cstate(dev, 5, "MPU OFF + CORE RET");
	cx->mpu_state = PWRDM_POWER_OFF;
	cx->core_state = PWRDM_POWER_RET;

	/* C7 . MPU OFF + Core OFF */
	cx = _fill_cstate(dev, 6, "MPU OFF + CORE OFF");
	/*
	 * Erratum i583: implementation for ES rev < Es1.2 on 3630. We cannot
	 * enable OFF mode in a stable form for previous revisions.
	 * We disable C7 state as a result.
	 */
	if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583)) {
		cx->valid = 0;
		pr_warn("%s: core off state C7 disabled due to i583\n",
			__func__);
	}
	cx->mpu_state = PWRDM_POWER_OFF;
	cx->core_state = PWRDM_POWER_OFF;

	dev->state_count = OMAP3_NUM_STATES;
	if (cpuidle_register_device(dev)) {
		printk(KERN_ERR "%s: CPUidle register device failed\n",
		       __func__);
		return -EIO;
	}

	return 0;
}
#else
int __init omap3_idle_init(void)
{
	return 0;
}
#endif /* CONFIG_CPU_IDLE */
Commit	Line	Data
99e6a4d2 RN	1	/*
	2	* linux/arch/arm/mach-omap2/cpuidle34xx.c
	3	*
	4	* OMAP3 CPU IDLE Routines
	5	*
	6	* Copyright (C) 2008 Texas Instruments, Inc.
	7	* Rajendra Nayak <rnayak@ti.com>
	8	*
	9	* Copyright (C) 2007 Texas Instruments, Inc.
	10	* Karthik Dasu <karthik-dp@ti.com>
	11	*
	12	* Copyright (C) 2006 Nokia Corporation
	13	* Tony Lindgren <tony@atomide.com>
	14	*
	15	* Copyright (C) 2005 Texas Instruments, Inc.
	16	* Richard Woodruff <r-woodruff2@ti.com>
	17	*
	18	* Based on pm.c for omap2
	19	*
	20	* This program is free software; you can redistribute it and/or modify
	21	* it under the terms of the GNU General Public License version 2 as
	22	* published by the Free Software Foundation.
	23	*/
	24
cf22854c	25	#include <linux/sched.h>
99e6a4d2 RN	26	#include <linux/cpuidle.h>
	27
	28	#include <plat/prcm.h>
20b01669	29	#include <plat/irqs.h>
72e06d08	30	#include "powerdomain.h"
1540f214	31	#include "clockdomain.h"
0f724ed9	32	#include <plat/serial.h>
99e6a4d2	33
c98e2230	34	#include "pm.h"
4814ced5	35	#include "control.h"
c98e2230	36
99e6a4d2 RN	37	#ifdef CONFIG_CPU_IDLE
99e6a4d2 RN	38
bb4de3df KH	39	/*
	40	* The latencies/thresholds for various C states have
	41	* to be configured from the respective board files.
	42	* These are some default values (which might not provide
	43	* the best power savings) used on boards which do not
	44	* pass these details from the board file.
	45	*/
	46	static struct cpuidle_params cpuidle_params_table[] = {
	47	/* C1 */
866ba0ef	48	{2 + 2, 5, 1},
bb4de3df	49	/* C2 */
866ba0ef	50	{10 + 10, 30, 1},
bb4de3df	51	/* C3 */
866ba0ef	52	{50 + 50, 300, 1},
bb4de3df	53	/* C4 */
866ba0ef	54	{1500 + 1800, 4000, 1},
bb4de3df	55	/* C5 */
866ba0ef	56	{2500 + 7500, 12000, 1},
bb4de3df	57	/* C6 */
866ba0ef	58	{3000 + 8500, 15000, 1},
bb4de3df	59	/* C7 */
866ba0ef	60	{10000 + 30000, 300000, 1},
bb4de3df	61	};
badc303a JP	62	#define OMAP3_NUM_STATES ARRAY_SIZE(cpuidle_params_table)
	63
	64	/* Mach specific information to be recorded in the C-state driver_data */
	65	struct omap3_idle_statedata {
	66	u32 mpu_state;
	67	u32 core_state;
	68	u8 valid;
	69	};
	70	struct omap3_idle_statedata omap3_idle_data[OMAP3_NUM_STATES];
	71
	72	struct powerdomain mpu_pd, core_pd, per_pd, cam_pd;
bb4de3df	73
06d8f065 PDS	74	static int _cpuidle_allow_idle(struct powerdomain *pwrdm,
	75	struct clockdomain *clkdm)
	76	{
5cd1937b	77	clkdm_allow_idle(clkdm);
06d8f065 PDS	78	return 0;
	79	}
	80
	81	static int _cpuidle_deny_idle(struct powerdomain *pwrdm,
	82	struct clockdomain *clkdm)
	83	{
5cd1937b	84	clkdm_deny_idle(clkdm);
06d8f065 PDS	85	return 0;
	86	}
	87
99e6a4d2 RN	88	/**
	89	* omap3_enter_idle - Programs OMAP3 to enter the specified state
	90	* @dev: cpuidle device
e978aa7d	91	* @index: the index of state to be entered
99e6a4d2 RN	92	*
	93	* Called from the CPUidle framework to program the device to the
	94	* specified target state selected by the governor.
	95	*/
	96	static int omap3_enter_idle(struct cpuidle_device *dev,
e978aa7d	97	int index)
99e6a4d2	98	{
e978aa7d	99	struct omap3_idle_statedata *cx =
4202735e	100	cpuidle_get_statedata(&dev->states_usage[index]);
99e6a4d2	101	struct timespec ts_preidle, ts_postidle, ts_idle;
c98e2230	102	u32 mpu_state = cx->mpu_state, core_state = cx->core_state;
e978aa7d	103	int idle_time;
99e6a4d2	104
99e6a4d2 RN	105	/* Used to keep track of the total time in idle */
	106	getnstimeofday(&ts_preidle);
	107
	108	local_irq_disable();
	109	local_fiq_disable();
	110
7139178e JH	111	pwrdm_set_next_pwrst(mpu_pd, mpu_state);
7139178e JH	112	pwrdm_set_next_pwrst(core_pd, core_state);
20b01669	113
cf22854c	114	if (omap_irq_pending() \|\| need_resched())
20b01669	115	goto return_sleep_time;
99e6a4d2	116
badc303a	117	/* Deny idle for C1 */
e978aa7d	118	if (index == 0) {
06d8f065 PDS	119	pwrdm_for_each_clkdm(mpu_pd, _cpuidle_deny_idle);
	120	pwrdm_for_each_clkdm(core_pd, _cpuidle_deny_idle);
	121	}
	122
99e6a4d2 RN	123	/* Execute ARM wfi */
	124	omap_sram_idle();
	125
badc303a	126	/* Re-allow idle for C1 */
e978aa7d	127	if (index == 0) {
06d8f065 PDS	128	pwrdm_for_each_clkdm(mpu_pd, _cpuidle_allow_idle);
	129	pwrdm_for_each_clkdm(core_pd, _cpuidle_allow_idle);
	130	}
	131
20b01669	132	return_sleep_time:
99e6a4d2 RN	133	getnstimeofday(&ts_postidle);
	134	ts_idle = timespec_sub(ts_postidle, ts_preidle);
	135
	136	local_irq_enable();
	137	local_fiq_enable();
	138
e978aa7d DD	139	idle_time = ts_idle.tv_nsec / NSEC_PER_USEC + ts_idle.tv_sec * \
	140	USEC_PER_SEC;
	141
	142	/* Update cpuidle counters */
	143	dev->last_residency = idle_time;
	144
	145	return index;
99e6a4d2 RN	146	}
99e6a4d2 RN	147
6af83b38	148	/**
04908918	149	* next_valid_state - Find next valid C-state
6af83b38	150	* @dev: cpuidle device
e978aa7d	151	* @index: Index of currently selected c-state
6af83b38	152	*
e978aa7d DD	153	* If the state corresponding to index is valid, index is returned back
	154	* to the caller. Else, this function searches for a lower c-state which is
	155	* still valid (as defined in omap3_power_states[]) and returns its index.
04908918 JP	156	*
	157	* A state is valid if the 'valid' field is enabled and
	158	* if it satisfies the enable_off_mode condition.
6af83b38	159	*/
e978aa7d DD	160	static int next_valid_state(struct cpuidle_device *dev,
e978aa7d DD	161	int index)
6af83b38	162	{
4202735e	163	struct cpuidle_state_usage *curr_usage = &dev->states_usage[index];
e978aa7d	164	struct cpuidle_state *curr = &dev->states[index];
4202735e	165	struct omap3_idle_statedata *cx = cpuidle_get_statedata(curr_usage);
04908918 JP	166	u32 mpu_deepest_state = PWRDM_POWER_RET;
04908918 JP	167	u32 core_deepest_state = PWRDM_POWER_RET;
e978aa7d	168	int next_index = -1;
04908918 JP	169
	170	if (enable_off_mode) {
	171	mpu_deepest_state = PWRDM_POWER_OFF;
	172	/*
	173	* Erratum i583: valable for ES rev < Es1.2 on 3630.
	174	* CORE OFF mode is not supported in a stable form, restrict
	175	* instead the CORE state to RET.
	176	*/
	177	if (!IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583))
	178	core_deepest_state = PWRDM_POWER_OFF;
	179	}
6af83b38 SP	180
6af83b38 SP	181	/* Check if current state is valid */
04908918 JP	182	if ((cx->valid) &&
	183	(cx->mpu_state >= mpu_deepest_state) &&
	184	(cx->core_state >= core_deepest_state)) {
e978aa7d	185	return index;
6af83b38	186	} else {
badc303a	187	int idx = OMAP3_NUM_STATES - 1;
6af83b38	188
c6cd91de	189	/* Reach the current state starting at highest C-state */
badc303a	190	for (; idx >= 0; idx--) {
6af83b38	191	if (&dev->states[idx] == curr) {
e978aa7d	192	next_index = idx;
6af83b38 SP	193	break;
	194	}
	195	}
	196
c6cd91de	197	/* Should never hit this condition */
e978aa7d	198	WARN_ON(next_index == -1);
6af83b38 SP	199
	200	/*
	201	* Drop to next valid state.
	202	* Start search from the next (lower) state.
	203	*/
	204	idx--;
badc303a	205	for (; idx >= 0; idx--) {
4202735e	206	cx = cpuidle_get_statedata(&dev->states_usage[idx]);
04908918 JP	207	if ((cx->valid) &&
	208	(cx->mpu_state >= mpu_deepest_state) &&
	209	(cx->core_state >= core_deepest_state)) {
e978aa7d	210	next_index = idx;
6af83b38 SP	211	break;
	212	}
	213	}
	214	/*
badc303a	215	* C1 is always valid.
e978aa7d DD	216	* So, no need to check for 'next_index == -1' outside
e978aa7d DD	217	* this loop.
6af83b38 SP	218	*/
	219	}
	220
e978aa7d	221	return next_index;
6af83b38 SP	222	}
6af83b38 SP	223
99e6a4d2 RN	224	/**
	225	* omap3_enter_idle_bm - Checks for any bus activity
	226	* @dev: cpuidle device
e978aa7d	227	* @index: array index of target state to be programmed
99e6a4d2	228	*
badc303a JP	229	* This function checks for any pending activity and then programs
badc303a JP	230	* the device to the specified or a safer state.
99e6a4d2 RN	231	*/
99e6a4d2 RN	232	static int omap3_enter_idle_bm(struct cpuidle_device *dev,
e978aa7d	233	int index)
99e6a4d2	234	{
e978aa7d	235	int new_state_idx;
c6cd91de	236	u32 core_next_state, per_next_state = 0, per_saved_state = 0, cam_state;
badc303a	237	struct omap3_idle_statedata *cx;
e7410cf7	238	int ret;
0f724ed9	239
c6cd91de	240	if (!omap3_can_sleep()) {
e978aa7d	241	new_state_idx = dev->safe_state_index;
e7410cf7 KH	242	goto select_state;
	243	}
	244
e7410cf7 KH	245	/*
	246	* Prevent idle completely if CAM is active.
	247	* CAM does not have wakeup capability in OMAP3.
	248	*/
	249	cam_state = pwrdm_read_pwrst(cam_pd);
	250	if (cam_state == PWRDM_POWER_ON) {
e978aa7d	251	new_state_idx = dev->safe_state_index;
e7410cf7 KH	252	goto select_state;
	253	}
	254
c6cd91de JP	255	/*
	256	* FIXME: we currently manage device-specific idle states
	257	* for PER and CORE in combination with CPU-specific
	258	* idle states. This is wrong, and device-specific
	259	* idle management needs to be separated out into
	260	* its own code.
	261	*/
	262
e7410cf7 KH	263	/*
	264	* Prevent PER off if CORE is not in retention or off as this
	265	* would disable PER wakeups completely.
	266	*/
4202735e	267	cx = cpuidle_get_statedata(&dev->states_usage[index]);
c6cd91de	268	core_next_state = cx->core_state;
e7410cf7 KH	269	per_next_state = per_saved_state = pwrdm_read_next_pwrst(per_pd);
e7410cf7 KH	270	if ((per_next_state == PWRDM_POWER_OFF) &&
65707fb3	271	(core_next_state > PWRDM_POWER_RET))
e7410cf7	272	per_next_state = PWRDM_POWER_RET;
0f724ed9	273
e7410cf7 KH	274	/* Are we changing PER target state? */
	275	if (per_next_state != per_saved_state)
	276	pwrdm_set_next_pwrst(per_pd, per_next_state);
	277
e978aa7d	278	new_state_idx = next_valid_state(dev, index);
c6cd91de	279
e7410cf7	280	select_state:
e978aa7d	281	ret = omap3_enter_idle(dev, new_state_idx);
e7410cf7 KH	282
	283	/* Restore original PER state if it was modified */
	284	if (per_next_state != per_saved_state)
	285	pwrdm_set_next_pwrst(per_pd, per_saved_state);
	286
	287	return ret;
99e6a4d2 RN	288	}
	289
	290	DEFINE_PER_CPU(struct cpuidle_device, omap3_idle_dev);
	291
bb4de3df KH	292	void omap3_pm_init_cpuidle(struct cpuidle_params *cpuidle_board_params)
	293	{
	294	int i;
	295
	296	if (!cpuidle_board_params)
	297	return;
	298
badc303a JP	299	for (i = 0; i < OMAP3_NUM_STATES; i++) {
badc303a JP	300	cpuidle_params_table[i].valid = cpuidle_board_params[i].valid;
866ba0ef JP	301	cpuidle_params_table[i].exit_latency =
	302	cpuidle_board_params[i].exit_latency;
	303	cpuidle_params_table[i].target_residency =
	304	cpuidle_board_params[i].target_residency;
bb4de3df KH	305	}
	306	return;
	307	}
	308
99e6a4d2 RN	309	struct cpuidle_driver omap3_idle_driver = {
	310	.name = "omap3_idle",
	311	.owner = THIS_MODULE,
	312	};
	313
c6cd91de	314	/* Helper to fill the C-state common data and register the driver_data */
badc303a JP	315	static inline struct omap3_idle_statedata *_fill_cstate(
	316	struct cpuidle_device *dev,
	317	int idx, const char *descr)
	318	{
	319	struct omap3_idle_statedata *cx = &omap3_idle_data[idx];
	320	struct cpuidle_state *state = &dev->states[idx];
4202735e	321	struct cpuidle_state_usage *state_usage = &dev->states_usage[idx];
badc303a JP	322
	323	state->exit_latency = cpuidle_params_table[idx].exit_latency;
	324	state->target_residency = cpuidle_params_table[idx].target_residency;
	325	state->flags = CPUIDLE_FLAG_TIME_VALID;
	326	state->enter = omap3_enter_idle_bm;
	327	cx->valid = cpuidle_params_table[idx].valid;
	328	sprintf(state->name, "C%d", idx + 1);
	329	strncpy(state->desc, descr, CPUIDLE_DESC_LEN);
4202735e	330	cpuidle_set_statedata(state_usage, cx);
badc303a JP	331
	332	return cx;
	333	}
	334
99e6a4d2 RN	335	/**
	336	* omap3_idle_init - Init routine for OMAP3 idle
	337	*
badc303a	338	* Registers the OMAP3 specific cpuidle driver to the cpuidle
99e6a4d2 RN	339	* framework with the valid set of states.
99e6a4d2 RN	340	*/
0343371e	341	int __init omap3_idle_init(void)
99e6a4d2	342	{
99e6a4d2	343	struct cpuidle_device *dev;
badc303a	344	struct omap3_idle_statedata *cx;
99e6a4d2 RN	345
99e6a4d2 RN	346	mpu_pd = pwrdm_lookup("mpu_pwrdm");
20b01669	347	core_pd = pwrdm_lookup("core_pwrdm");
e7410cf7 KH	348	per_pd = pwrdm_lookup("per_pwrdm");
e7410cf7 KH	349	cam_pd = pwrdm_lookup("cam_pwrdm");
99e6a4d2	350
99e6a4d2	351	cpuidle_register_driver(&omap3_idle_driver);
99e6a4d2	352	dev = &per_cpu(omap3_idle_dev, smp_processor_id());
e978aa7d	353	dev->safe_state_index = -1;
99e6a4d2	354
badc303a JP	355	/* C1 . MPU WFI + Core active */
	356	cx = _fill_cstate(dev, 0, "MPU ON + CORE ON");
	357	(&dev->states[0])->enter = omap3_enter_idle;
e978aa7d	358	dev->safe_state_index = 0;
badc303a JP	359	cx->valid = 1; /* C1 is always valid */
	360	cx->mpu_state = PWRDM_POWER_ON;
	361	cx->core_state = PWRDM_POWER_ON;
	362
	363	/* C2 . MPU WFI + Core inactive */
	364	cx = _fill_cstate(dev, 1, "MPU ON + CORE ON");
	365	cx->mpu_state = PWRDM_POWER_ON;
	366	cx->core_state = PWRDM_POWER_ON;
	367
	368	/* C3 . MPU CSWR + Core inactive */
	369	cx = _fill_cstate(dev, 2, "MPU RET + CORE ON");
	370	cx->mpu_state = PWRDM_POWER_RET;
	371	cx->core_state = PWRDM_POWER_ON;
	372
	373	/* C4 . MPU OFF + Core inactive */
	374	cx = _fill_cstate(dev, 3, "MPU OFF + CORE ON");
	375	cx->mpu_state = PWRDM_POWER_OFF;
	376	cx->core_state = PWRDM_POWER_ON;
	377
	378	/* C5 . MPU RET + Core RET */
	379	cx = _fill_cstate(dev, 4, "MPU RET + CORE RET");
	380	cx->mpu_state = PWRDM_POWER_RET;
	381	cx->core_state = PWRDM_POWER_RET;
99e6a4d2	382
badc303a JP	383	/* C6 . MPU OFF + Core RET */
	384	cx = _fill_cstate(dev, 5, "MPU OFF + CORE RET");
	385	cx->mpu_state = PWRDM_POWER_OFF;
	386	cx->core_state = PWRDM_POWER_RET;
	387
	388	/* C7 . MPU OFF + Core OFF */
	389	cx = _fill_cstate(dev, 6, "MPU OFF + CORE OFF");
	390	/*
	391	* Erratum i583: implementation for ES rev < Es1.2 on 3630. We cannot
	392	* enable OFF mode in a stable form for previous revisions.
	393	* We disable C7 state as a result.
	394	*/
	395	if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583)) {
	396	cx->valid = 0;
	397	pr_warn("%s: core off state C7 disabled due to i583\n",
	398	__func__);
	399	}
	400	cx->mpu_state = PWRDM_POWER_OFF;
	401	cx->core_state = PWRDM_POWER_OFF;
99e6a4d2	402
badc303a	403	dev->state_count = OMAP3_NUM_STATES;
99e6a4d2 RN	404	if (cpuidle_register_device(dev)) {
	405	printk(KERN_ERR "%s: CPUidle register device failed\n",
	406	__func__);
	407	return -EIO;
	408	}
	409
	410	return 0;
	411	}
0343371e KJ	412	#else
	413	int __init omap3_idle_init(void)
	414	{
	415	return 0;
	416	}
99e6a4d2	417	#endif /* CONFIG_CPU_IDLE */