[deliverable/linux.git] / arch / arm / mach-omap2 / cpuidle34xx.c

/*
 * linux/arch/arm/mach-omap2/cpuidle34xx.c
 *
 * OMAP3 CPU IDLE Routines
 *
 * Copyright (C) 2008 Texas Instruments, Inc.
 * Rajendra Nayak <rnayak@ti.com>
 *
 * Copyright (C) 2007 Texas Instruments, Inc.
 * Karthik Dasu <karthik-dp@ti.com>
 *
 * Copyright (C) 2006 Nokia Corporation
 * Tony Lindgren <tony@atomide.com>
 *
 * Copyright (C) 2005 Texas Instruments, Inc.
 * Richard Woodruff <r-woodruff2@ti.com>
 *
 * Based on pm.c for omap2
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/sched.h>
#include <linux/cpuidle.h>
#include <linux/export.h>
#include <linux/cpu_pm.h>

#include <plat/prcm.h>
#include <plat/irqs.h>
#include "powerdomain.h"
#include "clockdomain.h"

#include "pm.h"
#include "control.h"
#include "common.h"

#ifdef CONFIG_CPU_IDLE

/*
 * The latencies/thresholds for various C states have
 * to be configured from the respective board files.
 * These are some default values (which might not provide
 * the best power savings) used on boards which do not
 * pass these details from the board file.
 */
static struct cpuidle_params cpuidle_params_table[] = {
	/* C1 */
	{2 + 2, 5, 1},
	/* C2 */
	{10 + 10, 30, 1},
	/* C3 */
	{50 + 50, 300, 1},
	/* C4 */
	{1500 + 1800, 4000, 1},
	/* C5 */
	{2500 + 7500, 12000, 1},
	/* C6 */
	{3000 + 8500, 15000, 1},
	/* C7 */
	{10000 + 30000, 300000, 1},
};
#define OMAP3_NUM_STATES ARRAY_SIZE(cpuidle_params_table)

/* Mach specific information to be recorded in the C-state driver_data */
struct omap3_idle_statedata {
	u32 mpu_state;
	u32 core_state;
	u8 valid;
};
struct omap3_idle_statedata omap3_idle_data[OMAP3_NUM_STATES];

struct powerdomain *mpu_pd, *core_pd, *per_pd, *cam_pd;

static int _cpuidle_allow_idle(struct powerdomain *pwrdm,
				struct clockdomain *clkdm)
{
	clkdm_allow_idle(clkdm);
	return 0;
}

static int _cpuidle_deny_idle(struct powerdomain *pwrdm,
				struct clockdomain *clkdm)
{
	clkdm_deny_idle(clkdm);
	return 0;
}

static int __omap3_enter_idle(struct cpuidle_device *dev,
				struct cpuidle_driver *drv,
				int index)
{
	struct omap3_idle_statedata *cx =
			cpuidle_get_statedata(&dev->states_usage[index]);
	u32 mpu_state = cx->mpu_state, core_state = cx->core_state;

	local_fiq_disable();

	pwrdm_set_next_pwrst(mpu_pd, mpu_state);
	pwrdm_set_next_pwrst(core_pd, core_state);

	if (omap_irq_pending() || need_resched())
		goto return_sleep_time;

	/* Deny idle for C1 */
	if (index == 0) {
		pwrdm_for_each_clkdm(mpu_pd, _cpuidle_deny_idle);
		pwrdm_for_each_clkdm(core_pd, _cpuidle_deny_idle);
	}

	/*
	 * Call idle CPU PM enter notifier chain so that
	 * VFP context is saved.
	 */
	if (mpu_state == PWRDM_POWER_OFF)
		cpu_pm_enter();

	/* Execute ARM wfi */
	omap_sram_idle();

	/*
	 * Call idle CPU PM enter notifier chain to restore
	 * VFP context.
	 */
	if (pwrdm_read_prev_pwrst(mpu_pd) == PWRDM_POWER_OFF)
		cpu_pm_exit();

	/* Re-allow idle for C1 */
	if (index == 0) {
		pwrdm_for_each_clkdm(mpu_pd, _cpuidle_allow_idle);
		pwrdm_for_each_clkdm(core_pd, _cpuidle_allow_idle);
	}

return_sleep_time:

	local_fiq_enable();

	return index;
}

/**
 * omap3_enter_idle - Programs OMAP3 to enter the specified state
 * @dev: cpuidle device
 * @drv: cpuidle driver
 * @index: the index of state to be entered
 *
 * Called from the CPUidle framework to program the device to the
 * specified target state selected by the governor.
 */
static inline int omap3_enter_idle(struct cpuidle_device *dev,
				struct cpuidle_driver *drv,
				int index)
{
	return cpuidle_wrap_enter(dev, drv, index, __omap3_enter_idle);
}

/**
 * next_valid_state - Find next valid C-state
 * @dev: cpuidle device
 * @drv: cpuidle driver
 * @index: Index of currently selected c-state
 *
 * If the state corresponding to index is valid, index is returned back
 * to the caller. Else, this function searches for a lower c-state which is
 * still valid (as defined in omap3_power_states[]) and returns its index.
 *
 * A state is valid if the 'valid' field is enabled and
 * if it satisfies the enable_off_mode condition.
 */
static int next_valid_state(struct cpuidle_device *dev,
			struct cpuidle_driver *drv,
				int index)
{
	struct cpuidle_state_usage *curr_usage = &dev->states_usage[index];
	struct cpuidle_state *curr = &drv->states[index];
	struct omap3_idle_statedata *cx = cpuidle_get_statedata(curr_usage);
	u32 mpu_deepest_state = PWRDM_POWER_RET;
	u32 core_deepest_state = PWRDM_POWER_RET;
	int next_index = -1;

	if (enable_off_mode) {
		mpu_deepest_state = PWRDM_POWER_OFF;
		/*
		 * Erratum i583: valable for ES rev < Es1.2 on 3630.
		 * CORE OFF mode is not supported in a stable form, restrict
		 * instead the CORE state to RET.
		 */
		if (!IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583))
			core_deepest_state = PWRDM_POWER_OFF;
	}

	/* Check if current state is valid */
	if ((cx->valid) &&
	    (cx->mpu_state >= mpu_deepest_state) &&
	    (cx->core_state >= core_deepest_state)) {
		return index;
	} else {
		int idx = OMAP3_NUM_STATES - 1;

		/* Reach the current state starting at highest C-state */
		for (; idx >= 0; idx--) {
			if (&drv->states[idx] == curr) {
				next_index = idx;
				break;
			}
		}

		/* Should never hit this condition */
		WARN_ON(next_index == -1);

		/*
		 * Drop to next valid state.
		 * Start search from the next (lower) state.
		 */
		idx--;
		for (; idx >= 0; idx--) {
			cx = cpuidle_get_statedata(&dev->states_usage[idx]);
			if ((cx->valid) &&
			    (cx->mpu_state >= mpu_deepest_state) &&
			    (cx->core_state >= core_deepest_state)) {
				next_index = idx;
				break;
			}
		}
		/*
		 * C1 is always valid.
		 * So, no need to check for 'next_index == -1' outside
		 * this loop.
		 */
	}

	return next_index;
}

/**
 * omap3_enter_idle_bm - Checks for any bus activity
 * @dev: cpuidle device
 * @drv: cpuidle driver
 * @index: array index of target state to be programmed
 *
 * This function checks for any pending activity and then programs
 * the device to the specified or a safer state.
 */
static int omap3_enter_idle_bm(struct cpuidle_device *dev,
				struct cpuidle_driver *drv,
			       int index)
{
	int new_state_idx;
	u32 core_next_state, per_next_state = 0, per_saved_state = 0, cam_state;
	struct omap3_idle_statedata *cx;
	int ret;

	/*
	 * Prevent idle completely if CAM is active.
	 * CAM does not have wakeup capability in OMAP3.
	 */
	cam_state = pwrdm_read_pwrst(cam_pd);
	if (cam_state == PWRDM_POWER_ON) {
		new_state_idx = drv->safe_state_index;
		goto select_state;
	}

	/*
	 * FIXME: we currently manage device-specific idle states
	 *        for PER and CORE in combination with CPU-specific
	 *        idle states.  This is wrong, and device-specific
	 *        idle management needs to be separated out into
	 *        its own code.
	 */

	/*
	 * Prevent PER off if CORE is not in retention or off as this
	 * would disable PER wakeups completely.
	 */
	cx = cpuidle_get_statedata(&dev->states_usage[index]);
	core_next_state = cx->core_state;
	per_next_state = per_saved_state = pwrdm_read_next_pwrst(per_pd);
	if ((per_next_state == PWRDM_POWER_OFF) &&
	    (core_next_state > PWRDM_POWER_RET))
		per_next_state = PWRDM_POWER_RET;

	/* Are we changing PER target state? */
	if (per_next_state != per_saved_state)
		pwrdm_set_next_pwrst(per_pd, per_next_state);

	new_state_idx = next_valid_state(dev, drv, index);

select_state:
	ret = omap3_enter_idle(dev, drv, new_state_idx);

	/* Restore original PER state if it was modified */
	if (per_next_state != per_saved_state)
		pwrdm_set_next_pwrst(per_pd, per_saved_state);

	return ret;
}

DEFINE_PER_CPU(struct cpuidle_device, omap3_idle_dev);

struct cpuidle_driver omap3_idle_driver = {
	.name = 	"omap3_idle",
	.owner = 	THIS_MODULE,
	.states = {
		{
			.enter		  = omap3_enter_idle,
			.exit_latency	  = 2 + 2,
			.target_residency = 5,
			.flags		  = CPUIDLE_FLAG_TIME_VALID,
			.name		  = "C1",
			.desc		  = "MPU ON + CORE ON",
		},
		{
			.enter		  = omap3_enter_idle_bm,
			.exit_latency	  = 10 + 10,
			.target_residency = 30,
			.flags		  = CPUIDLE_FLAG_TIME_VALID,
			.name		  = "C2",
			.desc		  = "MPU ON + CORE ON",
		},
		{
			.enter		  = omap3_enter_idle_bm,
			.exit_latency	  = 50 + 50,
			.target_residency = 300,
			.flags		  = CPUIDLE_FLAG_TIME_VALID,
			.name		  = "C3",
			.desc		  = "MPU RET + CORE ON",
		},
		{
			.enter		  = omap3_enter_idle_bm,
			.exit_latency	  = 1500 + 1800,
			.target_residency = 4000,
			.flags		  = CPUIDLE_FLAG_TIME_VALID,
			.name		  = "C4",
			.desc		  = "MPU OFF + CORE ON",
		},
		{
			.enter		  = omap3_enter_idle_bm,
			.exit_latency	  = 2500 + 7500,
			.target_residency = 12000,
			.flags		  = CPUIDLE_FLAG_TIME_VALID,
			.name		  = "C5",
			.desc		  = "MPU RET + CORE RET",
		},
		{
			.enter		  = omap3_enter_idle_bm,
			.exit_latency	  = 3000 + 8500,
			.target_residency = 15000,
			.flags		  = CPUIDLE_FLAG_TIME_VALID,
			.name		  = "C6",
			.desc		  = "MPU OFF + CORE RET",
		},
		{
			.enter		  = omap3_enter_idle_bm,
			.exit_latency	  = 10000 + 30000,
			.target_residency = 30000,
			.flags		  = CPUIDLE_FLAG_TIME_VALID,
			.name		  = "C7",
			.desc		  = "MPU OFF + CORE OFF",
		},
	},
	.state_count = OMAP3_NUM_STATES,
	.safe_state_index = 0,
};

/* Helper to register the driver_data */
static inline struct omap3_idle_statedata *_fill_cstate_usage(
					struct cpuidle_device *dev,
					int idx)
{
	struct omap3_idle_statedata *cx = &omap3_idle_data[idx];
	struct cpuidle_state_usage *state_usage = &dev->states_usage[idx];

	cx->valid		= cpuidle_params_table[idx].valid;
	cpuidle_set_statedata(state_usage, cx);

	return cx;
}

/**
 * omap3_idle_init - Init routine for OMAP3 idle
 *
 * Registers the OMAP3 specific cpuidle driver to the cpuidle
 * framework with the valid set of states.
 */
int __init omap3_idle_init(void)
{
	struct cpuidle_device *dev;
	struct cpuidle_driver *drv = &omap3_idle_driver;
	struct omap3_idle_statedata *cx;

	mpu_pd = pwrdm_lookup("mpu_pwrdm");
	core_pd = pwrdm_lookup("core_pwrdm");
	per_pd = pwrdm_lookup("per_pwrdm");
	cam_pd = pwrdm_lookup("cam_pwrdm");


	dev = &per_cpu(omap3_idle_dev, smp_processor_id());

	/* C1 . MPU WFI + Core active */
	cx = _fill_cstate_usage(dev, 0);
	cx->valid = 1;	/* C1 is always valid */
	cx->mpu_state = PWRDM_POWER_ON;
	cx->core_state = PWRDM_POWER_ON;

	/* C2 . MPU WFI + Core inactive */
	cx = _fill_cstate_usage(dev, 1);
	cx->mpu_state = PWRDM_POWER_ON;
	cx->core_state = PWRDM_POWER_ON;

	/* C3 . MPU CSWR + Core inactive */
	cx = _fill_cstate_usage(dev, 2);
	cx->mpu_state = PWRDM_POWER_RET;
	cx->core_state = PWRDM_POWER_ON;

	/* C4 . MPU OFF + Core inactive */
	cx = _fill_cstate_usage(dev, 3);
	cx->mpu_state = PWRDM_POWER_OFF;
	cx->core_state = PWRDM_POWER_ON;

	/* C5 . MPU RET + Core RET */
	cx = _fill_cstate_usage(dev, 4);
	cx->mpu_state = PWRDM_POWER_RET;
	cx->core_state = PWRDM_POWER_RET;

	/* C6 . MPU OFF + Core RET */
	cx = _fill_cstate_usage(dev, 5);
	cx->mpu_state = PWRDM_POWER_OFF;
	cx->core_state = PWRDM_POWER_RET;

	/* C7 . MPU OFF + Core OFF */
	cx = _fill_cstate_usage(dev, 6);
	cx->mpu_state = PWRDM_POWER_OFF;
	cx->core_state = PWRDM_POWER_OFF;

	drv->state_count = OMAP3_NUM_STATES;
	cpuidle_register_driver(&omap3_idle_driver);

	if (cpuidle_register_device(dev)) {
		printk(KERN_ERR "%s: CPUidle register device failed\n",
		       __func__);
		return -EIO;
	}

	return 0;
}
#else
int __init omap3_idle_init(void)
{
	return 0;
}
#endif /* CONFIG_CPU_IDLE */
Commit	Line	Data
99e6a4d2 RN	1	/*
	2	* linux/arch/arm/mach-omap2/cpuidle34xx.c
	3	*
	4	* OMAP3 CPU IDLE Routines
	5	*
	6	* Copyright (C) 2008 Texas Instruments, Inc.
	7	* Rajendra Nayak <rnayak@ti.com>
	8	*
	9	* Copyright (C) 2007 Texas Instruments, Inc.
	10	* Karthik Dasu <karthik-dp@ti.com>
	11	*
	12	* Copyright (C) 2006 Nokia Corporation
	13	* Tony Lindgren <tony@atomide.com>
	14	*
	15	* Copyright (C) 2005 Texas Instruments, Inc.
	16	* Richard Woodruff <r-woodruff2@ti.com>
	17	*
	18	* Based on pm.c for omap2
	19	*
	20	* This program is free software; you can redistribute it and/or modify
	21	* it under the terms of the GNU General Public License version 2 as
	22	* published by the Free Software Foundation.
	23	*/
	24
cf22854c	25	#include <linux/sched.h>
99e6a4d2	26	#include <linux/cpuidle.h>
5698eb4e	27	#include <linux/export.h>
ff819da4	28	#include <linux/cpu_pm.h>
99e6a4d2 RN	29
99e6a4d2 RN	30	#include <plat/prcm.h>
20b01669	31	#include <plat/irqs.h>
72e06d08	32	#include "powerdomain.h"
1540f214	33	#include "clockdomain.h"
99e6a4d2	34
c98e2230	35	#include "pm.h"
4814ced5	36	#include "control.h"
ba8bb18a	37	#include "common.h"
c98e2230	38
99e6a4d2 RN	39	#ifdef CONFIG_CPU_IDLE
99e6a4d2 RN	40
bb4de3df KH	41	/*
	42	* The latencies/thresholds for various C states have
	43	* to be configured from the respective board files.
	44	* These are some default values (which might not provide
	45	* the best power savings) used on boards which do not
	46	* pass these details from the board file.
	47	*/
	48	static struct cpuidle_params cpuidle_params_table[] = {
	49	/* C1 */
866ba0ef	50	{2 + 2, 5, 1},
bb4de3df	51	/* C2 */
866ba0ef	52	{10 + 10, 30, 1},
bb4de3df	53	/* C3 */
866ba0ef	54	{50 + 50, 300, 1},
bb4de3df	55	/* C4 */
866ba0ef	56	{1500 + 1800, 4000, 1},
bb4de3df	57	/* C5 */
866ba0ef	58	{2500 + 7500, 12000, 1},
bb4de3df	59	/* C6 */
866ba0ef	60	{3000 + 8500, 15000, 1},
bb4de3df	61	/* C7 */
866ba0ef	62	{10000 + 30000, 300000, 1},
bb4de3df	63	};
badc303a JP	64	#define OMAP3_NUM_STATES ARRAY_SIZE(cpuidle_params_table)
	65
	66	/* Mach specific information to be recorded in the C-state driver_data */
	67	struct omap3_idle_statedata {
	68	u32 mpu_state;
	69	u32 core_state;
	70	u8 valid;
	71	};
	72	struct omap3_idle_statedata omap3_idle_data[OMAP3_NUM_STATES];
	73
	74	struct powerdomain mpu_pd, core_pd, per_pd, cam_pd;
bb4de3df	75
06d8f065 PDS	76	static int _cpuidle_allow_idle(struct powerdomain *pwrdm,
	77	struct clockdomain *clkdm)
	78	{
5cd1937b	79	clkdm_allow_idle(clkdm);
06d8f065 PDS	80	return 0;
	81	}
	82
	83	static int _cpuidle_deny_idle(struct powerdomain *pwrdm,
	84	struct clockdomain *clkdm)
	85	{
5cd1937b	86	clkdm_deny_idle(clkdm);
06d8f065 PDS	87	return 0;
	88	}
	89
6da45dce	90	static int __omap3_enter_idle(struct cpuidle_device *dev,
46bcfad7	91	struct cpuidle_driver *drv,
e978aa7d	92	int index)
99e6a4d2	93	{
e978aa7d	94	struct omap3_idle_statedata *cx =
4202735e	95	cpuidle_get_statedata(&dev->states_usage[index]);
c98e2230	96	u32 mpu_state = cx->mpu_state, core_state = cx->core_state;
99e6a4d2	97
99e6a4d2 RN	98	local_fiq_disable();
99e6a4d2 RN	99
7139178e JH	100	pwrdm_set_next_pwrst(mpu_pd, mpu_state);
7139178e JH	101	pwrdm_set_next_pwrst(core_pd, core_state);
20b01669	102
cf22854c	103	if (omap_irq_pending() \|\| need_resched())
20b01669	104	goto return_sleep_time;
99e6a4d2	105
badc303a	106	/* Deny idle for C1 */
e978aa7d	107	if (index == 0) {
06d8f065 PDS	108	pwrdm_for_each_clkdm(mpu_pd, _cpuidle_deny_idle);
	109	pwrdm_for_each_clkdm(core_pd, _cpuidle_deny_idle);
	110	}
	111
ff819da4 SS	112	/*
	113	* Call idle CPU PM enter notifier chain so that
	114	* VFP context is saved.
	115	*/
	116	if (mpu_state == PWRDM_POWER_OFF)
	117	cpu_pm_enter();
	118
99e6a4d2 RN	119	/* Execute ARM wfi */
	120	omap_sram_idle();
	121
ff819da4 SS	122	/*
	123	* Call idle CPU PM enter notifier chain to restore
	124	* VFP context.
	125	*/
	126	if (pwrdm_read_prev_pwrst(mpu_pd) == PWRDM_POWER_OFF)
	127	cpu_pm_exit();
	128
badc303a	129	/* Re-allow idle for C1 */
e978aa7d	130	if (index == 0) {
06d8f065 PDS	131	pwrdm_for_each_clkdm(mpu_pd, _cpuidle_allow_idle);
	132	pwrdm_for_each_clkdm(core_pd, _cpuidle_allow_idle);
	133	}
	134
20b01669	135	return_sleep_time:
99e6a4d2	136
99e6a4d2 RN	137	local_fiq_enable();
99e6a4d2 RN	138
e978aa7d	139	return index;
99e6a4d2 RN	140	}
99e6a4d2 RN	141
6da45dce RL	142	/**
	143	* omap3_enter_idle - Programs OMAP3 to enter the specified state
	144	* @dev: cpuidle device
	145	* @drv: cpuidle driver
	146	* @index: the index of state to be entered
	147	*
	148	* Called from the CPUidle framework to program the device to the
	149	* specified target state selected by the governor.
	150	*/
	151	static inline int omap3_enter_idle(struct cpuidle_device *dev,
	152	struct cpuidle_driver *drv,
	153	int index)
	154	{
	155	return cpuidle_wrap_enter(dev, drv, index, __omap3_enter_idle);
	156	}
	157
6af83b38	158	/**
04908918	159	* next_valid_state - Find next valid C-state
6af83b38	160	* @dev: cpuidle device
46bcfad7	161	* @drv: cpuidle driver
e978aa7d	162	* @index: Index of currently selected c-state
6af83b38	163	*
e978aa7d DD	164	* If the state corresponding to index is valid, index is returned back
	165	* to the caller. Else, this function searches for a lower c-state which is
	166	* still valid (as defined in omap3_power_states[]) and returns its index.
04908918 JP	167	*
	168	* A state is valid if the 'valid' field is enabled and
	169	* if it satisfies the enable_off_mode condition.
6af83b38	170	*/
e978aa7d	171	static int next_valid_state(struct cpuidle_device *dev,
46bcfad7	172	struct cpuidle_driver *drv,
e978aa7d	173	int index)
6af83b38	174	{
4202735e	175	struct cpuidle_state_usage *curr_usage = &dev->states_usage[index];
46bcfad7	176	struct cpuidle_state *curr = &drv->states[index];
4202735e	177	struct omap3_idle_statedata *cx = cpuidle_get_statedata(curr_usage);
04908918 JP	178	u32 mpu_deepest_state = PWRDM_POWER_RET;
04908918 JP	179	u32 core_deepest_state = PWRDM_POWER_RET;
e978aa7d	180	int next_index = -1;
04908918 JP	181
	182	if (enable_off_mode) {
	183	mpu_deepest_state = PWRDM_POWER_OFF;
	184	/*
	185	* Erratum i583: valable for ES rev < Es1.2 on 3630.
	186	* CORE OFF mode is not supported in a stable form, restrict
	187	* instead the CORE state to RET.
	188	*/
	189	if (!IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583))
	190	core_deepest_state = PWRDM_POWER_OFF;
	191	}
6af83b38 SP	192
6af83b38 SP	193	/* Check if current state is valid */
04908918 JP	194	if ((cx->valid) &&
	195	(cx->mpu_state >= mpu_deepest_state) &&
	196	(cx->core_state >= core_deepest_state)) {
e978aa7d	197	return index;
6af83b38	198	} else {
badc303a	199	int idx = OMAP3_NUM_STATES - 1;
6af83b38	200
c6cd91de	201	/* Reach the current state starting at highest C-state */
badc303a	202	for (; idx >= 0; idx--) {
46bcfad7	203	if (&drv->states[idx] == curr) {
e978aa7d	204	next_index = idx;
6af83b38 SP	205	break;
	206	}
	207	}
	208
c6cd91de	209	/* Should never hit this condition */
e978aa7d	210	WARN_ON(next_index == -1);
6af83b38 SP	211
	212	/*
	213	* Drop to next valid state.
	214	* Start search from the next (lower) state.
	215	*/
	216	idx--;
badc303a	217	for (; idx >= 0; idx--) {
4202735e	218	cx = cpuidle_get_statedata(&dev->states_usage[idx]);
04908918 JP	219	if ((cx->valid) &&
	220	(cx->mpu_state >= mpu_deepest_state) &&
	221	(cx->core_state >= core_deepest_state)) {
e978aa7d	222	next_index = idx;
6af83b38 SP	223	break;
	224	}
	225	}
	226	/*
badc303a	227	* C1 is always valid.
e978aa7d DD	228	* So, no need to check for 'next_index == -1' outside
e978aa7d DD	229	* this loop.
6af83b38 SP	230	*/
	231	}
	232
e978aa7d	233	return next_index;
6af83b38 SP	234	}
6af83b38 SP	235
99e6a4d2 RN	236	/**
	237	* omap3_enter_idle_bm - Checks for any bus activity
	238	* @dev: cpuidle device
46bcfad7	239	* @drv: cpuidle driver
e978aa7d	240	* @index: array index of target state to be programmed
99e6a4d2	241	*
badc303a JP	242	* This function checks for any pending activity and then programs
badc303a JP	243	* the device to the specified or a safer state.
99e6a4d2 RN	244	*/
99e6a4d2 RN	245	static int omap3_enter_idle_bm(struct cpuidle_device *dev,
46bcfad7	246	struct cpuidle_driver *drv,
e978aa7d	247	int index)
99e6a4d2	248	{
e978aa7d	249	int new_state_idx;
c6cd91de	250	u32 core_next_state, per_next_state = 0, per_saved_state = 0, cam_state;
badc303a	251	struct omap3_idle_statedata *cx;
e7410cf7	252	int ret;
0f724ed9	253
e7410cf7 KH	254	/*
	255	* Prevent idle completely if CAM is active.
	256	* CAM does not have wakeup capability in OMAP3.
	257	*/
	258	cam_state = pwrdm_read_pwrst(cam_pd);
	259	if (cam_state == PWRDM_POWER_ON) {
46bcfad7	260	new_state_idx = drv->safe_state_index;
e7410cf7 KH	261	goto select_state;
	262	}
	263
c6cd91de JP	264	/*
	265	* FIXME: we currently manage device-specific idle states
	266	* for PER and CORE in combination with CPU-specific
	267	* idle states. This is wrong, and device-specific
	268	* idle management needs to be separated out into
	269	* its own code.
	270	*/
	271
e7410cf7 KH	272	/*
	273	* Prevent PER off if CORE is not in retention or off as this
	274	* would disable PER wakeups completely.
	275	*/
4202735e	276	cx = cpuidle_get_statedata(&dev->states_usage[index]);
c6cd91de	277	core_next_state = cx->core_state;
e7410cf7 KH	278	per_next_state = per_saved_state = pwrdm_read_next_pwrst(per_pd);
e7410cf7 KH	279	if ((per_next_state == PWRDM_POWER_OFF) &&
65707fb3	280	(core_next_state > PWRDM_POWER_RET))
e7410cf7	281	per_next_state = PWRDM_POWER_RET;
0f724ed9	282
e7410cf7 KH	283	/* Are we changing PER target state? */
	284	if (per_next_state != per_saved_state)
	285	pwrdm_set_next_pwrst(per_pd, per_next_state);
	286
46bcfad7	287	new_state_idx = next_valid_state(dev, drv, index);
c6cd91de	288
e7410cf7	289	select_state:
46bcfad7	290	ret = omap3_enter_idle(dev, drv, new_state_idx);
e7410cf7 KH	291
	292	/* Restore original PER state if it was modified */
	293	if (per_next_state != per_saved_state)
	294	pwrdm_set_next_pwrst(per_pd, per_saved_state);
	295
	296	return ret;
99e6a4d2 RN	297	}
	298
	299	DEFINE_PER_CPU(struct cpuidle_device, omap3_idle_dev);
	300
99e6a4d2 RN	301	struct cpuidle_driver omap3_idle_driver = {
	302	.name = "omap3_idle",
	303	.owner = THIS_MODULE,
200dd520 DL	304	.states = {
	305	{
	306	.enter = omap3_enter_idle,
	307	.exit_latency = 2 + 2,
	308	.target_residency = 5,
	309	.flags = CPUIDLE_FLAG_TIME_VALID,
	310	.name = "C1",
	311	.desc = "MPU ON + CORE ON",
	312	},
	313	{
	314	.enter = omap3_enter_idle_bm,
	315	.exit_latency = 10 + 10,
	316	.target_residency = 30,
	317	.flags = CPUIDLE_FLAG_TIME_VALID,
	318	.name = "C2",
	319	.desc = "MPU ON + CORE ON",
	320	},
	321	{
	322	.enter = omap3_enter_idle_bm,
	323	.exit_latency = 50 + 50,
	324	.target_residency = 300,
	325	.flags = CPUIDLE_FLAG_TIME_VALID,
	326	.name = "C3",
	327	.desc = "MPU RET + CORE ON",
	328	},
	329	{
	330	.enter = omap3_enter_idle_bm,
	331	.exit_latency = 1500 + 1800,
	332	.target_residency = 4000,
	333	.flags = CPUIDLE_FLAG_TIME_VALID,
	334	.name = "C4",
	335	.desc = "MPU OFF + CORE ON",
	336	},
	337	{
	338	.enter = omap3_enter_idle_bm,
	339	.exit_latency = 2500 + 7500,
	340	.target_residency = 12000,
	341	.flags = CPUIDLE_FLAG_TIME_VALID,
	342	.name = "C5",
	343	.desc = "MPU RET + CORE RET",
	344	},
	345	{
	346	.enter = omap3_enter_idle_bm,
	347	.exit_latency = 3000 + 8500,
	348	.target_residency = 15000,
	349	.flags = CPUIDLE_FLAG_TIME_VALID,
	350	.name = "C6",
	351	.desc = "MPU OFF + CORE RET",
	352	},
	353	{
	354	.enter = omap3_enter_idle_bm,
	355	.exit_latency = 10000 + 30000,
	356	.target_residency = 30000,
	357	.flags = CPUIDLE_FLAG_TIME_VALID,
	358	.name = "C7",
	359	.desc = "MPU OFF + CORE OFF",
	360	},
	361	},
	362	.state_count = OMAP3_NUM_STATES,
	363	.safe_state_index = 0,
99e6a4d2 RN	364	};
99e6a4d2 RN	365
46bcfad7 DD	366	/* Helper to register the driver_data */
	367	static inline struct omap3_idle_statedata *_fill_cstate_usage(
	368	struct cpuidle_device *dev,
	369	int idx)
	370	{
	371	struct omap3_idle_statedata *cx = &omap3_idle_data[idx];
	372	struct cpuidle_state_usage *state_usage = &dev->states_usage[idx];
	373
	374	cx->valid = cpuidle_params_table[idx].valid;
4202735e	375	cpuidle_set_statedata(state_usage, cx);
badc303a JP	376
	377	return cx;
	378	}
	379
99e6a4d2 RN	380	/**
	381	* omap3_idle_init - Init routine for OMAP3 idle
	382	*
badc303a	383	* Registers the OMAP3 specific cpuidle driver to the cpuidle
99e6a4d2 RN	384	* framework with the valid set of states.
99e6a4d2 RN	385	*/
0343371e	386	int __init omap3_idle_init(void)
99e6a4d2	387	{
99e6a4d2	388	struct cpuidle_device *dev;
46bcfad7	389	struct cpuidle_driver *drv = &omap3_idle_driver;
badc303a	390	struct omap3_idle_statedata *cx;
99e6a4d2 RN	391
99e6a4d2 RN	392	mpu_pd = pwrdm_lookup("mpu_pwrdm");
20b01669	393	core_pd = pwrdm_lookup("core_pwrdm");
e7410cf7 KH	394	per_pd = pwrdm_lookup("per_pwrdm");
e7410cf7 KH	395	cam_pd = pwrdm_lookup("cam_pwrdm");
99e6a4d2	396
46bcfad7	397
99e6a4d2 RN	398	dev = &per_cpu(omap3_idle_dev, smp_processor_id());
99e6a4d2 RN	399
badc303a	400	/* C1 . MPU WFI + Core active */
46bcfad7	401	cx = _fill_cstate_usage(dev, 0);
badc303a JP	402	cx->valid = 1; /* C1 is always valid */
	403	cx->mpu_state = PWRDM_POWER_ON;
	404	cx->core_state = PWRDM_POWER_ON;
	405
	406	/* C2 . MPU WFI + Core inactive */
46bcfad7	407	cx = _fill_cstate_usage(dev, 1);
badc303a JP	408	cx->mpu_state = PWRDM_POWER_ON;
	409	cx->core_state = PWRDM_POWER_ON;
	410
	411	/* C3 . MPU CSWR + Core inactive */
46bcfad7	412	cx = _fill_cstate_usage(dev, 2);
badc303a JP	413	cx->mpu_state = PWRDM_POWER_RET;
	414	cx->core_state = PWRDM_POWER_ON;
	415
	416	/* C4 . MPU OFF + Core inactive */
46bcfad7	417	cx = _fill_cstate_usage(dev, 3);
badc303a JP	418	cx->mpu_state = PWRDM_POWER_OFF;
	419	cx->core_state = PWRDM_POWER_ON;
	420
	421	/* C5 . MPU RET + Core RET */
46bcfad7	422	cx = _fill_cstate_usage(dev, 4);
badc303a JP	423	cx->mpu_state = PWRDM_POWER_RET;
badc303a JP	424	cx->core_state = PWRDM_POWER_RET;
99e6a4d2	425
badc303a	426	/* C6 . MPU OFF + Core RET */
46bcfad7	427	cx = _fill_cstate_usage(dev, 5);
badc303a JP	428	cx->mpu_state = PWRDM_POWER_OFF;
	429	cx->core_state = PWRDM_POWER_RET;
	430
	431	/* C7 . MPU OFF + Core OFF */
46bcfad7	432	cx = _fill_cstate_usage(dev, 6);
badc303a JP	433	cx->mpu_state = PWRDM_POWER_OFF;
badc303a JP	434	cx->core_state = PWRDM_POWER_OFF;
99e6a4d2	435
46bcfad7 DD	436	drv->state_count = OMAP3_NUM_STATES;
	437	cpuidle_register_driver(&omap3_idle_driver);
	438
99e6a4d2 RN	439	if (cpuidle_register_device(dev)) {
	440	printk(KERN_ERR "%s: CPUidle register device failed\n",
	441	__func__);
	442	return -EIO;
	443	}
	444
	445	return 0;
	446	}
0343371e KJ	447	#else
	448	int __init omap3_idle_init(void)
	449	{
	450	return 0;
	451	}
99e6a4d2	452	#endif /* CONFIG_CPU_IDLE */