Commit | Line | Data |
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99e6a4d2 RN |
1 | /* |
2 | * linux/arch/arm/mach-omap2/cpuidle34xx.c | |
3 | * | |
4 | * OMAP3 CPU IDLE Routines | |
5 | * | |
6 | * Copyright (C) 2008 Texas Instruments, Inc. | |
7 | * Rajendra Nayak <rnayak@ti.com> | |
8 | * | |
9 | * Copyright (C) 2007 Texas Instruments, Inc. | |
10 | * Karthik Dasu <karthik-dp@ti.com> | |
11 | * | |
12 | * Copyright (C) 2006 Nokia Corporation | |
13 | * Tony Lindgren <tony@atomide.com> | |
14 | * | |
15 | * Copyright (C) 2005 Texas Instruments, Inc. | |
16 | * Richard Woodruff <r-woodruff2@ti.com> | |
17 | * | |
18 | * Based on pm.c for omap2 | |
19 | * | |
20 | * This program is free software; you can redistribute it and/or modify | |
21 | * it under the terms of the GNU General Public License version 2 as | |
22 | * published by the Free Software Foundation. | |
23 | */ | |
24 | ||
cf22854c | 25 | #include <linux/sched.h> |
99e6a4d2 | 26 | #include <linux/cpuidle.h> |
5698eb4e | 27 | #include <linux/export.h> |
99e6a4d2 RN |
28 | |
29 | #include <plat/prcm.h> | |
20b01669 | 30 | #include <plat/irqs.h> |
72e06d08 | 31 | #include "powerdomain.h" |
1540f214 | 32 | #include "clockdomain.h" |
0f724ed9 | 33 | #include <plat/serial.h> |
99e6a4d2 | 34 | |
c98e2230 | 35 | #include "pm.h" |
4814ced5 | 36 | #include "control.h" |
ba8bb18a | 37 | #include "common.h" |
c98e2230 | 38 | |
99e6a4d2 RN |
39 | #ifdef CONFIG_CPU_IDLE |
40 | ||
bb4de3df KH |
41 | /* |
42 | * The latencies/thresholds for various C states have | |
43 | * to be configured from the respective board files. | |
44 | * These are some default values (which might not provide | |
45 | * the best power savings) used on boards which do not | |
46 | * pass these details from the board file. | |
47 | */ | |
48 | static struct cpuidle_params cpuidle_params_table[] = { | |
49 | /* C1 */ | |
866ba0ef | 50 | {2 + 2, 5, 1}, |
bb4de3df | 51 | /* C2 */ |
866ba0ef | 52 | {10 + 10, 30, 1}, |
bb4de3df | 53 | /* C3 */ |
866ba0ef | 54 | {50 + 50, 300, 1}, |
bb4de3df | 55 | /* C4 */ |
866ba0ef | 56 | {1500 + 1800, 4000, 1}, |
bb4de3df | 57 | /* C5 */ |
866ba0ef | 58 | {2500 + 7500, 12000, 1}, |
bb4de3df | 59 | /* C6 */ |
866ba0ef | 60 | {3000 + 8500, 15000, 1}, |
bb4de3df | 61 | /* C7 */ |
866ba0ef | 62 | {10000 + 30000, 300000, 1}, |
bb4de3df | 63 | }; |
badc303a JP |
64 | #define OMAP3_NUM_STATES ARRAY_SIZE(cpuidle_params_table) |
65 | ||
66 | /* Mach specific information to be recorded in the C-state driver_data */ | |
67 | struct omap3_idle_statedata { | |
68 | u32 mpu_state; | |
69 | u32 core_state; | |
70 | u8 valid; | |
71 | }; | |
72 | struct omap3_idle_statedata omap3_idle_data[OMAP3_NUM_STATES]; | |
73 | ||
74 | struct powerdomain *mpu_pd, *core_pd, *per_pd, *cam_pd; | |
bb4de3df | 75 | |
06d8f065 PDS |
76 | static int _cpuidle_allow_idle(struct powerdomain *pwrdm, |
77 | struct clockdomain *clkdm) | |
78 | { | |
5cd1937b | 79 | clkdm_allow_idle(clkdm); |
06d8f065 PDS |
80 | return 0; |
81 | } | |
82 | ||
83 | static int _cpuidle_deny_idle(struct powerdomain *pwrdm, | |
84 | struct clockdomain *clkdm) | |
85 | { | |
5cd1937b | 86 | clkdm_deny_idle(clkdm); |
06d8f065 PDS |
87 | return 0; |
88 | } | |
89 | ||
99e6a4d2 RN |
90 | /** |
91 | * omap3_enter_idle - Programs OMAP3 to enter the specified state | |
92 | * @dev: cpuidle device | |
46bcfad7 | 93 | * @drv: cpuidle driver |
e978aa7d | 94 | * @index: the index of state to be entered |
99e6a4d2 RN |
95 | * |
96 | * Called from the CPUidle framework to program the device to the | |
97 | * specified target state selected by the governor. | |
98 | */ | |
99 | static int omap3_enter_idle(struct cpuidle_device *dev, | |
46bcfad7 | 100 | struct cpuidle_driver *drv, |
e978aa7d | 101 | int index) |
99e6a4d2 | 102 | { |
e978aa7d | 103 | struct omap3_idle_statedata *cx = |
4202735e | 104 | cpuidle_get_statedata(&dev->states_usage[index]); |
99e6a4d2 | 105 | struct timespec ts_preidle, ts_postidle, ts_idle; |
c98e2230 | 106 | u32 mpu_state = cx->mpu_state, core_state = cx->core_state; |
e978aa7d | 107 | int idle_time; |
99e6a4d2 | 108 | |
99e6a4d2 RN |
109 | /* Used to keep track of the total time in idle */ |
110 | getnstimeofday(&ts_preidle); | |
111 | ||
112 | local_irq_disable(); | |
113 | local_fiq_disable(); | |
114 | ||
7139178e JH |
115 | pwrdm_set_next_pwrst(mpu_pd, mpu_state); |
116 | pwrdm_set_next_pwrst(core_pd, core_state); | |
20b01669 | 117 | |
cf22854c | 118 | if (omap_irq_pending() || need_resched()) |
20b01669 | 119 | goto return_sleep_time; |
99e6a4d2 | 120 | |
badc303a | 121 | /* Deny idle for C1 */ |
e978aa7d | 122 | if (index == 0) { |
06d8f065 PDS |
123 | pwrdm_for_each_clkdm(mpu_pd, _cpuidle_deny_idle); |
124 | pwrdm_for_each_clkdm(core_pd, _cpuidle_deny_idle); | |
125 | } | |
126 | ||
99e6a4d2 RN |
127 | /* Execute ARM wfi */ |
128 | omap_sram_idle(); | |
129 | ||
badc303a | 130 | /* Re-allow idle for C1 */ |
e978aa7d | 131 | if (index == 0) { |
06d8f065 PDS |
132 | pwrdm_for_each_clkdm(mpu_pd, _cpuidle_allow_idle); |
133 | pwrdm_for_each_clkdm(core_pd, _cpuidle_allow_idle); | |
134 | } | |
135 | ||
20b01669 | 136 | return_sleep_time: |
99e6a4d2 RN |
137 | getnstimeofday(&ts_postidle); |
138 | ts_idle = timespec_sub(ts_postidle, ts_preidle); | |
139 | ||
140 | local_irq_enable(); | |
141 | local_fiq_enable(); | |
142 | ||
e978aa7d DD |
143 | idle_time = ts_idle.tv_nsec / NSEC_PER_USEC + ts_idle.tv_sec * \ |
144 | USEC_PER_SEC; | |
145 | ||
146 | /* Update cpuidle counters */ | |
147 | dev->last_residency = idle_time; | |
148 | ||
149 | return index; | |
99e6a4d2 RN |
150 | } |
151 | ||
6af83b38 | 152 | /** |
04908918 | 153 | * next_valid_state - Find next valid C-state |
6af83b38 | 154 | * @dev: cpuidle device |
46bcfad7 | 155 | * @drv: cpuidle driver |
e978aa7d | 156 | * @index: Index of currently selected c-state |
6af83b38 | 157 | * |
e978aa7d DD |
158 | * If the state corresponding to index is valid, index is returned back |
159 | * to the caller. Else, this function searches for a lower c-state which is | |
160 | * still valid (as defined in omap3_power_states[]) and returns its index. | |
04908918 JP |
161 | * |
162 | * A state is valid if the 'valid' field is enabled and | |
163 | * if it satisfies the enable_off_mode condition. | |
6af83b38 | 164 | */ |
e978aa7d | 165 | static int next_valid_state(struct cpuidle_device *dev, |
46bcfad7 | 166 | struct cpuidle_driver *drv, |
e978aa7d | 167 | int index) |
6af83b38 | 168 | { |
4202735e | 169 | struct cpuidle_state_usage *curr_usage = &dev->states_usage[index]; |
46bcfad7 | 170 | struct cpuidle_state *curr = &drv->states[index]; |
4202735e | 171 | struct omap3_idle_statedata *cx = cpuidle_get_statedata(curr_usage); |
04908918 JP |
172 | u32 mpu_deepest_state = PWRDM_POWER_RET; |
173 | u32 core_deepest_state = PWRDM_POWER_RET; | |
e978aa7d | 174 | int next_index = -1; |
04908918 JP |
175 | |
176 | if (enable_off_mode) { | |
177 | mpu_deepest_state = PWRDM_POWER_OFF; | |
178 | /* | |
179 | * Erratum i583: valable for ES rev < Es1.2 on 3630. | |
180 | * CORE OFF mode is not supported in a stable form, restrict | |
181 | * instead the CORE state to RET. | |
182 | */ | |
183 | if (!IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583)) | |
184 | core_deepest_state = PWRDM_POWER_OFF; | |
185 | } | |
6af83b38 SP |
186 | |
187 | /* Check if current state is valid */ | |
04908918 JP |
188 | if ((cx->valid) && |
189 | (cx->mpu_state >= mpu_deepest_state) && | |
190 | (cx->core_state >= core_deepest_state)) { | |
e978aa7d | 191 | return index; |
6af83b38 | 192 | } else { |
badc303a | 193 | int idx = OMAP3_NUM_STATES - 1; |
6af83b38 | 194 | |
c6cd91de | 195 | /* Reach the current state starting at highest C-state */ |
badc303a | 196 | for (; idx >= 0; idx--) { |
46bcfad7 | 197 | if (&drv->states[idx] == curr) { |
e978aa7d | 198 | next_index = idx; |
6af83b38 SP |
199 | break; |
200 | } | |
201 | } | |
202 | ||
c6cd91de | 203 | /* Should never hit this condition */ |
e978aa7d | 204 | WARN_ON(next_index == -1); |
6af83b38 SP |
205 | |
206 | /* | |
207 | * Drop to next valid state. | |
208 | * Start search from the next (lower) state. | |
209 | */ | |
210 | idx--; | |
badc303a | 211 | for (; idx >= 0; idx--) { |
4202735e | 212 | cx = cpuidle_get_statedata(&dev->states_usage[idx]); |
04908918 JP |
213 | if ((cx->valid) && |
214 | (cx->mpu_state >= mpu_deepest_state) && | |
215 | (cx->core_state >= core_deepest_state)) { | |
e978aa7d | 216 | next_index = idx; |
6af83b38 SP |
217 | break; |
218 | } | |
219 | } | |
220 | /* | |
badc303a | 221 | * C1 is always valid. |
e978aa7d DD |
222 | * So, no need to check for 'next_index == -1' outside |
223 | * this loop. | |
6af83b38 SP |
224 | */ |
225 | } | |
226 | ||
e978aa7d | 227 | return next_index; |
6af83b38 SP |
228 | } |
229 | ||
99e6a4d2 RN |
230 | /** |
231 | * omap3_enter_idle_bm - Checks for any bus activity | |
232 | * @dev: cpuidle device | |
46bcfad7 | 233 | * @drv: cpuidle driver |
e978aa7d | 234 | * @index: array index of target state to be programmed |
99e6a4d2 | 235 | * |
badc303a JP |
236 | * This function checks for any pending activity and then programs |
237 | * the device to the specified or a safer state. | |
99e6a4d2 RN |
238 | */ |
239 | static int omap3_enter_idle_bm(struct cpuidle_device *dev, | |
46bcfad7 | 240 | struct cpuidle_driver *drv, |
e978aa7d | 241 | int index) |
99e6a4d2 | 242 | { |
e978aa7d | 243 | int new_state_idx; |
c6cd91de | 244 | u32 core_next_state, per_next_state = 0, per_saved_state = 0, cam_state; |
badc303a | 245 | struct omap3_idle_statedata *cx; |
e7410cf7 | 246 | int ret; |
0f724ed9 | 247 | |
c6cd91de | 248 | if (!omap3_can_sleep()) { |
46bcfad7 | 249 | new_state_idx = drv->safe_state_index; |
e7410cf7 KH |
250 | goto select_state; |
251 | } | |
252 | ||
e7410cf7 KH |
253 | /* |
254 | * Prevent idle completely if CAM is active. | |
255 | * CAM does not have wakeup capability in OMAP3. | |
256 | */ | |
257 | cam_state = pwrdm_read_pwrst(cam_pd); | |
258 | if (cam_state == PWRDM_POWER_ON) { | |
46bcfad7 | 259 | new_state_idx = drv->safe_state_index; |
e7410cf7 KH |
260 | goto select_state; |
261 | } | |
262 | ||
c6cd91de JP |
263 | /* |
264 | * FIXME: we currently manage device-specific idle states | |
265 | * for PER and CORE in combination with CPU-specific | |
266 | * idle states. This is wrong, and device-specific | |
267 | * idle management needs to be separated out into | |
268 | * its own code. | |
269 | */ | |
270 | ||
e7410cf7 KH |
271 | /* |
272 | * Prevent PER off if CORE is not in retention or off as this | |
273 | * would disable PER wakeups completely. | |
274 | */ | |
4202735e | 275 | cx = cpuidle_get_statedata(&dev->states_usage[index]); |
c6cd91de | 276 | core_next_state = cx->core_state; |
e7410cf7 KH |
277 | per_next_state = per_saved_state = pwrdm_read_next_pwrst(per_pd); |
278 | if ((per_next_state == PWRDM_POWER_OFF) && | |
65707fb3 | 279 | (core_next_state > PWRDM_POWER_RET)) |
e7410cf7 | 280 | per_next_state = PWRDM_POWER_RET; |
0f724ed9 | 281 | |
e7410cf7 KH |
282 | /* Are we changing PER target state? */ |
283 | if (per_next_state != per_saved_state) | |
284 | pwrdm_set_next_pwrst(per_pd, per_next_state); | |
285 | ||
46bcfad7 | 286 | new_state_idx = next_valid_state(dev, drv, index); |
c6cd91de | 287 | |
e7410cf7 | 288 | select_state: |
46bcfad7 | 289 | ret = omap3_enter_idle(dev, drv, new_state_idx); |
e7410cf7 KH |
290 | |
291 | /* Restore original PER state if it was modified */ | |
292 | if (per_next_state != per_saved_state) | |
293 | pwrdm_set_next_pwrst(per_pd, per_saved_state); | |
294 | ||
295 | return ret; | |
99e6a4d2 RN |
296 | } |
297 | ||
298 | DEFINE_PER_CPU(struct cpuidle_device, omap3_idle_dev); | |
299 | ||
bb4de3df KH |
300 | void omap3_pm_init_cpuidle(struct cpuidle_params *cpuidle_board_params) |
301 | { | |
302 | int i; | |
303 | ||
304 | if (!cpuidle_board_params) | |
305 | return; | |
306 | ||
badc303a JP |
307 | for (i = 0; i < OMAP3_NUM_STATES; i++) { |
308 | cpuidle_params_table[i].valid = cpuidle_board_params[i].valid; | |
866ba0ef JP |
309 | cpuidle_params_table[i].exit_latency = |
310 | cpuidle_board_params[i].exit_latency; | |
311 | cpuidle_params_table[i].target_residency = | |
312 | cpuidle_board_params[i].target_residency; | |
bb4de3df KH |
313 | } |
314 | return; | |
315 | } | |
316 | ||
99e6a4d2 RN |
317 | struct cpuidle_driver omap3_idle_driver = { |
318 | .name = "omap3_idle", | |
319 | .owner = THIS_MODULE, | |
320 | }; | |
321 | ||
46bcfad7 DD |
322 | /* Helper to fill the C-state common data*/ |
323 | static inline void _fill_cstate(struct cpuidle_driver *drv, | |
badc303a JP |
324 | int idx, const char *descr) |
325 | { | |
46bcfad7 | 326 | struct cpuidle_state *state = &drv->states[idx]; |
badc303a JP |
327 | |
328 | state->exit_latency = cpuidle_params_table[idx].exit_latency; | |
329 | state->target_residency = cpuidle_params_table[idx].target_residency; | |
330 | state->flags = CPUIDLE_FLAG_TIME_VALID; | |
331 | state->enter = omap3_enter_idle_bm; | |
badc303a JP |
332 | sprintf(state->name, "C%d", idx + 1); |
333 | strncpy(state->desc, descr, CPUIDLE_DESC_LEN); | |
46bcfad7 DD |
334 | |
335 | } | |
336 | ||
337 | /* Helper to register the driver_data */ | |
338 | static inline struct omap3_idle_statedata *_fill_cstate_usage( | |
339 | struct cpuidle_device *dev, | |
340 | int idx) | |
341 | { | |
342 | struct omap3_idle_statedata *cx = &omap3_idle_data[idx]; | |
343 | struct cpuidle_state_usage *state_usage = &dev->states_usage[idx]; | |
344 | ||
345 | cx->valid = cpuidle_params_table[idx].valid; | |
4202735e | 346 | cpuidle_set_statedata(state_usage, cx); |
badc303a JP |
347 | |
348 | return cx; | |
349 | } | |
350 | ||
99e6a4d2 RN |
351 | /** |
352 | * omap3_idle_init - Init routine for OMAP3 idle | |
353 | * | |
badc303a | 354 | * Registers the OMAP3 specific cpuidle driver to the cpuidle |
99e6a4d2 RN |
355 | * framework with the valid set of states. |
356 | */ | |
0343371e | 357 | int __init omap3_idle_init(void) |
99e6a4d2 | 358 | { |
99e6a4d2 | 359 | struct cpuidle_device *dev; |
46bcfad7 | 360 | struct cpuidle_driver *drv = &omap3_idle_driver; |
badc303a | 361 | struct omap3_idle_statedata *cx; |
99e6a4d2 RN |
362 | |
363 | mpu_pd = pwrdm_lookup("mpu_pwrdm"); | |
20b01669 | 364 | core_pd = pwrdm_lookup("core_pwrdm"); |
e7410cf7 KH |
365 | per_pd = pwrdm_lookup("per_pwrdm"); |
366 | cam_pd = pwrdm_lookup("cam_pwrdm"); | |
99e6a4d2 | 367 | |
46bcfad7 DD |
368 | |
369 | drv->safe_state_index = -1; | |
99e6a4d2 RN |
370 | dev = &per_cpu(omap3_idle_dev, smp_processor_id()); |
371 | ||
badc303a | 372 | /* C1 . MPU WFI + Core active */ |
46bcfad7 DD |
373 | _fill_cstate(drv, 0, "MPU ON + CORE ON"); |
374 | (&drv->states[0])->enter = omap3_enter_idle; | |
375 | drv->safe_state_index = 0; | |
376 | cx = _fill_cstate_usage(dev, 0); | |
badc303a JP |
377 | cx->valid = 1; /* C1 is always valid */ |
378 | cx->mpu_state = PWRDM_POWER_ON; | |
379 | cx->core_state = PWRDM_POWER_ON; | |
380 | ||
381 | /* C2 . MPU WFI + Core inactive */ | |
46bcfad7 DD |
382 | _fill_cstate(drv, 1, "MPU ON + CORE ON"); |
383 | cx = _fill_cstate_usage(dev, 1); | |
badc303a JP |
384 | cx->mpu_state = PWRDM_POWER_ON; |
385 | cx->core_state = PWRDM_POWER_ON; | |
386 | ||
387 | /* C3 . MPU CSWR + Core inactive */ | |
46bcfad7 DD |
388 | _fill_cstate(drv, 2, "MPU RET + CORE ON"); |
389 | cx = _fill_cstate_usage(dev, 2); | |
badc303a JP |
390 | cx->mpu_state = PWRDM_POWER_RET; |
391 | cx->core_state = PWRDM_POWER_ON; | |
392 | ||
393 | /* C4 . MPU OFF + Core inactive */ | |
46bcfad7 DD |
394 | _fill_cstate(drv, 3, "MPU OFF + CORE ON"); |
395 | cx = _fill_cstate_usage(dev, 3); | |
badc303a JP |
396 | cx->mpu_state = PWRDM_POWER_OFF; |
397 | cx->core_state = PWRDM_POWER_ON; | |
398 | ||
399 | /* C5 . MPU RET + Core RET */ | |
46bcfad7 DD |
400 | _fill_cstate(drv, 4, "MPU RET + CORE RET"); |
401 | cx = _fill_cstate_usage(dev, 4); | |
badc303a JP |
402 | cx->mpu_state = PWRDM_POWER_RET; |
403 | cx->core_state = PWRDM_POWER_RET; | |
99e6a4d2 | 404 | |
badc303a | 405 | /* C6 . MPU OFF + Core RET */ |
46bcfad7 DD |
406 | _fill_cstate(drv, 5, "MPU OFF + CORE RET"); |
407 | cx = _fill_cstate_usage(dev, 5); | |
badc303a JP |
408 | cx->mpu_state = PWRDM_POWER_OFF; |
409 | cx->core_state = PWRDM_POWER_RET; | |
410 | ||
411 | /* C7 . MPU OFF + Core OFF */ | |
46bcfad7 DD |
412 | _fill_cstate(drv, 6, "MPU OFF + CORE OFF"); |
413 | cx = _fill_cstate_usage(dev, 6); | |
badc303a JP |
414 | /* |
415 | * Erratum i583: implementation for ES rev < Es1.2 on 3630. We cannot | |
416 | * enable OFF mode in a stable form for previous revisions. | |
417 | * We disable C7 state as a result. | |
418 | */ | |
419 | if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583)) { | |
420 | cx->valid = 0; | |
421 | pr_warn("%s: core off state C7 disabled due to i583\n", | |
422 | __func__); | |
423 | } | |
424 | cx->mpu_state = PWRDM_POWER_OFF; | |
425 | cx->core_state = PWRDM_POWER_OFF; | |
99e6a4d2 | 426 | |
46bcfad7 DD |
427 | drv->state_count = OMAP3_NUM_STATES; |
428 | cpuidle_register_driver(&omap3_idle_driver); | |
429 | ||
badc303a | 430 | dev->state_count = OMAP3_NUM_STATES; |
99e6a4d2 RN |
431 | if (cpuidle_register_device(dev)) { |
432 | printk(KERN_ERR "%s: CPUidle register device failed\n", | |
433 | __func__); | |
434 | return -EIO; | |
435 | } | |
436 | ||
437 | return 0; | |
438 | } | |
0343371e KJ |
439 | #else |
440 | int __init omap3_idle_init(void) | |
441 | { | |
442 | return 0; | |
443 | } | |
99e6a4d2 | 444 | #endif /* CONFIG_CPU_IDLE */ |