[deliverable/linux.git] / arch / arm / mach-omap2 / cpuidle34xx.c

/*
 * linux/arch/arm/mach-omap2/cpuidle34xx.c
 *
 * OMAP3 CPU IDLE Routines
 *
 * Copyright (C) 2008 Texas Instruments, Inc.
 * Rajendra Nayak <rnayak@ti.com>
 *
 * Copyright (C) 2007 Texas Instruments, Inc.
 * Karthik Dasu <karthik-dp@ti.com>
 *
 * Copyright (C) 2006 Nokia Corporation
 * Tony Lindgren <tony@atomide.com>
 *
 * Copyright (C) 2005 Texas Instruments, Inc.
 * Richard Woodruff <r-woodruff2@ti.com>
 *
 * Based on pm.c for omap2
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/sched.h>
#include <linux/cpuidle.h>
#include <linux/export.h>
#include <linux/cpu_pm.h>

#include <plat/prcm.h>
#include <plat/irqs.h>
#include "powerdomain.h"
#include "clockdomain.h"

#include "pm.h"
#include "control.h"
#include "common.h"

#ifdef CONFIG_CPU_IDLE

/* Mach specific information to be recorded in the C-state driver_data */
struct omap3_idle_statedata {
	u32 mpu_state;
	u32 core_state;
};

struct omap3_idle_statedata omap3_idle_data[] = {
	{
		.mpu_state = PWRDM_POWER_ON,
		.core_state = PWRDM_POWER_ON,
	},
	{
		.mpu_state = PWRDM_POWER_ON,
		.core_state = PWRDM_POWER_ON,
	},
	{
		.mpu_state = PWRDM_POWER_RET,
		.core_state = PWRDM_POWER_ON,
	},
	{
		.mpu_state = PWRDM_POWER_OFF,
		.core_state = PWRDM_POWER_ON,
	},
	{
		.mpu_state = PWRDM_POWER_RET,
		.core_state = PWRDM_POWER_RET,
	},
	{
		.mpu_state = PWRDM_POWER_OFF,
		.core_state = PWRDM_POWER_RET,
	},
	{
		.mpu_state = PWRDM_POWER_OFF,
		.core_state = PWRDM_POWER_OFF,
	},
};

struct powerdomain *mpu_pd, *core_pd, *per_pd, *cam_pd;

static int _cpuidle_allow_idle(struct powerdomain *pwrdm,
				struct clockdomain *clkdm)
{
	clkdm_allow_idle(clkdm);
	return 0;
}

static int _cpuidle_deny_idle(struct powerdomain *pwrdm,
				struct clockdomain *clkdm)
{
	clkdm_deny_idle(clkdm);
	return 0;
}

static int __omap3_enter_idle(struct cpuidle_device *dev,
				struct cpuidle_driver *drv,
				int index)
{
	struct omap3_idle_statedata *cx = &omap3_idle_data[index];
	u32 mpu_state = cx->mpu_state, core_state = cx->core_state;

	local_fiq_disable();

	pwrdm_set_next_pwrst(mpu_pd, mpu_state);
	pwrdm_set_next_pwrst(core_pd, core_state);

	if (omap_irq_pending() || need_resched())
		goto return_sleep_time;

	/* Deny idle for C1 */
	if (index == 0) {
		pwrdm_for_each_clkdm(mpu_pd, _cpuidle_deny_idle);
		pwrdm_for_each_clkdm(core_pd, _cpuidle_deny_idle);
	}

	/*
	 * Call idle CPU PM enter notifier chain so that
	 * VFP context is saved.
	 */
	if (mpu_state == PWRDM_POWER_OFF)
		cpu_pm_enter();

	/* Execute ARM wfi */
	omap_sram_idle();

	/*
	 * Call idle CPU PM enter notifier chain to restore
	 * VFP context.
	 */
	if (pwrdm_read_prev_pwrst(mpu_pd) == PWRDM_POWER_OFF)
		cpu_pm_exit();

	/* Re-allow idle for C1 */
	if (index == 0) {
		pwrdm_for_each_clkdm(mpu_pd, _cpuidle_allow_idle);
		pwrdm_for_each_clkdm(core_pd, _cpuidle_allow_idle);
	}

return_sleep_time:

	local_fiq_enable();

	return index;
}

/**
 * omap3_enter_idle - Programs OMAP3 to enter the specified state
 * @dev: cpuidle device
 * @drv: cpuidle driver
 * @index: the index of state to be entered
 *
 * Called from the CPUidle framework to program the device to the
 * specified target state selected by the governor.
 */
static inline int omap3_enter_idle(struct cpuidle_device *dev,
				struct cpuidle_driver *drv,
				int index)
{
	return cpuidle_wrap_enter(dev, drv, index, __omap3_enter_idle);
}

/**
 * next_valid_state - Find next valid C-state
 * @dev: cpuidle device
 * @drv: cpuidle driver
 * @index: Index of currently selected c-state
 *
 * If the state corresponding to index is valid, index is returned back
 * to the caller. Else, this function searches for a lower c-state which is
 * still valid (as defined in omap3_power_states[]) and returns its index.
 *
 * A state is valid if the 'valid' field is enabled and
 * if it satisfies the enable_off_mode condition.
 */
static int next_valid_state(struct cpuidle_device *dev,
			    struct cpuidle_driver *drv, int index)
{
	struct omap3_idle_statedata *cx = &omap3_idle_data[index];
	u32 mpu_deepest_state = PWRDM_POWER_RET;
	u32 core_deepest_state = PWRDM_POWER_RET;
	int idx;
	int next_index = -1;

	if (enable_off_mode) {
		mpu_deepest_state = PWRDM_POWER_OFF;
		/*
		 * Erratum i583: valable for ES rev < Es1.2 on 3630.
		 * CORE OFF mode is not supported in a stable form, restrict
		 * instead the CORE state to RET.
		 */
		if (!IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583))
			core_deepest_state = PWRDM_POWER_OFF;
	}

	/* Check if current state is valid */
	if ((cx->mpu_state >= mpu_deepest_state) &&
	    (cx->core_state >= core_deepest_state))
		return index;

	/*
	 * Drop to next valid state.
	 * Start search from the next (lower) state.
	 */
	for (idx = index - 1; idx >= 0; idx--) {
		cx =  &omap3_idle_data[idx];
		if ((cx->mpu_state >= mpu_deepest_state) &&
		    (cx->core_state >= core_deepest_state)) {
			next_index = idx;
			break;
		}
	}

	/*
	 * C1 is always valid.
	 * So, no need to check for 'next_index == -1' outside
	 * this loop.
	 */

	return next_index;
}

/**
 * omap3_enter_idle_bm - Checks for any bus activity
 * @dev: cpuidle device
 * @drv: cpuidle driver
 * @index: array index of target state to be programmed
 *
 * This function checks for any pending activity and then programs
 * the device to the specified or a safer state.
 */
static int omap3_enter_idle_bm(struct cpuidle_device *dev,
				struct cpuidle_driver *drv,
			       int index)
{
	int new_state_idx;
	u32 core_next_state, per_next_state = 0, per_saved_state = 0, cam_state;
	struct omap3_idle_statedata *cx;
	int ret;

	/*
	 * Prevent idle completely if CAM is active.
	 * CAM does not have wakeup capability in OMAP3.
	 */
	cam_state = pwrdm_read_pwrst(cam_pd);
	if (cam_state == PWRDM_POWER_ON) {
		new_state_idx = drv->safe_state_index;
		goto select_state;
	}

	/*
	 * FIXME: we currently manage device-specific idle states
	 *        for PER and CORE in combination with CPU-specific
	 *        idle states.  This is wrong, and device-specific
	 *        idle management needs to be separated out into
	 *        its own code.
	 */

	/*
	 * Prevent PER off if CORE is not in retention or off as this
	 * would disable PER wakeups completely.
	 */
	cx = &omap3_idle_data[index];
	core_next_state = cx->core_state;
	per_next_state = per_saved_state = pwrdm_read_next_pwrst(per_pd);
	if ((per_next_state == PWRDM_POWER_OFF) &&
	    (core_next_state > PWRDM_POWER_RET))
		per_next_state = PWRDM_POWER_RET;

	/* Are we changing PER target state? */
	if (per_next_state != per_saved_state)
		pwrdm_set_next_pwrst(per_pd, per_next_state);

	new_state_idx = next_valid_state(dev, drv, index);

select_state:
	ret = omap3_enter_idle(dev, drv, new_state_idx);

	/* Restore original PER state if it was modified */
	if (per_next_state != per_saved_state)
		pwrdm_set_next_pwrst(per_pd, per_saved_state);

	return ret;
}

DEFINE_PER_CPU(struct cpuidle_device, omap3_idle_dev);

struct cpuidle_driver omap3_idle_driver = {
	.name = 	"omap3_idle",
	.owner = 	THIS_MODULE,
	.states = {
		{
			.enter		  = omap3_enter_idle,
			.exit_latency	  = 2 + 2,
			.target_residency = 5,
			.flags		  = CPUIDLE_FLAG_TIME_VALID,
			.name		  = "C1",
			.desc		  = "MPU ON + CORE ON",
		},
		{
			.enter		  = omap3_enter_idle_bm,
			.exit_latency	  = 10 + 10,
			.target_residency = 30,
			.flags		  = CPUIDLE_FLAG_TIME_VALID,
			.name		  = "C2",
			.desc		  = "MPU ON + CORE ON",
		},
		{
			.enter		  = omap3_enter_idle_bm,
			.exit_latency	  = 50 + 50,
			.target_residency = 300,
			.flags		  = CPUIDLE_FLAG_TIME_VALID,
			.name		  = "C3",
			.desc		  = "MPU RET + CORE ON",
		},
		{
			.enter		  = omap3_enter_idle_bm,
			.exit_latency	  = 1500 + 1800,
			.target_residency = 4000,
			.flags		  = CPUIDLE_FLAG_TIME_VALID,
			.name		  = "C4",
			.desc		  = "MPU OFF + CORE ON",
		},
		{
			.enter		  = omap3_enter_idle_bm,
			.exit_latency	  = 2500 + 7500,
			.target_residency = 12000,
			.flags		  = CPUIDLE_FLAG_TIME_VALID,
			.name		  = "C5",
			.desc		  = "MPU RET + CORE RET",
		},
		{
			.enter		  = omap3_enter_idle_bm,
			.exit_latency	  = 3000 + 8500,
			.target_residency = 15000,
			.flags		  = CPUIDLE_FLAG_TIME_VALID,
			.name		  = "C6",
			.desc		  = "MPU OFF + CORE RET",
		},
		{
			.enter		  = omap3_enter_idle_bm,
			.exit_latency	  = 10000 + 30000,
			.target_residency = 30000,
			.flags		  = CPUIDLE_FLAG_TIME_VALID,
			.name		  = "C7",
			.desc		  = "MPU OFF + CORE OFF",
		},
	},
	.state_count = ARRAY_SIZE(omap3_idle_data),
	.safe_state_index = 0,
};

/**
 * omap3_idle_init - Init routine for OMAP3 idle
 *
 * Registers the OMAP3 specific cpuidle driver to the cpuidle
 * framework with the valid set of states.
 */
int __init omap3_idle_init(void)
{
	struct cpuidle_device *dev;

	mpu_pd = pwrdm_lookup("mpu_pwrdm");
	core_pd = pwrdm_lookup("core_pwrdm");
	per_pd = pwrdm_lookup("per_pwrdm");
	cam_pd = pwrdm_lookup("cam_pwrdm");

	cpuidle_register_driver(&omap3_idle_driver);

	dev = &per_cpu(omap3_idle_dev, smp_processor_id());
	dev->cpu = 0;

	if (cpuidle_register_device(dev)) {
		printk(KERN_ERR "%s: CPUidle register device failed\n",
		       __func__);
		return -EIO;
	}

	return 0;
}
#else
int __init omap3_idle_init(void)
{
	return 0;
}
#endif /* CONFIG_CPU_IDLE */
Commit	Line	Data
99e6a4d2 RN	1	/*
	2	* linux/arch/arm/mach-omap2/cpuidle34xx.c
	3	*
	4	* OMAP3 CPU IDLE Routines
	5	*
	6	* Copyright (C) 2008 Texas Instruments, Inc.
	7	* Rajendra Nayak <rnayak@ti.com>
	8	*
	9	* Copyright (C) 2007 Texas Instruments, Inc.
	10	* Karthik Dasu <karthik-dp@ti.com>
	11	*
	12	* Copyright (C) 2006 Nokia Corporation
	13	* Tony Lindgren <tony@atomide.com>
	14	*
	15	* Copyright (C) 2005 Texas Instruments, Inc.
	16	* Richard Woodruff <r-woodruff2@ti.com>
	17	*
	18	* Based on pm.c for omap2
	19	*
	20	* This program is free software; you can redistribute it and/or modify
	21	* it under the terms of the GNU General Public License version 2 as
	22	* published by the Free Software Foundation.
	23	*/
	24
cf22854c	25	#include <linux/sched.h>
99e6a4d2	26	#include <linux/cpuidle.h>
5698eb4e	27	#include <linux/export.h>
ff819da4	28	#include <linux/cpu_pm.h>
99e6a4d2 RN	29
99e6a4d2 RN	30	#include <plat/prcm.h>
20b01669	31	#include <plat/irqs.h>
72e06d08	32	#include "powerdomain.h"
1540f214	33	#include "clockdomain.h"
99e6a4d2	34
c98e2230	35	#include "pm.h"
4814ced5	36	#include "control.h"
ba8bb18a	37	#include "common.h"
c98e2230	38
99e6a4d2 RN	39	#ifdef CONFIG_CPU_IDLE
99e6a4d2 RN	40
badc303a JP	41	/* Mach specific information to be recorded in the C-state driver_data */
	42	struct omap3_idle_statedata {
	43	u32 mpu_state;
	44	u32 core_state;
badc303a	45	};
0c2487f6	46
88c377dd DL	47	struct omap3_idle_statedata omap3_idle_data[] = {
	48	{
	49	.mpu_state = PWRDM_POWER_ON,
	50	.core_state = PWRDM_POWER_ON,
	51	},
	52	{
	53	.mpu_state = PWRDM_POWER_ON,
	54	.core_state = PWRDM_POWER_ON,
	55	},
	56	{
	57	.mpu_state = PWRDM_POWER_RET,
	58	.core_state = PWRDM_POWER_ON,
	59	},
	60	{
	61	.mpu_state = PWRDM_POWER_OFF,
	62	.core_state = PWRDM_POWER_ON,
	63	},
	64	{
	65	.mpu_state = PWRDM_POWER_RET,
	66	.core_state = PWRDM_POWER_RET,
	67	},
	68	{
	69	.mpu_state = PWRDM_POWER_OFF,
	70	.core_state = PWRDM_POWER_RET,
	71	},
	72	{
	73	.mpu_state = PWRDM_POWER_OFF,
	74	.core_state = PWRDM_POWER_OFF,
	75	},
	76	};
badc303a JP	77
badc303a JP	78	struct powerdomain mpu_pd, core_pd, per_pd, cam_pd;
bb4de3df	79
06d8f065 PDS	80	static int _cpuidle_allow_idle(struct powerdomain *pwrdm,
	81	struct clockdomain *clkdm)
	82	{
5cd1937b	83	clkdm_allow_idle(clkdm);
06d8f065 PDS	84	return 0;
	85	}
	86
	87	static int _cpuidle_deny_idle(struct powerdomain *pwrdm,
	88	struct clockdomain *clkdm)
	89	{
5cd1937b	90	clkdm_deny_idle(clkdm);
06d8f065 PDS	91	return 0;
	92	}
	93
6da45dce	94	static int __omap3_enter_idle(struct cpuidle_device *dev,
46bcfad7	95	struct cpuidle_driver *drv,
e978aa7d	96	int index)
99e6a4d2	97	{
6622ac55	98	struct omap3_idle_statedata *cx = &omap3_idle_data[index];
c98e2230	99	u32 mpu_state = cx->mpu_state, core_state = cx->core_state;
99e6a4d2	100
99e6a4d2 RN	101	local_fiq_disable();
99e6a4d2 RN	102
7139178e JH	103	pwrdm_set_next_pwrst(mpu_pd, mpu_state);
7139178e JH	104	pwrdm_set_next_pwrst(core_pd, core_state);
20b01669	105
cf22854c	106	if (omap_irq_pending() \|\| need_resched())
20b01669	107	goto return_sleep_time;
99e6a4d2	108
badc303a	109	/* Deny idle for C1 */
e978aa7d	110	if (index == 0) {
06d8f065 PDS	111	pwrdm_for_each_clkdm(mpu_pd, _cpuidle_deny_idle);
	112	pwrdm_for_each_clkdm(core_pd, _cpuidle_deny_idle);
	113	}
	114
ff819da4 SS	115	/*
	116	* Call idle CPU PM enter notifier chain so that
	117	* VFP context is saved.
	118	*/
	119	if (mpu_state == PWRDM_POWER_OFF)
	120	cpu_pm_enter();
	121
99e6a4d2 RN	122	/* Execute ARM wfi */
	123	omap_sram_idle();
	124
ff819da4 SS	125	/*
	126	* Call idle CPU PM enter notifier chain to restore
	127	* VFP context.
	128	*/
	129	if (pwrdm_read_prev_pwrst(mpu_pd) == PWRDM_POWER_OFF)
	130	cpu_pm_exit();
	131
badc303a	132	/* Re-allow idle for C1 */
e978aa7d	133	if (index == 0) {
06d8f065 PDS	134	pwrdm_for_each_clkdm(mpu_pd, _cpuidle_allow_idle);
	135	pwrdm_for_each_clkdm(core_pd, _cpuidle_allow_idle);
	136	}
	137
20b01669	138	return_sleep_time:
99e6a4d2	139
99e6a4d2 RN	140	local_fiq_enable();
99e6a4d2 RN	141
e978aa7d	142	return index;
99e6a4d2 RN	143	}
99e6a4d2 RN	144
6da45dce RL	145	/**
	146	* omap3_enter_idle - Programs OMAP3 to enter the specified state
	147	* @dev: cpuidle device
	148	* @drv: cpuidle driver
	149	* @index: the index of state to be entered
	150	*
	151	* Called from the CPUidle framework to program the device to the
	152	* specified target state selected by the governor.
	153	*/
	154	static inline int omap3_enter_idle(struct cpuidle_device *dev,
	155	struct cpuidle_driver *drv,
	156	int index)
	157	{
	158	return cpuidle_wrap_enter(dev, drv, index, __omap3_enter_idle);
	159	}
	160
6af83b38	161	/**
04908918	162	* next_valid_state - Find next valid C-state
6af83b38	163	* @dev: cpuidle device
46bcfad7	164	* @drv: cpuidle driver
e978aa7d	165	* @index: Index of currently selected c-state
6af83b38	166	*
e978aa7d DD	167	* If the state corresponding to index is valid, index is returned back
	168	* to the caller. Else, this function searches for a lower c-state which is
	169	* still valid (as defined in omap3_power_states[]) and returns its index.
04908918 JP	170	*
	171	* A state is valid if the 'valid' field is enabled and
	172	* if it satisfies the enable_off_mode condition.
6af83b38	173	*/
e978aa7d	174	static int next_valid_state(struct cpuidle_device *dev,
e92a4586	175	struct cpuidle_driver *drv, int index)
6af83b38	176	{
6622ac55	177	struct omap3_idle_statedata *cx = &omap3_idle_data[index];
04908918 JP	178	u32 mpu_deepest_state = PWRDM_POWER_RET;
04908918 JP	179	u32 core_deepest_state = PWRDM_POWER_RET;
e92a4586	180	int idx;
e978aa7d	181	int next_index = -1;
04908918 JP	182
	183	if (enable_off_mode) {
	184	mpu_deepest_state = PWRDM_POWER_OFF;
	185	/*
	186	* Erratum i583: valable for ES rev < Es1.2 on 3630.
	187	* CORE OFF mode is not supported in a stable form, restrict
	188	* instead the CORE state to RET.
	189	*/
	190	if (!IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583))
	191	core_deepest_state = PWRDM_POWER_OFF;
	192	}
6af83b38 SP	193
6af83b38 SP	194	/* Check if current state is valid */
f79b5d8a	195	if ((cx->mpu_state >= mpu_deepest_state) &&
e92a4586	196	(cx->core_state >= core_deepest_state))
e978aa7d	197	return index;
6af83b38	198
e92a4586 DL	199	/*
	200	* Drop to next valid state.
	201	* Start search from the next (lower) state.
	202	*/
	203	for (idx = index - 1; idx >= 0; idx--) {
	204	cx = &omap3_idle_data[idx];
	205	if ((cx->mpu_state >= mpu_deepest_state) &&
	206	(cx->core_state >= core_deepest_state)) {
	207	next_index = idx;
	208	break;
6af83b38	209	}
6af83b38 SP	210	}
6af83b38 SP	211
e92a4586 DL	212	/*
	213	* C1 is always valid.
	214	* So, no need to check for 'next_index == -1' outside
	215	* this loop.
	216	*/
	217
e978aa7d	218	return next_index;
6af83b38 SP	219	}
6af83b38 SP	220
99e6a4d2 RN	221	/**
	222	* omap3_enter_idle_bm - Checks for any bus activity
	223	* @dev: cpuidle device
46bcfad7	224	* @drv: cpuidle driver
e978aa7d	225	* @index: array index of target state to be programmed
99e6a4d2	226	*
badc303a JP	227	* This function checks for any pending activity and then programs
badc303a JP	228	* the device to the specified or a safer state.
99e6a4d2 RN	229	*/
99e6a4d2 RN	230	static int omap3_enter_idle_bm(struct cpuidle_device *dev,
46bcfad7	231	struct cpuidle_driver *drv,
e978aa7d	232	int index)
99e6a4d2	233	{
e978aa7d	234	int new_state_idx;
c6cd91de	235	u32 core_next_state, per_next_state = 0, per_saved_state = 0, cam_state;
badc303a	236	struct omap3_idle_statedata *cx;
e7410cf7	237	int ret;
0f724ed9	238
e7410cf7 KH	239	/*
	240	* Prevent idle completely if CAM is active.
	241	* CAM does not have wakeup capability in OMAP3.
	242	*/
	243	cam_state = pwrdm_read_pwrst(cam_pd);
	244	if (cam_state == PWRDM_POWER_ON) {
46bcfad7	245	new_state_idx = drv->safe_state_index;
e7410cf7 KH	246	goto select_state;
	247	}
	248
c6cd91de JP	249	/*
	250	* FIXME: we currently manage device-specific idle states
	251	* for PER and CORE in combination with CPU-specific
	252	* idle states. This is wrong, and device-specific
	253	* idle management needs to be separated out into
	254	* its own code.
	255	*/
	256
e7410cf7 KH	257	/*
	258	* Prevent PER off if CORE is not in retention or off as this
	259	* would disable PER wakeups completely.
	260	*/
6622ac55	261	cx = &omap3_idle_data[index];
c6cd91de	262	core_next_state = cx->core_state;
e7410cf7 KH	263	per_next_state = per_saved_state = pwrdm_read_next_pwrst(per_pd);
e7410cf7 KH	264	if ((per_next_state == PWRDM_POWER_OFF) &&
65707fb3	265	(core_next_state > PWRDM_POWER_RET))
e7410cf7	266	per_next_state = PWRDM_POWER_RET;
0f724ed9	267
e7410cf7 KH	268	/* Are we changing PER target state? */
	269	if (per_next_state != per_saved_state)
	270	pwrdm_set_next_pwrst(per_pd, per_next_state);
	271
46bcfad7	272	new_state_idx = next_valid_state(dev, drv, index);
c6cd91de	273
e7410cf7	274	select_state:
46bcfad7	275	ret = omap3_enter_idle(dev, drv, new_state_idx);
e7410cf7 KH	276
	277	/* Restore original PER state if it was modified */
	278	if (per_next_state != per_saved_state)
	279	pwrdm_set_next_pwrst(per_pd, per_saved_state);
	280
	281	return ret;
99e6a4d2 RN	282	}
	283
	284	DEFINE_PER_CPU(struct cpuidle_device, omap3_idle_dev);
	285
99e6a4d2 RN	286	struct cpuidle_driver omap3_idle_driver = {
	287	.name = "omap3_idle",
	288	.owner = THIS_MODULE,
200dd520 DL	289	.states = {
	290	{
	291	.enter = omap3_enter_idle,
	292	.exit_latency = 2 + 2,
	293	.target_residency = 5,
	294	.flags = CPUIDLE_FLAG_TIME_VALID,
	295	.name = "C1",
	296	.desc = "MPU ON + CORE ON",
	297	},
	298	{
	299	.enter = omap3_enter_idle_bm,
	300	.exit_latency = 10 + 10,
	301	.target_residency = 30,
	302	.flags = CPUIDLE_FLAG_TIME_VALID,
	303	.name = "C2",
	304	.desc = "MPU ON + CORE ON",
	305	},
	306	{
	307	.enter = omap3_enter_idle_bm,
	308	.exit_latency = 50 + 50,
	309	.target_residency = 300,
	310	.flags = CPUIDLE_FLAG_TIME_VALID,
	311	.name = "C3",
	312	.desc = "MPU RET + CORE ON",
	313	},
	314	{
	315	.enter = omap3_enter_idle_bm,
	316	.exit_latency = 1500 + 1800,
	317	.target_residency = 4000,
	318	.flags = CPUIDLE_FLAG_TIME_VALID,
	319	.name = "C4",
	320	.desc = "MPU OFF + CORE ON",
	321	},
	322	{
	323	.enter = omap3_enter_idle_bm,
	324	.exit_latency = 2500 + 7500,
	325	.target_residency = 12000,
	326	.flags = CPUIDLE_FLAG_TIME_VALID,
	327	.name = "C5",
	328	.desc = "MPU RET + CORE RET",
	329	},
	330	{
	331	.enter = omap3_enter_idle_bm,
	332	.exit_latency = 3000 + 8500,
	333	.target_residency = 15000,
	334	.flags = CPUIDLE_FLAG_TIME_VALID,
	335	.name = "C6",
	336	.desc = "MPU OFF + CORE RET",
	337	},
	338	{
	339	.enter = omap3_enter_idle_bm,
	340	.exit_latency = 10000 + 30000,
	341	.target_residency = 30000,
	342	.flags = CPUIDLE_FLAG_TIME_VALID,
	343	.name = "C7",
	344	.desc = "MPU OFF + CORE OFF",
	345	},
	346	},
88c377dd	347	.state_count = ARRAY_SIZE(omap3_idle_data),
200dd520	348	.safe_state_index = 0,
99e6a4d2 RN	349	};
	350
	351	/**
	352	* omap3_idle_init - Init routine for OMAP3 idle
	353	*
badc303a	354	* Registers the OMAP3 specific cpuidle driver to the cpuidle
99e6a4d2 RN	355	* framework with the valid set of states.
99e6a4d2 RN	356	*/
0343371e	357	int __init omap3_idle_init(void)
99e6a4d2	358	{
99e6a4d2 RN	359	struct cpuidle_device *dev;
	360
	361	mpu_pd = pwrdm_lookup("mpu_pwrdm");
20b01669	362	core_pd = pwrdm_lookup("core_pwrdm");
e7410cf7 KH	363	per_pd = pwrdm_lookup("per_pwrdm");
e7410cf7 KH	364	cam_pd = pwrdm_lookup("cam_pwrdm");
99e6a4d2	365
6622ac55	366	cpuidle_register_driver(&omap3_idle_driver);
46bcfad7	367
99e6a4d2	368	dev = &per_cpu(omap3_idle_dev, smp_processor_id());
6622ac55	369	dev->cpu = 0;
46bcfad7	370
99e6a4d2 RN	371	if (cpuidle_register_device(dev)) {
	372	printk(KERN_ERR "%s: CPUidle register device failed\n",
	373	__func__);
	374	return -EIO;
	375	}
	376
	377	return 0;
	378	}
0343371e KJ	379	#else
	380	int __init omap3_idle_init(void)
	381	{
	382	return 0;
	383	}
99e6a4d2	384	#endif /* CONFIG_CPU_IDLE */