[deliverable/linux.git] / arch / arm / mach-omap2 / cpuidle34xx.c

/*
 * linux/arch/arm/mach-omap2/cpuidle34xx.c
 *
 * OMAP3 CPU IDLE Routines
 *
 * Copyright (C) 2008 Texas Instruments, Inc.
 * Rajendra Nayak <rnayak@ti.com>
 *
 * Copyright (C) 2007 Texas Instruments, Inc.
 * Karthik Dasu <karthik-dp@ti.com>
 *
 * Copyright (C) 2006 Nokia Corporation
 * Tony Lindgren <tony@atomide.com>
 *
 * Copyright (C) 2005 Texas Instruments, Inc.
 * Richard Woodruff <r-woodruff2@ti.com>
 *
 * Based on pm.c for omap2
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/sched.h>
#include <linux/cpuidle.h>
#include <linux/export.h>
#include <linux/cpu_pm.h>

#include <plat/prcm.h>
#include <plat/irqs.h>
#include "powerdomain.h"
#include "clockdomain.h"

#include "pm.h"
#include "control.h"
#include "common.h"

#ifdef CONFIG_CPU_IDLE

/*
 * The latencies/thresholds for various C states have
 * to be configured from the respective board files.
 * These are some default values (which might not provide
 * the best power savings) used on boards which do not
 * pass these details from the board file.
 */
static struct cpuidle_params cpuidle_params_table[] = {
	/* C1 */
	{2 + 2, 5, 1},
	/* C2 */
	{10 + 10, 30, 1},
	/* C3 */
	{50 + 50, 300, 1},
	/* C4 */
	{1500 + 1800, 4000, 1},
	/* C5 */
	{2500 + 7500, 12000, 1},
	/* C6 */
	{3000 + 8500, 15000, 1},
	/* C7 */
	{10000 + 30000, 300000, 1},
};
#define OMAP3_NUM_STATES ARRAY_SIZE(cpuidle_params_table)

/* Mach specific information to be recorded in the C-state driver_data */
struct omap3_idle_statedata {
	u32 mpu_state;
	u32 core_state;
};
struct omap3_idle_statedata omap3_idle_data[OMAP3_NUM_STATES];

struct powerdomain *mpu_pd, *core_pd, *per_pd, *cam_pd;

static int _cpuidle_allow_idle(struct powerdomain *pwrdm,
				struct clockdomain *clkdm)
{
	clkdm_allow_idle(clkdm);
	return 0;
}

static int _cpuidle_deny_idle(struct powerdomain *pwrdm,
				struct clockdomain *clkdm)
{
	clkdm_deny_idle(clkdm);
	return 0;
}

static int __omap3_enter_idle(struct cpuidle_device *dev,
				struct cpuidle_driver *drv,
				int index)
{
	struct omap3_idle_statedata *cx =
			cpuidle_get_statedata(&dev->states_usage[index]);
	u32 mpu_state = cx->mpu_state, core_state = cx->core_state;

	local_fiq_disable();

	pwrdm_set_next_pwrst(mpu_pd, mpu_state);
	pwrdm_set_next_pwrst(core_pd, core_state);

	if (omap_irq_pending() || need_resched())
		goto return_sleep_time;

	/* Deny idle for C1 */
	if (index == 0) {
		pwrdm_for_each_clkdm(mpu_pd, _cpuidle_deny_idle);
		pwrdm_for_each_clkdm(core_pd, _cpuidle_deny_idle);
	}

	/*
	 * Call idle CPU PM enter notifier chain so that
	 * VFP context is saved.
	 */
	if (mpu_state == PWRDM_POWER_OFF)
		cpu_pm_enter();

	/* Execute ARM wfi */
	omap_sram_idle();

	/*
	 * Call idle CPU PM enter notifier chain to restore
	 * VFP context.
	 */
	if (pwrdm_read_prev_pwrst(mpu_pd) == PWRDM_POWER_OFF)
		cpu_pm_exit();

	/* Re-allow idle for C1 */
	if (index == 0) {
		pwrdm_for_each_clkdm(mpu_pd, _cpuidle_allow_idle);
		pwrdm_for_each_clkdm(core_pd, _cpuidle_allow_idle);
	}

return_sleep_time:

	local_fiq_enable();

	return index;
}

/**
 * omap3_enter_idle - Programs OMAP3 to enter the specified state
 * @dev: cpuidle device
 * @drv: cpuidle driver
 * @index: the index of state to be entered
 *
 * Called from the CPUidle framework to program the device to the
 * specified target state selected by the governor.
 */
static inline int omap3_enter_idle(struct cpuidle_device *dev,
				struct cpuidle_driver *drv,
				int index)
{
	return cpuidle_wrap_enter(dev, drv, index, __omap3_enter_idle);
}

/**
 * next_valid_state - Find next valid C-state
 * @dev: cpuidle device
 * @drv: cpuidle driver
 * @index: Index of currently selected c-state
 *
 * If the state corresponding to index is valid, index is returned back
 * to the caller. Else, this function searches for a lower c-state which is
 * still valid (as defined in omap3_power_states[]) and returns its index.
 *
 * A state is valid if the 'valid' field is enabled and
 * if it satisfies the enable_off_mode condition.
 */
static int next_valid_state(struct cpuidle_device *dev,
			struct cpuidle_driver *drv,
				int index)
{
	struct cpuidle_state_usage *curr_usage = &dev->states_usage[index];
	struct cpuidle_state *curr = &drv->states[index];
	struct omap3_idle_statedata *cx = cpuidle_get_statedata(curr_usage);
	u32 mpu_deepest_state = PWRDM_POWER_RET;
	u32 core_deepest_state = PWRDM_POWER_RET;
	int next_index = -1;

	if (enable_off_mode) {
		mpu_deepest_state = PWRDM_POWER_OFF;
		/*
		 * Erratum i583: valable for ES rev < Es1.2 on 3630.
		 * CORE OFF mode is not supported in a stable form, restrict
		 * instead the CORE state to RET.
		 */
		if (!IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583))
			core_deepest_state = PWRDM_POWER_OFF;
	}

	/* Check if current state is valid */
	if ((cx->mpu_state >= mpu_deepest_state) &&
	    (cx->core_state >= core_deepest_state)) {
		return index;
	} else {
		int idx = OMAP3_NUM_STATES - 1;

		/* Reach the current state starting at highest C-state */
		for (; idx >= 0; idx--) {
			if (&drv->states[idx] == curr) {
				next_index = idx;
				break;
			}
		}

		/* Should never hit this condition */
		WARN_ON(next_index == -1);

		/*
		 * Drop to next valid state.
		 * Start search from the next (lower) state.
		 */
		idx--;
		for (; idx >= 0; idx--) {
			cx = cpuidle_get_statedata(&dev->states_usage[idx]);
			if ((cx->mpu_state >= mpu_deepest_state) &&
			    (cx->core_state >= core_deepest_state)) {
				next_index = idx;
				break;
			}
		}
		/*
		 * C1 is always valid.
		 * So, no need to check for 'next_index == -1' outside
		 * this loop.
		 */
	}

	return next_index;
}

/**
 * omap3_enter_idle_bm - Checks for any bus activity
 * @dev: cpuidle device
 * @drv: cpuidle driver
 * @index: array index of target state to be programmed
 *
 * This function checks for any pending activity and then programs
 * the device to the specified or a safer state.
 */
static int omap3_enter_idle_bm(struct cpuidle_device *dev,
				struct cpuidle_driver *drv,
			       int index)
{
	int new_state_idx;
	u32 core_next_state, per_next_state = 0, per_saved_state = 0, cam_state;
	struct omap3_idle_statedata *cx;
	int ret;

	/*
	 * Prevent idle completely if CAM is active.
	 * CAM does not have wakeup capability in OMAP3.
	 */
	cam_state = pwrdm_read_pwrst(cam_pd);
	if (cam_state == PWRDM_POWER_ON) {
		new_state_idx = drv->safe_state_index;
		goto select_state;
	}

	/*
	 * FIXME: we currently manage device-specific idle states
	 *        for PER and CORE in combination with CPU-specific
	 *        idle states.  This is wrong, and device-specific
	 *        idle management needs to be separated out into
	 *        its own code.
	 */

	/*
	 * Prevent PER off if CORE is not in retention or off as this
	 * would disable PER wakeups completely.
	 */
	cx = cpuidle_get_statedata(&dev->states_usage[index]);
	core_next_state = cx->core_state;
	per_next_state = per_saved_state = pwrdm_read_next_pwrst(per_pd);
	if ((per_next_state == PWRDM_POWER_OFF) &&
	    (core_next_state > PWRDM_POWER_RET))
		per_next_state = PWRDM_POWER_RET;

	/* Are we changing PER target state? */
	if (per_next_state != per_saved_state)
		pwrdm_set_next_pwrst(per_pd, per_next_state);

	new_state_idx = next_valid_state(dev, drv, index);

select_state:
	ret = omap3_enter_idle(dev, drv, new_state_idx);

	/* Restore original PER state if it was modified */
	if (per_next_state != per_saved_state)
		pwrdm_set_next_pwrst(per_pd, per_saved_state);

	return ret;
}

DEFINE_PER_CPU(struct cpuidle_device, omap3_idle_dev);

struct cpuidle_driver omap3_idle_driver = {
	.name = 	"omap3_idle",
	.owner = 	THIS_MODULE,
	.states = {
		{
			.enter		  = omap3_enter_idle,
			.exit_latency	  = 2 + 2,
			.target_residency = 5,
			.flags		  = CPUIDLE_FLAG_TIME_VALID,
			.name		  = "C1",
			.desc		  = "MPU ON + CORE ON",
		},
		{
			.enter		  = omap3_enter_idle_bm,
			.exit_latency	  = 10 + 10,
			.target_residency = 30,
			.flags		  = CPUIDLE_FLAG_TIME_VALID,
			.name		  = "C2",
			.desc		  = "MPU ON + CORE ON",
		},
		{
			.enter		  = omap3_enter_idle_bm,
			.exit_latency	  = 50 + 50,
			.target_residency = 300,
			.flags		  = CPUIDLE_FLAG_TIME_VALID,
			.name		  = "C3",
			.desc		  = "MPU RET + CORE ON",
		},
		{
			.enter		  = omap3_enter_idle_bm,
			.exit_latency	  = 1500 + 1800,
			.target_residency = 4000,
			.flags		  = CPUIDLE_FLAG_TIME_VALID,
			.name		  = "C4",
			.desc		  = "MPU OFF + CORE ON",
		},
		{
			.enter		  = omap3_enter_idle_bm,
			.exit_latency	  = 2500 + 7500,
			.target_residency = 12000,
			.flags		  = CPUIDLE_FLAG_TIME_VALID,
			.name		  = "C5",
			.desc		  = "MPU RET + CORE RET",
		},
		{
			.enter		  = omap3_enter_idle_bm,
			.exit_latency	  = 3000 + 8500,
			.target_residency = 15000,
			.flags		  = CPUIDLE_FLAG_TIME_VALID,
			.name		  = "C6",
			.desc		  = "MPU OFF + CORE RET",
		},
		{
			.enter		  = omap3_enter_idle_bm,
			.exit_latency	  = 10000 + 30000,
			.target_residency = 30000,
			.flags		  = CPUIDLE_FLAG_TIME_VALID,
			.name		  = "C7",
			.desc		  = "MPU OFF + CORE OFF",
		},
	},
	.state_count = OMAP3_NUM_STATES,
	.safe_state_index = 0,
};

/* Helper to register the driver_data */
static inline struct omap3_idle_statedata *_fill_cstate_usage(
					struct cpuidle_device *dev,
					int idx)
{
	struct omap3_idle_statedata *cx = &omap3_idle_data[idx];
	struct cpuidle_state_usage *state_usage = &dev->states_usage[idx];

	cpuidle_set_statedata(state_usage, cx);

	return cx;
}

/**
 * omap3_idle_init - Init routine for OMAP3 idle
 *
 * Registers the OMAP3 specific cpuidle driver to the cpuidle
 * framework with the valid set of states.
 */
int __init omap3_idle_init(void)
{
	struct cpuidle_device *dev;
	struct omap3_idle_statedata *cx;

	mpu_pd = pwrdm_lookup("mpu_pwrdm");
	core_pd = pwrdm_lookup("core_pwrdm");
	per_pd = pwrdm_lookup("per_pwrdm");
	cam_pd = pwrdm_lookup("cam_pwrdm");


	dev = &per_cpu(omap3_idle_dev, smp_processor_id());

	/* C1 . MPU WFI + Core active */
	cx = _fill_cstate_usage(dev, 0);
	cx->mpu_state = PWRDM_POWER_ON;
	cx->core_state = PWRDM_POWER_ON;

	/* C2 . MPU WFI + Core inactive */
	cx = _fill_cstate_usage(dev, 1);
	cx->mpu_state = PWRDM_POWER_ON;
	cx->core_state = PWRDM_POWER_ON;

	/* C3 . MPU CSWR + Core inactive */
	cx = _fill_cstate_usage(dev, 2);
	cx->mpu_state = PWRDM_POWER_RET;
	cx->core_state = PWRDM_POWER_ON;

	/* C4 . MPU OFF + Core inactive */
	cx = _fill_cstate_usage(dev, 3);
	cx->mpu_state = PWRDM_POWER_OFF;
	cx->core_state = PWRDM_POWER_ON;

	/* C5 . MPU RET + Core RET */
	cx = _fill_cstate_usage(dev, 4);
	cx->mpu_state = PWRDM_POWER_RET;
	cx->core_state = PWRDM_POWER_RET;

	/* C6 . MPU OFF + Core RET */
	cx = _fill_cstate_usage(dev, 5);
	cx->mpu_state = PWRDM_POWER_OFF;
	cx->core_state = PWRDM_POWER_RET;

	/* C7 . MPU OFF + Core OFF */
	cx = _fill_cstate_usage(dev, 6);
	cx->mpu_state = PWRDM_POWER_OFF;
	cx->core_state = PWRDM_POWER_OFF;

	cpuidle_register_driver(&omap3_idle_driver);

	if (cpuidle_register_device(dev)) {
		printk(KERN_ERR "%s: CPUidle register device failed\n",
		       __func__);
		return -EIO;
	}

	return 0;
}
#else
int __init omap3_idle_init(void)
{
	return 0;
}
#endif /* CONFIG_CPU_IDLE */
Commit	Line	Data
99e6a4d2 RN	1	/*
	2	* linux/arch/arm/mach-omap2/cpuidle34xx.c
	3	*
	4	* OMAP3 CPU IDLE Routines
	5	*
	6	* Copyright (C) 2008 Texas Instruments, Inc.
	7	* Rajendra Nayak <rnayak@ti.com>
	8	*
	9	* Copyright (C) 2007 Texas Instruments, Inc.
	10	* Karthik Dasu <karthik-dp@ti.com>
	11	*
	12	* Copyright (C) 2006 Nokia Corporation
	13	* Tony Lindgren <tony@atomide.com>
	14	*
	15	* Copyright (C) 2005 Texas Instruments, Inc.
	16	* Richard Woodruff <r-woodruff2@ti.com>
	17	*
	18	* Based on pm.c for omap2
	19	*
	20	* This program is free software; you can redistribute it and/or modify
	21	* it under the terms of the GNU General Public License version 2 as
	22	* published by the Free Software Foundation.
	23	*/
	24
cf22854c	25	#include <linux/sched.h>
99e6a4d2	26	#include <linux/cpuidle.h>
5698eb4e	27	#include <linux/export.h>
ff819da4	28	#include <linux/cpu_pm.h>
99e6a4d2 RN	29
99e6a4d2 RN	30	#include <plat/prcm.h>
20b01669	31	#include <plat/irqs.h>
72e06d08	32	#include "powerdomain.h"
1540f214	33	#include "clockdomain.h"
99e6a4d2	34
c98e2230	35	#include "pm.h"
4814ced5	36	#include "control.h"
ba8bb18a	37	#include "common.h"
c98e2230	38
99e6a4d2 RN	39	#ifdef CONFIG_CPU_IDLE
99e6a4d2 RN	40
bb4de3df KH	41	/*
	42	* The latencies/thresholds for various C states have
	43	* to be configured from the respective board files.
	44	* These are some default values (which might not provide
	45	* the best power savings) used on boards which do not
	46	* pass these details from the board file.
	47	*/
	48	static struct cpuidle_params cpuidle_params_table[] = {
	49	/* C1 */
866ba0ef	50	{2 + 2, 5, 1},
bb4de3df	51	/* C2 */
866ba0ef	52	{10 + 10, 30, 1},
bb4de3df	53	/* C3 */
866ba0ef	54	{50 + 50, 300, 1},
bb4de3df	55	/* C4 */
866ba0ef	56	{1500 + 1800, 4000, 1},
bb4de3df	57	/* C5 */
866ba0ef	58	{2500 + 7500, 12000, 1},
bb4de3df	59	/* C6 */
866ba0ef	60	{3000 + 8500, 15000, 1},
bb4de3df	61	/* C7 */
866ba0ef	62	{10000 + 30000, 300000, 1},
bb4de3df	63	};
badc303a JP	64	#define OMAP3_NUM_STATES ARRAY_SIZE(cpuidle_params_table)
	65
	66	/* Mach specific information to be recorded in the C-state driver_data */
	67	struct omap3_idle_statedata {
	68	u32 mpu_state;
	69	u32 core_state;
badc303a JP	70	};
	71	struct omap3_idle_statedata omap3_idle_data[OMAP3_NUM_STATES];
	72
	73	struct powerdomain mpu_pd, core_pd, per_pd, cam_pd;
bb4de3df	74
06d8f065 PDS	75	static int _cpuidle_allow_idle(struct powerdomain *pwrdm,
	76	struct clockdomain *clkdm)
	77	{
5cd1937b	78	clkdm_allow_idle(clkdm);
06d8f065 PDS	79	return 0;
	80	}
	81
	82	static int _cpuidle_deny_idle(struct powerdomain *pwrdm,
	83	struct clockdomain *clkdm)
	84	{
5cd1937b	85	clkdm_deny_idle(clkdm);
06d8f065 PDS	86	return 0;
	87	}
	88
6da45dce	89	static int __omap3_enter_idle(struct cpuidle_device *dev,
46bcfad7	90	struct cpuidle_driver *drv,
e978aa7d	91	int index)
99e6a4d2	92	{
e978aa7d	93	struct omap3_idle_statedata *cx =
4202735e	94	cpuidle_get_statedata(&dev->states_usage[index]);
c98e2230	95	u32 mpu_state = cx->mpu_state, core_state = cx->core_state;
99e6a4d2	96
99e6a4d2 RN	97	local_fiq_disable();
99e6a4d2 RN	98
7139178e JH	99	pwrdm_set_next_pwrst(mpu_pd, mpu_state);
7139178e JH	100	pwrdm_set_next_pwrst(core_pd, core_state);
20b01669	101
cf22854c	102	if (omap_irq_pending() \|\| need_resched())
20b01669	103	goto return_sleep_time;
99e6a4d2	104
badc303a	105	/* Deny idle for C1 */
e978aa7d	106	if (index == 0) {
06d8f065 PDS	107	pwrdm_for_each_clkdm(mpu_pd, _cpuidle_deny_idle);
	108	pwrdm_for_each_clkdm(core_pd, _cpuidle_deny_idle);
	109	}
	110
ff819da4 SS	111	/*
	112	* Call idle CPU PM enter notifier chain so that
	113	* VFP context is saved.
	114	*/
	115	if (mpu_state == PWRDM_POWER_OFF)
	116	cpu_pm_enter();
	117
99e6a4d2 RN	118	/* Execute ARM wfi */
	119	omap_sram_idle();
	120
ff819da4 SS	121	/*
	122	* Call idle CPU PM enter notifier chain to restore
	123	* VFP context.
	124	*/
	125	if (pwrdm_read_prev_pwrst(mpu_pd) == PWRDM_POWER_OFF)
	126	cpu_pm_exit();
	127
badc303a	128	/* Re-allow idle for C1 */
e978aa7d	129	if (index == 0) {
06d8f065 PDS	130	pwrdm_for_each_clkdm(mpu_pd, _cpuidle_allow_idle);
	131	pwrdm_for_each_clkdm(core_pd, _cpuidle_allow_idle);
	132	}
	133
20b01669	134	return_sleep_time:
99e6a4d2	135
99e6a4d2 RN	136	local_fiq_enable();
99e6a4d2 RN	137
e978aa7d	138	return index;
99e6a4d2 RN	139	}
99e6a4d2 RN	140
6da45dce RL	141	/**
	142	* omap3_enter_idle - Programs OMAP3 to enter the specified state
	143	* @dev: cpuidle device
	144	* @drv: cpuidle driver
	145	* @index: the index of state to be entered
	146	*
	147	* Called from the CPUidle framework to program the device to the
	148	* specified target state selected by the governor.
	149	*/
	150	static inline int omap3_enter_idle(struct cpuidle_device *dev,
	151	struct cpuidle_driver *drv,
	152	int index)
	153	{
	154	return cpuidle_wrap_enter(dev, drv, index, __omap3_enter_idle);
	155	}
	156
6af83b38	157	/**
04908918	158	* next_valid_state - Find next valid C-state
6af83b38	159	* @dev: cpuidle device
46bcfad7	160	* @drv: cpuidle driver
e978aa7d	161	* @index: Index of currently selected c-state
6af83b38	162	*
e978aa7d DD	163	* If the state corresponding to index is valid, index is returned back
	164	* to the caller. Else, this function searches for a lower c-state which is
	165	* still valid (as defined in omap3_power_states[]) and returns its index.
04908918 JP	166	*
	167	* A state is valid if the 'valid' field is enabled and
	168	* if it satisfies the enable_off_mode condition.
6af83b38	169	*/
e978aa7d	170	static int next_valid_state(struct cpuidle_device *dev,
46bcfad7	171	struct cpuidle_driver *drv,
e978aa7d	172	int index)
6af83b38	173	{
4202735e	174	struct cpuidle_state_usage *curr_usage = &dev->states_usage[index];
46bcfad7	175	struct cpuidle_state *curr = &drv->states[index];
4202735e	176	struct omap3_idle_statedata *cx = cpuidle_get_statedata(curr_usage);
04908918 JP	177	u32 mpu_deepest_state = PWRDM_POWER_RET;
04908918 JP	178	u32 core_deepest_state = PWRDM_POWER_RET;
e978aa7d	179	int next_index = -1;
04908918 JP	180
	181	if (enable_off_mode) {
	182	mpu_deepest_state = PWRDM_POWER_OFF;
	183	/*
	184	* Erratum i583: valable for ES rev < Es1.2 on 3630.
	185	* CORE OFF mode is not supported in a stable form, restrict
	186	* instead the CORE state to RET.
	187	*/
	188	if (!IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583))
	189	core_deepest_state = PWRDM_POWER_OFF;
	190	}
6af83b38 SP	191
6af83b38 SP	192	/* Check if current state is valid */
f79b5d8a	193	if ((cx->mpu_state >= mpu_deepest_state) &&
04908918	194	(cx->core_state >= core_deepest_state)) {
e978aa7d	195	return index;
6af83b38	196	} else {
badc303a	197	int idx = OMAP3_NUM_STATES - 1;
6af83b38	198
c6cd91de	199	/* Reach the current state starting at highest C-state */
badc303a	200	for (; idx >= 0; idx--) {
46bcfad7	201	if (&drv->states[idx] == curr) {
e978aa7d	202	next_index = idx;
6af83b38 SP	203	break;
	204	}
	205	}
	206
c6cd91de	207	/* Should never hit this condition */
e978aa7d	208	WARN_ON(next_index == -1);
6af83b38 SP	209
	210	/*
	211	* Drop to next valid state.
	212	* Start search from the next (lower) state.
	213	*/
	214	idx--;
badc303a	215	for (; idx >= 0; idx--) {
4202735e	216	cx = cpuidle_get_statedata(&dev->states_usage[idx]);
f79b5d8a	217	if ((cx->mpu_state >= mpu_deepest_state) &&
04908918	218	(cx->core_state >= core_deepest_state)) {
e978aa7d	219	next_index = idx;
6af83b38 SP	220	break;
	221	}
	222	}
	223	/*
badc303a	224	* C1 is always valid.
e978aa7d DD	225	* So, no need to check for 'next_index == -1' outside
e978aa7d DD	226	* this loop.
6af83b38 SP	227	*/
	228	}
	229
e978aa7d	230	return next_index;
6af83b38 SP	231	}
6af83b38 SP	232
99e6a4d2 RN	233	/**
	234	* omap3_enter_idle_bm - Checks for any bus activity
	235	* @dev: cpuidle device
46bcfad7	236	* @drv: cpuidle driver
e978aa7d	237	* @index: array index of target state to be programmed
99e6a4d2	238	*
badc303a JP	239	* This function checks for any pending activity and then programs
badc303a JP	240	* the device to the specified or a safer state.
99e6a4d2 RN	241	*/
99e6a4d2 RN	242	static int omap3_enter_idle_bm(struct cpuidle_device *dev,
46bcfad7	243	struct cpuidle_driver *drv,
e978aa7d	244	int index)
99e6a4d2	245	{
e978aa7d	246	int new_state_idx;
c6cd91de	247	u32 core_next_state, per_next_state = 0, per_saved_state = 0, cam_state;
badc303a	248	struct omap3_idle_statedata *cx;
e7410cf7	249	int ret;
0f724ed9	250
e7410cf7 KH	251	/*
	252	* Prevent idle completely if CAM is active.
	253	* CAM does not have wakeup capability in OMAP3.
	254	*/
	255	cam_state = pwrdm_read_pwrst(cam_pd);
	256	if (cam_state == PWRDM_POWER_ON) {
46bcfad7	257	new_state_idx = drv->safe_state_index;
e7410cf7 KH	258	goto select_state;
	259	}
	260
c6cd91de JP	261	/*
	262	* FIXME: we currently manage device-specific idle states
	263	* for PER and CORE in combination with CPU-specific
	264	* idle states. This is wrong, and device-specific
	265	* idle management needs to be separated out into
	266	* its own code.
	267	*/
	268
e7410cf7 KH	269	/*
	270	* Prevent PER off if CORE is not in retention or off as this
	271	* would disable PER wakeups completely.
	272	*/
4202735e	273	cx = cpuidle_get_statedata(&dev->states_usage[index]);
c6cd91de	274	core_next_state = cx->core_state;
e7410cf7 KH	275	per_next_state = per_saved_state = pwrdm_read_next_pwrst(per_pd);
e7410cf7 KH	276	if ((per_next_state == PWRDM_POWER_OFF) &&
65707fb3	277	(core_next_state > PWRDM_POWER_RET))
e7410cf7	278	per_next_state = PWRDM_POWER_RET;
0f724ed9	279
e7410cf7 KH	280	/* Are we changing PER target state? */
	281	if (per_next_state != per_saved_state)
	282	pwrdm_set_next_pwrst(per_pd, per_next_state);
	283
46bcfad7	284	new_state_idx = next_valid_state(dev, drv, index);
c6cd91de	285
e7410cf7	286	select_state:
46bcfad7	287	ret = omap3_enter_idle(dev, drv, new_state_idx);
e7410cf7 KH	288
	289	/* Restore original PER state if it was modified */
	290	if (per_next_state != per_saved_state)
	291	pwrdm_set_next_pwrst(per_pd, per_saved_state);
	292
	293	return ret;
99e6a4d2 RN	294	}
	295
	296	DEFINE_PER_CPU(struct cpuidle_device, omap3_idle_dev);
	297
99e6a4d2 RN	298	struct cpuidle_driver omap3_idle_driver = {
	299	.name = "omap3_idle",
	300	.owner = THIS_MODULE,
200dd520 DL	301	.states = {
	302	{
	303	.enter = omap3_enter_idle,
	304	.exit_latency = 2 + 2,
	305	.target_residency = 5,
	306	.flags = CPUIDLE_FLAG_TIME_VALID,
	307	.name = "C1",
	308	.desc = "MPU ON + CORE ON",
	309	},
	310	{
	311	.enter = omap3_enter_idle_bm,
	312	.exit_latency = 10 + 10,
	313	.target_residency = 30,
	314	.flags = CPUIDLE_FLAG_TIME_VALID,
	315	.name = "C2",
	316	.desc = "MPU ON + CORE ON",
	317	},
	318	{
	319	.enter = omap3_enter_idle_bm,
	320	.exit_latency = 50 + 50,
	321	.target_residency = 300,
	322	.flags = CPUIDLE_FLAG_TIME_VALID,
	323	.name = "C3",
	324	.desc = "MPU RET + CORE ON",
	325	},
	326	{
	327	.enter = omap3_enter_idle_bm,
	328	.exit_latency = 1500 + 1800,
	329	.target_residency = 4000,
	330	.flags = CPUIDLE_FLAG_TIME_VALID,
	331	.name = "C4",
	332	.desc = "MPU OFF + CORE ON",
	333	},
	334	{
	335	.enter = omap3_enter_idle_bm,
	336	.exit_latency = 2500 + 7500,
	337	.target_residency = 12000,
	338	.flags = CPUIDLE_FLAG_TIME_VALID,
	339	.name = "C5",
	340	.desc = "MPU RET + CORE RET",
	341	},
	342	{
	343	.enter = omap3_enter_idle_bm,
	344	.exit_latency = 3000 + 8500,
	345	.target_residency = 15000,
	346	.flags = CPUIDLE_FLAG_TIME_VALID,
	347	.name = "C6",
	348	.desc = "MPU OFF + CORE RET",
	349	},
	350	{
	351	.enter = omap3_enter_idle_bm,
	352	.exit_latency = 10000 + 30000,
	353	.target_residency = 30000,
	354	.flags = CPUIDLE_FLAG_TIME_VALID,
	355	.name = "C7",
	356	.desc = "MPU OFF + CORE OFF",
	357	},
	358	},
	359	.state_count = OMAP3_NUM_STATES,
	360	.safe_state_index = 0,
99e6a4d2 RN	361	};
99e6a4d2 RN	362
46bcfad7 DD	363	/* Helper to register the driver_data */
	364	static inline struct omap3_idle_statedata *_fill_cstate_usage(
	365	struct cpuidle_device *dev,
	366	int idx)
	367	{
	368	struct omap3_idle_statedata *cx = &omap3_idle_data[idx];
	369	struct cpuidle_state_usage *state_usage = &dev->states_usage[idx];
	370
4202735e	371	cpuidle_set_statedata(state_usage, cx);
badc303a JP	372
	373	return cx;
	374	}
	375
99e6a4d2 RN	376	/**
	377	* omap3_idle_init - Init routine for OMAP3 idle
	378	*
badc303a	379	* Registers the OMAP3 specific cpuidle driver to the cpuidle
99e6a4d2 RN	380	* framework with the valid set of states.
99e6a4d2 RN	381	*/
0343371e	382	int __init omap3_idle_init(void)
99e6a4d2	383	{
99e6a4d2	384	struct cpuidle_device *dev;
badc303a	385	struct omap3_idle_statedata *cx;
99e6a4d2 RN	386
99e6a4d2 RN	387	mpu_pd = pwrdm_lookup("mpu_pwrdm");
20b01669	388	core_pd = pwrdm_lookup("core_pwrdm");
e7410cf7 KH	389	per_pd = pwrdm_lookup("per_pwrdm");
e7410cf7 KH	390	cam_pd = pwrdm_lookup("cam_pwrdm");
99e6a4d2	391
46bcfad7	392
99e6a4d2 RN	393	dev = &per_cpu(omap3_idle_dev, smp_processor_id());
99e6a4d2 RN	394
badc303a	395	/* C1 . MPU WFI + Core active */
46bcfad7	396	cx = _fill_cstate_usage(dev, 0);
badc303a JP	397	cx->mpu_state = PWRDM_POWER_ON;
	398	cx->core_state = PWRDM_POWER_ON;
	399
	400	/* C2 . MPU WFI + Core inactive */
46bcfad7	401	cx = _fill_cstate_usage(dev, 1);
badc303a JP	402	cx->mpu_state = PWRDM_POWER_ON;
	403	cx->core_state = PWRDM_POWER_ON;
	404
	405	/* C3 . MPU CSWR + Core inactive */
46bcfad7	406	cx = _fill_cstate_usage(dev, 2);
badc303a JP	407	cx->mpu_state = PWRDM_POWER_RET;
	408	cx->core_state = PWRDM_POWER_ON;
	409
	410	/* C4 . MPU OFF + Core inactive */
46bcfad7	411	cx = _fill_cstate_usage(dev, 3);
badc303a JP	412	cx->mpu_state = PWRDM_POWER_OFF;
	413	cx->core_state = PWRDM_POWER_ON;
	414
	415	/* C5 . MPU RET + Core RET */
46bcfad7	416	cx = _fill_cstate_usage(dev, 4);
badc303a JP	417	cx->mpu_state = PWRDM_POWER_RET;
badc303a JP	418	cx->core_state = PWRDM_POWER_RET;
99e6a4d2	419
badc303a	420	/* C6 . MPU OFF + Core RET */
46bcfad7	421	cx = _fill_cstate_usage(dev, 5);
badc303a JP	422	cx->mpu_state = PWRDM_POWER_OFF;
	423	cx->core_state = PWRDM_POWER_RET;
	424
	425	/* C7 . MPU OFF + Core OFF */
46bcfad7	426	cx = _fill_cstate_usage(dev, 6);
badc303a JP	427	cx->mpu_state = PWRDM_POWER_OFF;
badc303a JP	428	cx->core_state = PWRDM_POWER_OFF;
99e6a4d2	429
46bcfad7 DD	430	cpuidle_register_driver(&omap3_idle_driver);
46bcfad7 DD	431
99e6a4d2 RN	432	if (cpuidle_register_device(dev)) {
	433	printk(KERN_ERR "%s: CPUidle register device failed\n",
	434	__func__);
	435	return -EIO;
	436	}
	437
	438	return 0;
	439	}
0343371e KJ	440	#else
	441	int __init omap3_idle_init(void)
	442	{
	443	return 0;
	444	}
99e6a4d2	445	#endif /* CONFIG_CPU_IDLE */