[deliverable/linux.git] / arch / arm / mach-omap2 / cpuidle44xx.c

/*
 * OMAP4+ CPU idle Routines
 *
 * Copyright (C) 2011-2013 Texas Instruments, Inc.
 * Santosh Shilimkar <santosh.shilimkar@ti.com>
 * Rajendra Nayak <rnayak@ti.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/sched.h>
#include <linux/cpuidle.h>
#include <linux/cpu_pm.h>
#include <linux/export.h>
#include <linux/clockchips.h>

#include <asm/cpuidle.h>
#include <asm/proc-fns.h>

#include "common.h"
#include "pm.h"
#include "prm.h"
#include "clockdomain.h"

#define MAX_CPUS	2

/* Machine specific information */
struct idle_statedata {
	u32 cpu_state;
	u32 mpu_logic_state;
	u32 mpu_state;
};

static struct idle_statedata omap4_idle_data[] = {
	{
		.cpu_state = PWRDM_POWER_ON,
		.mpu_state = PWRDM_POWER_ON,
		.mpu_logic_state = PWRDM_POWER_RET,
	},
	{
		.cpu_state = PWRDM_POWER_OFF,
		.mpu_state = PWRDM_POWER_RET,
		.mpu_logic_state = PWRDM_POWER_RET,
	},
	{
		.cpu_state = PWRDM_POWER_OFF,
		.mpu_state = PWRDM_POWER_RET,
		.mpu_logic_state = PWRDM_POWER_OFF,
	},
};

static struct powerdomain *mpu_pd, *cpu_pd[MAX_CPUS];
static struct clockdomain *cpu_clkdm[MAX_CPUS];

static atomic_t abort_barrier;
static bool cpu_done[MAX_CPUS];
static struct idle_statedata *state_ptr = &omap4_idle_data[0];

/* Private functions */

/**
 * omap_enter_idle_[simple/coupled] - OMAP4PLUS cpuidle entry functions
 * @dev: cpuidle device
 * @drv: cpuidle driver
 * @index: the index of state to be entered
 *
 * Called from the CPUidle framework to program the device to the
 * specified low power state selected by the governor.
 * Returns the amount of time spent in the low power state.
 */
static int omap_enter_idle_simple(struct cpuidle_device *dev,
			struct cpuidle_driver *drv,
			int index)
{
	omap_do_wfi();
	return index;
}

static int omap_enter_idle_coupled(struct cpuidle_device *dev,
			struct cpuidle_driver *drv,
			int index)
{
	struct idle_statedata *cx = state_ptr + index;
	u32 mpuss_can_lose_context = 0;
	int cpu_id = smp_processor_id();

	/*
	 * CPU0 has to wait and stay ON until CPU1 is OFF state.
	 * This is necessary to honour hardware recommondation
	 * of triggeing all the possible low power modes once CPU1 is
	 * out of coherency and in OFF mode.
	 */
	if (dev->cpu == 0 && cpumask_test_cpu(1, cpu_online_mask)) {
		while (pwrdm_read_pwrst(cpu_pd[1]) != PWRDM_POWER_OFF) {
			cpu_relax();

			/*
			 * CPU1 could have already entered & exited idle
			 * without hitting off because of a wakeup
			 * or a failed attempt to hit off mode.  Check for
			 * that here, otherwise we could spin forever
			 * waiting for CPU1 off.
			 */
			if (cpu_done[1])
			    goto fail;

		}
	}

	mpuss_can_lose_context = (cx->mpu_state == PWRDM_POWER_RET) &&
				 (cx->mpu_logic_state == PWRDM_POWER_OFF);

	clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &cpu_id);

	/*
	 * Call idle CPU PM enter notifier chain so that
	 * VFP and per CPU interrupt context is saved.
	 */
	cpu_pm_enter();

	if (dev->cpu == 0) {
		pwrdm_set_logic_retst(mpu_pd, cx->mpu_logic_state);
		omap_set_pwrdm_state(mpu_pd, cx->mpu_state);

		/*
		 * Call idle CPU cluster PM enter notifier chain
		 * to save GIC and wakeupgen context.
		 */
		if (mpuss_can_lose_context)
			cpu_cluster_pm_enter();
	}

	omap4_enter_lowpower(dev->cpu, cx->cpu_state);
	cpu_done[dev->cpu] = true;

	/* Wakeup CPU1 only if it is not offlined */
	if (dev->cpu == 0 && cpumask_test_cpu(1, cpu_online_mask)) {

		if (IS_PM44XX_ERRATUM(PM_OMAP4_ROM_SMP_BOOT_ERRATUM_GICD) &&
		    mpuss_can_lose_context)
			gic_dist_disable();

		clkdm_wakeup(cpu_clkdm[1]);
		omap_set_pwrdm_state(cpu_pd[1], PWRDM_POWER_ON);
		clkdm_allow_idle(cpu_clkdm[1]);

		if (IS_PM44XX_ERRATUM(PM_OMAP4_ROM_SMP_BOOT_ERRATUM_GICD) &&
		    mpuss_can_lose_context) {
			while (gic_dist_disabled()) {
				udelay(1);
				cpu_relax();
			}
			gic_timer_retrigger();
		}
	}

	/*
	 * Call idle CPU PM exit notifier chain to restore
	 * VFP and per CPU IRQ context.
	 */
	cpu_pm_exit();

	/*
	 * Call idle CPU cluster PM exit notifier chain
	 * to restore GIC and wakeupgen context.
	 */
	if (dev->cpu == 0 && mpuss_can_lose_context)
		cpu_cluster_pm_exit();

	clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &cpu_id);

fail:
	cpuidle_coupled_parallel_barrier(dev, &abort_barrier);
	cpu_done[dev->cpu] = false;

	return index;
}

/*
 * For each cpu, setup the broadcast timer because local timers
 * stops for the states above C1.
 */
static void omap_setup_broadcast_timer(void *arg)
{
	int cpu = smp_processor_id();
	clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ON, &cpu);
}

static struct cpuidle_driver omap4_idle_driver = {
	.name				= "omap4_idle",
	.owner				= THIS_MODULE,
	.states = {
		{
			/* C1 - CPU0 ON + CPU1 ON + MPU ON */
			.exit_latency = 2 + 2,
			.target_residency = 5,
			.flags = CPUIDLE_FLAG_TIME_VALID,
			.enter = omap_enter_idle_simple,
			.name = "C1",
			.desc = "CPUx ON, MPUSS ON"
		},
		{
			/* C2 - CPU0 OFF + CPU1 OFF + MPU CSWR */
			.exit_latency = 328 + 440,
			.target_residency = 960,
			.flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_COUPLED,
			.enter = omap_enter_idle_coupled,
			.name = "C2",
			.desc = "CPUx OFF, MPUSS CSWR",
		},
		{
			/* C3 - CPU0 OFF + CPU1 OFF + MPU OSWR */
			.exit_latency = 460 + 518,
			.target_residency = 1100,
			.flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_COUPLED,
			.enter = omap_enter_idle_coupled,
			.name = "C3",
			.desc = "CPUx OFF, MPUSS OSWR",
		},
	},
	.state_count = ARRAY_SIZE(omap4_idle_data),
	.safe_state_index = 0,
};

/* Public functions */

/**
 * omap4_idle_init - Init routine for OMAP4+ idle
 *
 * Registers the OMAP4+ specific cpuidle driver to the cpuidle
 * framework with the valid set of states.
 */
int __init omap4_idle_init(void)
{
	mpu_pd = pwrdm_lookup("mpu_pwrdm");
	cpu_pd[0] = pwrdm_lookup("cpu0_pwrdm");
	cpu_pd[1] = pwrdm_lookup("cpu1_pwrdm");
	if ((!mpu_pd) || (!cpu_pd[0]) || (!cpu_pd[1]))
		return -ENODEV;

	cpu_clkdm[0] = clkdm_lookup("mpu0_clkdm");
	cpu_clkdm[1] = clkdm_lookup("mpu1_clkdm");
	if (!cpu_clkdm[0] || !cpu_clkdm[1])
		return -ENODEV;

	/* Configure the broadcast timer on each cpu */
	on_each_cpu(omap_setup_broadcast_timer, NULL, 1);

	return cpuidle_register(&omap4_idle_driver, cpu_online_mask);
}
Commit	Line	Data
98272660	1	/*
db4f3dab	2	* OMAP4+ CPU idle Routines
98272660	3	*
db4f3dab	4	* Copyright (C) 2011-2013 Texas Instruments, Inc.
98272660 SS	5	* Santosh Shilimkar <santosh.shilimkar@ti.com>
	6	* Rajendra Nayak <rnayak@ti.com>
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License version 2 as
	10	* published by the Free Software Foundation.
	11	*/
	12
	13	#include <linux/sched.h>
	14	#include <linux/cpuidle.h>
	15	#include <linux/cpu_pm.h>
	16	#include <linux/export.h>
4b353a70	17	#include <linux/clockchips.h>
98272660	18
0e9e8b4b	19	#include <asm/cpuidle.h>
98272660 SS	20	#include <asm/proc-fns.h>
	21
	22	#include "common.h"
	23	#include "pm.h"
	24	#include "prm.h"
dd3ad97c	25	#include "clockdomain.h"
98272660	26
865da01c SS	27	#define MAX_CPUS 2
865da01c SS	28
7aeb658d	29	/* Machine specific information */
db4f3dab	30	struct idle_statedata {
98272660 SS	31	u32 cpu_state;
	32	u32 mpu_logic_state;
	33	u32 mpu_state;
98272660 SS	34	};
98272660 SS	35
db4f3dab	36	static struct idle_statedata omap4_idle_data[] = {
d0d133d9 DL	37	{
	38	.cpu_state = PWRDM_POWER_ON,
	39	.mpu_state = PWRDM_POWER_ON,
	40	.mpu_logic_state = PWRDM_POWER_RET,
	41	},
	42	{
	43	.cpu_state = PWRDM_POWER_OFF,
	44	.mpu_state = PWRDM_POWER_RET,
	45	.mpu_logic_state = PWRDM_POWER_RET,
	46	},
	47	{
	48	.cpu_state = PWRDM_POWER_OFF,
	49	.mpu_state = PWRDM_POWER_RET,
	50	.mpu_logic_state = PWRDM_POWER_OFF,
	51	},
	52	};
98272660	53
865da01c SS	54	static struct powerdomain mpu_pd, cpu_pd[MAX_CPUS];
865da01c SS	55	static struct clockdomain *cpu_clkdm[MAX_CPUS];
98272660	56
5b4d5bcc	57	static atomic_t abort_barrier;
865da01c	58	static bool cpu_done[MAX_CPUS];
db4f3dab	59	static struct idle_statedata *state_ptr = &omap4_idle_data[0];
98272660	60
9db316b6 PW	61	/* Private functions */
9db316b6 PW	62
98272660	63	/**
db4f3dab	64	* omap_enter_idle_[simple/coupled] - OMAP4PLUS cpuidle entry functions
98272660 SS	65	* @dev: cpuidle device
	66	* @drv: cpuidle driver
	67	* @index: the index of state to be entered
	68	*
	69	* Called from the CPUidle framework to program the device to the
	70	* specified low power state selected by the governor.
	71	* Returns the amount of time spent in the low power state.
	72	*/
db4f3dab	73	static int omap_enter_idle_simple(struct cpuidle_device *dev,
dd3ad97c SS	74	struct cpuidle_driver *drv,
	75	int index)
	76	{
dd3ad97c	77	omap_do_wfi();
dd3ad97c SS	78	return index;
	79	}
	80
db4f3dab	81	static int omap_enter_idle_coupled(struct cpuidle_device *dev,
98272660 SS	82	struct cpuidle_driver *drv,
	83	int index)
	84	{
db4f3dab	85	struct idle_statedata *cx = state_ptr + index;
74ed7bdc	86	u32 mpuss_can_lose_context = 0;
4b353a70	87	int cpu_id = smp_processor_id();
98272660	88
98272660	89	/*
dd3ad97c	90	* CPU0 has to wait and stay ON until CPU1 is OFF state.
98272660 SS	91	* This is necessary to honour hardware recommondation
	92	* of triggeing all the possible low power modes once CPU1 is
	93	* out of coherency and in OFF mode.
98272660	94	*/
dd3ad97c	95	if (dev->cpu == 0 && cpumask_test_cpu(1, cpu_online_mask)) {
5b4d5bcc	96	while (pwrdm_read_pwrst(cpu_pd[1]) != PWRDM_POWER_OFF) {
dd3ad97c	97	cpu_relax();
5b4d5bcc KH	98
	99	/*
	100	* CPU1 could have already entered & exited idle
	101	* without hitting off because of a wakeup
	102	* or a failed attempt to hit off mode. Check for
	103	* that here, otherwise we could spin forever
	104	* waiting for CPU1 off.
	105	*/
	106	if (cpu_done[1])
	107	goto fail;
	108
	109	}
98272660 SS	110	}
98272660 SS	111
74ed7bdc SG	112	mpuss_can_lose_context = (cx->mpu_state == PWRDM_POWER_RET) &&
	113	(cx->mpu_logic_state == PWRDM_POWER_OFF);
	114
4b353a70 SS	115	clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &cpu_id);
4b353a70 SS	116
98272660 SS	117	/*
	118	* Call idle CPU PM enter notifier chain so that
	119	* VFP and per CPU interrupt context is saved.
	120	*/
dd3ad97c SS	121	cpu_pm_enter();
	122
	123	if (dev->cpu == 0) {
	124	pwrdm_set_logic_retst(mpu_pd, cx->mpu_logic_state);
	125	omap_set_pwrdm_state(mpu_pd, cx->mpu_state);
	126
	127	/*
	128	* Call idle CPU cluster PM enter notifier chain
	129	* to save GIC and wakeupgen context.
	130	*/
74ed7bdc SG	131	if (mpuss_can_lose_context)
74ed7bdc SG	132	cpu_cluster_pm_enter();
dd3ad97c	133	}
98272660 SS	134
98272660 SS	135	omap4_enter_lowpower(dev->cpu, cx->cpu_state);
5b4d5bcc	136	cpu_done[dev->cpu] = true;
98272660	137
dd3ad97c SS	138	/* Wakeup CPU1 only if it is not offlined */
dd3ad97c SS	139	if (dev->cpu == 0 && cpumask_test_cpu(1, cpu_online_mask)) {
74ed7bdc SG	140
	141	if (IS_PM44XX_ERRATUM(PM_OMAP4_ROM_SMP_BOOT_ERRATUM_GICD) &&
	142	mpuss_can_lose_context)
	143	gic_dist_disable();
	144
dd3ad97c	145	clkdm_wakeup(cpu_clkdm[1]);
b7806dc7	146	omap_set_pwrdm_state(cpu_pd[1], PWRDM_POWER_ON);
dd3ad97c	147	clkdm_allow_idle(cpu_clkdm[1]);
74ed7bdc SG	148
	149	if (IS_PM44XX_ERRATUM(PM_OMAP4_ROM_SMP_BOOT_ERRATUM_GICD) &&
	150	mpuss_can_lose_context) {
	151	while (gic_dist_disabled()) {
	152	udelay(1);
	153	cpu_relax();
	154	}
	155	gic_timer_retrigger();
	156	}
dd3ad97c	157	}
98272660 SS	158
	159	/*
	160	* Call idle CPU PM exit notifier chain to restore
dd3ad97c	161	* VFP and per CPU IRQ context.
98272660	162	*/
dd3ad97c	163	cpu_pm_exit();
98272660 SS	164
	165	/*
	166	* Call idle CPU cluster PM exit notifier chain
	167	* to restore GIC and wakeupgen context.
	168	*/
74ed7bdc	169	if (dev->cpu == 0 && mpuss_can_lose_context)
98272660 SS	170	cpu_cluster_pm_exit();
98272660 SS	171
4b353a70 SS	172	clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &cpu_id);
4b353a70 SS	173
5b4d5bcc KH	174	fail:
	175	cpuidle_coupled_parallel_barrier(dev, &abort_barrier);
	176	cpu_done[dev->cpu] = false;
98be0dde	177
98272660 SS	178	return index;
	179	}
	180
4b353a70 SS	181	/*
	182	* For each cpu, setup the broadcast timer because local timers
	183	* stops for the states above C1.
	184	*/
	185	static void omap_setup_broadcast_timer(void *arg)
	186	{
	187	int cpu = smp_processor_id();
	188	clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ON, &cpu);
	189	}
	190
9db316b6	191	static struct cpuidle_driver omap4_idle_driver = {
d13e9261 RL	192	.name = "omap4_idle",
d13e9261 RL	193	.owner = THIS_MODULE,
78e9016f DL	194	.states = {
	195	{
	196	/* C1 - CPU0 ON + CPU1 ON + MPU ON */
	197	.exit_latency = 2 + 2,
	198	.target_residency = 5,
	199	.flags = CPUIDLE_FLAG_TIME_VALID,
db4f3dab	200	.enter = omap_enter_idle_simple,
78e9016f	201	.name = "C1",
eb495d33	202	.desc = "CPUx ON, MPUSS ON"
78e9016f DL	203	},
78e9016f DL	204	{
9db316b6	205	/* C2 - CPU0 OFF + CPU1 OFF + MPU CSWR */
78e9016f DL	206	.exit_latency = 328 + 440,
78e9016f DL	207	.target_residency = 960,
4b353a70	208	.flags = CPUIDLE_FLAG_TIME_VALID \| CPUIDLE_FLAG_COUPLED,
db4f3dab	209	.enter = omap_enter_idle_coupled,
78e9016f	210	.name = "C2",
eb495d33	211	.desc = "CPUx OFF, MPUSS CSWR",
78e9016f DL	212	},
	213	{
	214	/* C3 - CPU0 OFF + CPU1 OFF + MPU OSWR */
	215	.exit_latency = 460 + 518,
	216	.target_residency = 1100,
4b353a70	217	.flags = CPUIDLE_FLAG_TIME_VALID \| CPUIDLE_FLAG_COUPLED,
db4f3dab	218	.enter = omap_enter_idle_coupled,
78e9016f	219	.name = "C3",
eb495d33	220	.desc = "CPUx OFF, MPUSS OSWR",
78e9016f DL	221	},
78e9016f DL	222	},
d0d133d9	223	.state_count = ARRAY_SIZE(omap4_idle_data),
78e9016f	224	.safe_state_index = 0,
98272660 SS	225	};
98272660 SS	226
9db316b6	227	/* Public functions */
b93d70ae	228
98272660	229	/**
db4f3dab	230	* omap4_idle_init - Init routine for OMAP4+ idle
98272660	231	*
db4f3dab	232	* Registers the OMAP4+ specific cpuidle driver to the cpuidle
98272660 SS	233	* framework with the valid set of states.
	234	*/
	235	int __init omap4_idle_init(void)
	236	{
98272660	237	mpu_pd = pwrdm_lookup("mpu_pwrdm");
dd3ad97c SS	238	cpu_pd[0] = pwrdm_lookup("cpu0_pwrdm");
	239	cpu_pd[1] = pwrdm_lookup("cpu1_pwrdm");
	240	if ((!mpu_pd) \|\| (!cpu_pd[0]) \|\| (!cpu_pd[1]))
98272660 SS	241	return -ENODEV;
98272660 SS	242
dd3ad97c SS	243	cpu_clkdm[0] = clkdm_lookup("mpu0_clkdm");
	244	cpu_clkdm[1] = clkdm_lookup("mpu1_clkdm");
	245	if (!cpu_clkdm[0] \|\| !cpu_clkdm[1])
98272660 SS	246	return -ENODEV;
98272660 SS	247
4b353a70 SS	248	/* Configure the broadcast timer on each cpu */
	249	on_each_cpu(omap_setup_broadcast_timer, NULL, 1);
	250
0e9e8b4b	251	return cpuidle_register(&omap4_idle_driver, cpu_online_mask);
98272660	252	}