[deliverable/linux.git] / arch / arm / mach-omap2 / cpuidle44xx.c

/*
 * OMAP4 CPU idle Routines
 *
 * Copyright (C) 2011 Texas Instruments, Inc.
 * Santosh Shilimkar <santosh.shilimkar@ti.com>
 * Rajendra Nayak <rnayak@ti.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/sched.h>
#include <linux/cpuidle.h>
#include <linux/cpu_pm.h>
#include <linux/export.h>
#include <linux/clockchips.h>

#include <asm/proc-fns.h>

#include "common.h"
#include "pm.h"
#include "prm.h"
#include "clockdomain.h"

/* Machine specific information */
struct omap4_idle_statedata {
	u32 cpu_state;
	u32 mpu_logic_state;
	u32 mpu_state;
};

static struct omap4_idle_statedata omap4_idle_data[] = {
	{
		.cpu_state = PWRDM_POWER_ON,
		.mpu_state = PWRDM_POWER_ON,
		.mpu_logic_state = PWRDM_POWER_RET,
	},
	{
		.cpu_state = PWRDM_POWER_OFF,
		.mpu_state = PWRDM_POWER_RET,
		.mpu_logic_state = PWRDM_POWER_RET,
	},
	{
		.cpu_state = PWRDM_POWER_OFF,
		.mpu_state = PWRDM_POWER_RET,
		.mpu_logic_state = PWRDM_POWER_OFF,
	},
};

static struct powerdomain *mpu_pd, *cpu_pd[NR_CPUS];
static struct clockdomain *cpu_clkdm[NR_CPUS];

static atomic_t abort_barrier;
static bool cpu_done[NR_CPUS];

/**
 * omap4_enter_idle_coupled_[simple/coupled] - OMAP4 cpuidle entry functions
 * @dev: cpuidle device
 * @drv: cpuidle driver
 * @index: the index of state to be entered
 *
 * Called from the CPUidle framework to program the device to the
 * specified low power state selected by the governor.
 * Returns the amount of time spent in the low power state.
 */
static int omap4_enter_idle_simple(struct cpuidle_device *dev,
			struct cpuidle_driver *drv,
			int index)
{
	local_fiq_disable();
	omap_do_wfi();
	local_fiq_enable();

	return index;
}

static int omap4_enter_idle_coupled(struct cpuidle_device *dev,
			struct cpuidle_driver *drv,
			int index)
{
	struct omap4_idle_statedata *cx = &omap4_idle_data[index];
	int cpu_id = smp_processor_id();

	local_fiq_disable();

	/*
	 * CPU0 has to wait and stay ON until CPU1 is OFF state.
	 * This is necessary to honour hardware recommondation
	 * of triggeing all the possible low power modes once CPU1 is
	 * out of coherency and in OFF mode.
	 */
	if (dev->cpu == 0 && cpumask_test_cpu(1, cpu_online_mask)) {
		while (pwrdm_read_pwrst(cpu_pd[1]) != PWRDM_POWER_OFF) {
			cpu_relax();

			/*
			 * CPU1 could have already entered & exited idle
			 * without hitting off because of a wakeup
			 * or a failed attempt to hit off mode.  Check for
			 * that here, otherwise we could spin forever
			 * waiting for CPU1 off.
			 */
			if (cpu_done[1])
			    goto fail;

		}
	}

	clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &cpu_id);

	/*
	 * Call idle CPU PM enter notifier chain so that
	 * VFP and per CPU interrupt context is saved.
	 */
	cpu_pm_enter();

	if (dev->cpu == 0) {
		pwrdm_set_logic_retst(mpu_pd, cx->mpu_logic_state);
		omap_set_pwrdm_state(mpu_pd, cx->mpu_state);

		/*
		 * Call idle CPU cluster PM enter notifier chain
		 * to save GIC and wakeupgen context.
		 */
		if ((cx->mpu_state == PWRDM_POWER_RET) &&
			(cx->mpu_logic_state == PWRDM_POWER_OFF))
				cpu_cluster_pm_enter();
	}

	omap4_enter_lowpower(dev->cpu, cx->cpu_state);
	cpu_done[dev->cpu] = true;

	/* Wakeup CPU1 only if it is not offlined */
	if (dev->cpu == 0 && cpumask_test_cpu(1, cpu_online_mask)) {
		clkdm_wakeup(cpu_clkdm[1]);
		clkdm_allow_idle(cpu_clkdm[1]);
	}

	/*
	 * Call idle CPU PM exit notifier chain to restore
	 * VFP and per CPU IRQ context.
	 */
	cpu_pm_exit();

	/*
	 * Call idle CPU cluster PM exit notifier chain
	 * to restore GIC and wakeupgen context.
	 */
	if (omap4_mpuss_read_prev_context_state())
		cpu_cluster_pm_exit();

	clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &cpu_id);

fail:
	cpuidle_coupled_parallel_barrier(dev, &abort_barrier);
	cpu_done[dev->cpu] = false;

	local_fiq_enable();

	return index;
}

DEFINE_PER_CPU(struct cpuidle_device, omap4_idle_dev);

struct cpuidle_driver omap4_idle_driver = {
	.name				= "omap4_idle",
	.owner				= THIS_MODULE,
	.en_core_tk_irqen		= 1,
	.states = {
		{
			/* C1 - CPU0 ON + CPU1 ON + MPU ON */
			.exit_latency = 2 + 2,
			.target_residency = 5,
			.flags = CPUIDLE_FLAG_TIME_VALID,
			.enter = omap4_enter_idle_simple,
			.name = "C1",
			.desc = "MPUSS ON"
		},
		{
                        /* C2 - CPU0 OFF + CPU1 OFF + MPU CSWR */
			.exit_latency = 328 + 440,
			.target_residency = 960,
			.flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_COUPLED,
			.enter = omap4_enter_idle_coupled,
			.name = "C2",
			.desc = "MPUSS CSWR",
		},
		{
			/* C3 - CPU0 OFF + CPU1 OFF + MPU OSWR */
			.exit_latency = 460 + 518,
			.target_residency = 1100,
			.flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_COUPLED,
			.enter = omap4_enter_idle_coupled,
			.name = "C3",
			.desc = "MPUSS OSWR",
		},
	},
	.state_count = ARRAY_SIZE(omap4_idle_data),
	.safe_state_index = 0,
};

/*
 * For each cpu, setup the broadcast timer because local timers
 * stops for the states above C1.
 */
static void omap_setup_broadcast_timer(void *arg)
{
	int cpu = smp_processor_id();
	clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ON, &cpu);
}

/**
 * omap4_idle_init - Init routine for OMAP4 idle
 *
 * Registers the OMAP4 specific cpuidle driver to the cpuidle
 * framework with the valid set of states.
 */
int __init omap4_idle_init(void)
{
	struct cpuidle_device *dev;
	unsigned int cpu_id = 0;

	mpu_pd = pwrdm_lookup("mpu_pwrdm");
	cpu_pd[0] = pwrdm_lookup("cpu0_pwrdm");
	cpu_pd[1] = pwrdm_lookup("cpu1_pwrdm");
	if ((!mpu_pd) || (!cpu_pd[0]) || (!cpu_pd[1]))
		return -ENODEV;

	cpu_clkdm[0] = clkdm_lookup("mpu0_clkdm");
	cpu_clkdm[1] = clkdm_lookup("mpu1_clkdm");
	if (!cpu_clkdm[0] || !cpu_clkdm[1])
		return -ENODEV;

	/* Configure the broadcast timer on each cpu */
	on_each_cpu(omap_setup_broadcast_timer, NULL, 1);

	for_each_cpu(cpu_id, cpu_online_mask) {
		dev = &per_cpu(omap4_idle_dev, cpu_id);
		dev->cpu = cpu_id;
#ifdef CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED
		dev->coupled_cpus = *cpu_online_mask;
#endif
		cpuidle_register_driver(&omap4_idle_driver);

		if (cpuidle_register_device(dev)) {
			pr_err("%s: CPUidle register failed\n", __func__);
			return -EIO;
		}
	}

	return 0;
}
Commit	Line	Data
98272660 SS	1	/*
	2	* OMAP4 CPU idle Routines
	3	*
	4	* Copyright (C) 2011 Texas Instruments, Inc.
	5	* Santosh Shilimkar <santosh.shilimkar@ti.com>
	6	* Rajendra Nayak <rnayak@ti.com>
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License version 2 as
	10	* published by the Free Software Foundation.
	11	*/
	12
	13	#include <linux/sched.h>
	14	#include <linux/cpuidle.h>
	15	#include <linux/cpu_pm.h>
	16	#include <linux/export.h>
98be0dde	17	#include <linux/clockchips.h>
98272660 SS	18
	19	#include <asm/proc-fns.h>
	20
	21	#include "common.h"
	22	#include "pm.h"
	23	#include "prm.h"
dd3ad97c	24	#include "clockdomain.h"
98272660	25
7aeb658d	26	/* Machine specific information */
98272660 SS	27	struct omap4_idle_statedata {
	28	u32 cpu_state;
	29	u32 mpu_logic_state;
	30	u32 mpu_state;
98272660 SS	31	};
98272660 SS	32
d0d133d9 DL	33	static struct omap4_idle_statedata omap4_idle_data[] = {
	34	{
	35	.cpu_state = PWRDM_POWER_ON,
	36	.mpu_state = PWRDM_POWER_ON,
	37	.mpu_logic_state = PWRDM_POWER_RET,
	38	},
	39	{
	40	.cpu_state = PWRDM_POWER_OFF,
	41	.mpu_state = PWRDM_POWER_RET,
	42	.mpu_logic_state = PWRDM_POWER_RET,
	43	},
	44	{
	45	.cpu_state = PWRDM_POWER_OFF,
	46	.mpu_state = PWRDM_POWER_RET,
	47	.mpu_logic_state = PWRDM_POWER_OFF,
	48	},
	49	};
98272660	50
dd3ad97c SS	51	static struct powerdomain mpu_pd, cpu_pd[NR_CPUS];
dd3ad97c SS	52	static struct clockdomain *cpu_clkdm[NR_CPUS];
98272660	53
5b4d5bcc KH	54	static atomic_t abort_barrier;
5b4d5bcc KH	55	static bool cpu_done[NR_CPUS];
98272660 SS	56
98272660 SS	57	/**
dd3ad97c	58	* omap4_enter_idle_coupled_[simple/coupled] - OMAP4 cpuidle entry functions
98272660 SS	59	* @dev: cpuidle device
	60	* @drv: cpuidle driver
	61	* @index: the index of state to be entered
	62	*
	63	* Called from the CPUidle framework to program the device to the
	64	* specified low power state selected by the governor.
	65	* Returns the amount of time spent in the low power state.
	66	*/
dd3ad97c SS	67	static int omap4_enter_idle_simple(struct cpuidle_device *dev,
	68	struct cpuidle_driver *drv,
	69	int index)
	70	{
	71	local_fiq_disable();
	72	omap_do_wfi();
	73	local_fiq_enable();
	74
	75	return index;
	76	}
	77
	78	static int omap4_enter_idle_coupled(struct cpuidle_device *dev,
98272660 SS	79	struct cpuidle_driver *drv,
	80	int index)
	81	{
7aeb658d	82	struct omap4_idle_statedata *cx = &omap4_idle_data[index];
98be0dde	83	int cpu_id = smp_processor_id();
98272660	84
98272660 SS	85	local_fiq_disable();
	86
	87	/*
dd3ad97c	88	* CPU0 has to wait and stay ON until CPU1 is OFF state.
98272660 SS	89	* This is necessary to honour hardware recommondation
	90	* of triggeing all the possible low power modes once CPU1 is
	91	* out of coherency and in OFF mode.
98272660	92	*/
dd3ad97c	93	if (dev->cpu == 0 && cpumask_test_cpu(1, cpu_online_mask)) {
5b4d5bcc	94	while (pwrdm_read_pwrst(cpu_pd[1]) != PWRDM_POWER_OFF) {
dd3ad97c	95	cpu_relax();
5b4d5bcc KH	96
	97	/*
	98	* CPU1 could have already entered & exited idle
	99	* without hitting off because of a wakeup
	100	* or a failed attempt to hit off mode. Check for
	101	* that here, otherwise we could spin forever
	102	* waiting for CPU1 off.
	103	*/
	104	if (cpu_done[1])
	105	goto fail;
	106
	107	}
98272660 SS	108	}
98272660 SS	109
dd3ad97c	110	clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &cpu_id);
98be0dde	111
98272660 SS	112	/*
	113	* Call idle CPU PM enter notifier chain so that
	114	* VFP and per CPU interrupt context is saved.
	115	*/
dd3ad97c SS	116	cpu_pm_enter();
	117
	118	if (dev->cpu == 0) {
	119	pwrdm_set_logic_retst(mpu_pd, cx->mpu_logic_state);
	120	omap_set_pwrdm_state(mpu_pd, cx->mpu_state);
	121
	122	/*
	123	* Call idle CPU cluster PM enter notifier chain
	124	* to save GIC and wakeupgen context.
	125	*/
	126	if ((cx->mpu_state == PWRDM_POWER_RET) &&
	127	(cx->mpu_logic_state == PWRDM_POWER_OFF))
	128	cpu_cluster_pm_enter();
	129	}
98272660 SS	130
98272660 SS	131	omap4_enter_lowpower(dev->cpu, cx->cpu_state);
5b4d5bcc	132	cpu_done[dev->cpu] = true;
98272660	133
dd3ad97c SS	134	/* Wakeup CPU1 only if it is not offlined */
	135	if (dev->cpu == 0 && cpumask_test_cpu(1, cpu_online_mask)) {
	136	clkdm_wakeup(cpu_clkdm[1]);
	137	clkdm_allow_idle(cpu_clkdm[1]);
	138	}
98272660 SS	139
	140	/*
	141	* Call idle CPU PM exit notifier chain to restore
dd3ad97c	142	* VFP and per CPU IRQ context.
98272660	143	*/
dd3ad97c	144	cpu_pm_exit();
98272660 SS	145
	146	/*
	147	* Call idle CPU cluster PM exit notifier chain
	148	* to restore GIC and wakeupgen context.
	149	*/
	150	if (omap4_mpuss_read_prev_context_state())
	151	cpu_cluster_pm_exit();
	152
dd3ad97c	153	clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &cpu_id);
98be0dde	154
5b4d5bcc KH	155	fail:
	156	cpuidle_coupled_parallel_barrier(dev, &abort_barrier);
	157	cpu_done[dev->cpu] = false;
98be0dde	158
98272660 SS	159	local_fiq_enable();
98272660 SS	160
98272660 SS	161	return index;
	162	}
	163
	164	DEFINE_PER_CPU(struct cpuidle_device, omap4_idle_dev);
	165
	166	struct cpuidle_driver omap4_idle_driver = {
d13e9261 RL	167	.name = "omap4_idle",
	168	.owner = THIS_MODULE,
	169	.en_core_tk_irqen = 1,
78e9016f DL	170	.states = {
	171	{
	172	/* C1 - CPU0 ON + CPU1 ON + MPU ON */
	173	.exit_latency = 2 + 2,
	174	.target_residency = 5,
	175	.flags = CPUIDLE_FLAG_TIME_VALID,
dd3ad97c	176	.enter = omap4_enter_idle_simple,
78e9016f DL	177	.name = "C1",
	178	.desc = "MPUSS ON"
	179	},
	180	{
	181	/* C2 - CPU0 OFF + CPU1 OFF + MPU CSWR */
	182	.exit_latency = 328 + 440,
	183	.target_residency = 960,
dd3ad97c SS	184	.flags = CPUIDLE_FLAG_TIME_VALID \| CPUIDLE_FLAG_COUPLED,
dd3ad97c SS	185	.enter = omap4_enter_idle_coupled,
78e9016f DL	186	.name = "C2",
	187	.desc = "MPUSS CSWR",
	188	},
	189	{
	190	/* C3 - CPU0 OFF + CPU1 OFF + MPU OSWR */
	191	.exit_latency = 460 + 518,
	192	.target_residency = 1100,
dd3ad97c SS	193	.flags = CPUIDLE_FLAG_TIME_VALID \| CPUIDLE_FLAG_COUPLED,
dd3ad97c SS	194	.enter = omap4_enter_idle_coupled,
78e9016f DL	195	.name = "C3",
	196	.desc = "MPUSS OSWR",
	197	},
	198	},
d0d133d9	199	.state_count = ARRAY_SIZE(omap4_idle_data),
78e9016f	200	.safe_state_index = 0,
98272660 SS	201	};
98272660 SS	202
b93d70ae SS	203	/*
	204	* For each cpu, setup the broadcast timer because local timers
	205	* stops for the states above C1.
	206	*/
	207	static void omap_setup_broadcast_timer(void *arg)
	208	{
	209	int cpu = smp_processor_id();
	210	clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ON, &cpu);
	211	}
	212
98272660 SS	213	/**
	214	* omap4_idle_init - Init routine for OMAP4 idle
	215	*
	216	* Registers the OMAP4 specific cpuidle driver to the cpuidle
	217	* framework with the valid set of states.
	218	*/
	219	int __init omap4_idle_init(void)
	220	{
98272660	221	struct cpuidle_device *dev;
98272660 SS	222	unsigned int cpu_id = 0;
	223
	224	mpu_pd = pwrdm_lookup("mpu_pwrdm");
dd3ad97c SS	225	cpu_pd[0] = pwrdm_lookup("cpu0_pwrdm");
	226	cpu_pd[1] = pwrdm_lookup("cpu1_pwrdm");
	227	if ((!mpu_pd) \|\| (!cpu_pd[0]) \|\| (!cpu_pd[1]))
98272660 SS	228	return -ENODEV;
98272660 SS	229
dd3ad97c SS	230	cpu_clkdm[0] = clkdm_lookup("mpu0_clkdm");
	231	cpu_clkdm[1] = clkdm_lookup("mpu1_clkdm");
	232	if (!cpu_clkdm[0] \|\| !cpu_clkdm[1])
98272660 SS	233	return -ENODEV;
98272660 SS	234
b93d70ae SS	235	/* Configure the broadcast timer on each cpu */
	236	on_each_cpu(omap_setup_broadcast_timer, NULL, 1);
	237
dd3ad97c SS	238	for_each_cpu(cpu_id, cpu_online_mask) {
	239	dev = &per_cpu(omap4_idle_dev, cpu_id);
	240	dev->cpu = cpu_id;
c7a9b09b	241	#ifdef CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED
dd3ad97c	242	dev->coupled_cpus = *cpu_online_mask;
c7a9b09b	243	#endif
dd3ad97c	244	cpuidle_register_driver(&omap4_idle_driver);
98272660	245
dd3ad97c SS	246	if (cpuidle_register_device(dev)) {
	247	pr_err("%s: CPUidle register failed\n", __func__);
	248	return -EIO;
	249	}
78e9016f	250	}
98272660 SS	251
	252	return 0;
	253	}