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98272660 SS |
1 | /* |
2 | * OMAP4 CPU idle Routines | |
3 | * | |
4 | * Copyright (C) 2011 Texas Instruments, Inc. | |
5 | * Santosh Shilimkar <santosh.shilimkar@ti.com> | |
6 | * Rajendra Nayak <rnayak@ti.com> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | */ | |
12 | ||
13 | #include <linux/sched.h> | |
14 | #include <linux/cpuidle.h> | |
15 | #include <linux/cpu_pm.h> | |
16 | #include <linux/export.h> | |
98be0dde | 17 | #include <linux/clockchips.h> |
98272660 SS |
18 | |
19 | #include <asm/proc-fns.h> | |
20 | ||
21 | #include "common.h" | |
22 | #include "pm.h" | |
23 | #include "prm.h" | |
24 | ||
25 | #ifdef CONFIG_CPU_IDLE | |
26 | ||
27 | /* Machine specific information to be recorded in the C-state driver_data */ | |
28 | struct omap4_idle_statedata { | |
29 | u32 cpu_state; | |
30 | u32 mpu_logic_state; | |
31 | u32 mpu_state; | |
98272660 SS |
32 | }; |
33 | ||
4e0a64fa | 34 | #define OMAP4_NUM_STATES 3 |
98272660 SS |
35 | |
36 | struct omap4_idle_statedata omap4_idle_data[OMAP4_NUM_STATES]; | |
37 | static struct powerdomain *mpu_pd, *cpu0_pd, *cpu1_pd; | |
38 | ||
39 | /** | |
40 | * omap4_enter_idle - Programs OMAP4 to enter the specified state | |
41 | * @dev: cpuidle device | |
42 | * @drv: cpuidle driver | |
43 | * @index: the index of state to be entered | |
44 | * | |
45 | * Called from the CPUidle framework to program the device to the | |
46 | * specified low power state selected by the governor. | |
47 | * Returns the amount of time spent in the low power state. | |
48 | */ | |
49 | static int omap4_enter_idle(struct cpuidle_device *dev, | |
50 | struct cpuidle_driver *drv, | |
51 | int index) | |
52 | { | |
53 | struct omap4_idle_statedata *cx = | |
54 | cpuidle_get_statedata(&dev->states_usage[index]); | |
98272660 | 55 | u32 cpu1_state; |
98be0dde | 56 | int cpu_id = smp_processor_id(); |
98272660 | 57 | |
98272660 SS |
58 | local_fiq_disable(); |
59 | ||
60 | /* | |
61 | * CPU0 has to stay ON (i.e in C1) until CPU1 is OFF state. | |
62 | * This is necessary to honour hardware recommondation | |
63 | * of triggeing all the possible low power modes once CPU1 is | |
64 | * out of coherency and in OFF mode. | |
65 | * Update dev->last_state so that governor stats reflects right | |
66 | * data. | |
67 | */ | |
68 | cpu1_state = pwrdm_read_pwrst(cpu1_pd); | |
69 | if (cpu1_state != PWRDM_POWER_OFF) { | |
03e4fd6e SS |
70 | index = drv->safe_state_index; |
71 | cx = cpuidle_get_statedata(&dev->states_usage[index]); | |
98272660 SS |
72 | } |
73 | ||
98be0dde SS |
74 | if (index > 0) |
75 | clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &cpu_id); | |
76 | ||
98272660 SS |
77 | /* |
78 | * Call idle CPU PM enter notifier chain so that | |
79 | * VFP and per CPU interrupt context is saved. | |
80 | */ | |
81 | if (cx->cpu_state == PWRDM_POWER_OFF) | |
82 | cpu_pm_enter(); | |
83 | ||
84 | pwrdm_set_logic_retst(mpu_pd, cx->mpu_logic_state); | |
85 | omap_set_pwrdm_state(mpu_pd, cx->mpu_state); | |
86 | ||
87 | /* | |
88 | * Call idle CPU cluster PM enter notifier chain | |
89 | * to save GIC and wakeupgen context. | |
90 | */ | |
91 | if ((cx->mpu_state == PWRDM_POWER_RET) && | |
92 | (cx->mpu_logic_state == PWRDM_POWER_OFF)) | |
93 | cpu_cluster_pm_enter(); | |
94 | ||
95 | omap4_enter_lowpower(dev->cpu, cx->cpu_state); | |
96 | ||
97 | /* | |
98 | * Call idle CPU PM exit notifier chain to restore | |
99 | * VFP and per CPU IRQ context. Only CPU0 state is | |
100 | * considered since CPU1 is managed by CPU hotplug. | |
101 | */ | |
102 | if (pwrdm_read_prev_pwrst(cpu0_pd) == PWRDM_POWER_OFF) | |
103 | cpu_pm_exit(); | |
104 | ||
105 | /* | |
106 | * Call idle CPU cluster PM exit notifier chain | |
107 | * to restore GIC and wakeupgen context. | |
108 | */ | |
109 | if (omap4_mpuss_read_prev_context_state()) | |
110 | cpu_cluster_pm_exit(); | |
111 | ||
98be0dde SS |
112 | if (index > 0) |
113 | clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &cpu_id); | |
114 | ||
98272660 SS |
115 | local_fiq_enable(); |
116 | ||
98272660 SS |
117 | return index; |
118 | } | |
119 | ||
120 | DEFINE_PER_CPU(struct cpuidle_device, omap4_idle_dev); | |
121 | ||
122 | struct cpuidle_driver omap4_idle_driver = { | |
d13e9261 RL |
123 | .name = "omap4_idle", |
124 | .owner = THIS_MODULE, | |
125 | .en_core_tk_irqen = 1, | |
78e9016f DL |
126 | .states = { |
127 | { | |
128 | /* C1 - CPU0 ON + CPU1 ON + MPU ON */ | |
129 | .exit_latency = 2 + 2, | |
130 | .target_residency = 5, | |
131 | .flags = CPUIDLE_FLAG_TIME_VALID, | |
132 | .enter = omap4_enter_idle, | |
133 | .name = "C1", | |
134 | .desc = "MPUSS ON" | |
135 | }, | |
136 | { | |
137 | /* C2 - CPU0 OFF + CPU1 OFF + MPU CSWR */ | |
138 | .exit_latency = 328 + 440, | |
139 | .target_residency = 960, | |
140 | .flags = CPUIDLE_FLAG_TIME_VALID, | |
141 | .enter = omap4_enter_idle, | |
142 | .name = "C2", | |
143 | .desc = "MPUSS CSWR", | |
144 | }, | |
145 | { | |
146 | /* C3 - CPU0 OFF + CPU1 OFF + MPU OSWR */ | |
147 | .exit_latency = 460 + 518, | |
148 | .target_residency = 1100, | |
149 | .flags = CPUIDLE_FLAG_TIME_VALID, | |
150 | .enter = omap4_enter_idle, | |
151 | .name = "C3", | |
152 | .desc = "MPUSS OSWR", | |
153 | }, | |
154 | }, | |
155 | .state_count = OMAP4_NUM_STATES, | |
156 | .safe_state_index = 0, | |
98272660 SS |
157 | }; |
158 | ||
98272660 SS |
159 | static inline struct omap4_idle_statedata *_fill_cstate_usage( |
160 | struct cpuidle_device *dev, | |
161 | int idx) | |
162 | { | |
163 | struct omap4_idle_statedata *cx = &omap4_idle_data[idx]; | |
164 | struct cpuidle_state_usage *state_usage = &dev->states_usage[idx]; | |
165 | ||
98272660 SS |
166 | cpuidle_set_statedata(state_usage, cx); |
167 | ||
168 | return cx; | |
169 | } | |
170 | ||
171 | ||
172 | ||
173 | /** | |
174 | * omap4_idle_init - Init routine for OMAP4 idle | |
175 | * | |
176 | * Registers the OMAP4 specific cpuidle driver to the cpuidle | |
177 | * framework with the valid set of states. | |
178 | */ | |
179 | int __init omap4_idle_init(void) | |
180 | { | |
181 | struct omap4_idle_statedata *cx; | |
182 | struct cpuidle_device *dev; | |
98272660 SS |
183 | unsigned int cpu_id = 0; |
184 | ||
185 | mpu_pd = pwrdm_lookup("mpu_pwrdm"); | |
186 | cpu0_pd = pwrdm_lookup("cpu0_pwrdm"); | |
187 | cpu1_pd = pwrdm_lookup("cpu1_pwrdm"); | |
188 | if ((!mpu_pd) || (!cpu0_pd) || (!cpu1_pd)) | |
189 | return -ENODEV; | |
190 | ||
98272660 SS |
191 | dev = &per_cpu(omap4_idle_dev, cpu_id); |
192 | dev->cpu = cpu_id; | |
193 | ||
98272660 | 194 | cx = _fill_cstate_usage(dev, 0); |
98272660 SS |
195 | cx->cpu_state = PWRDM_POWER_ON; |
196 | cx->mpu_state = PWRDM_POWER_ON; | |
197 | cx->mpu_logic_state = PWRDM_POWER_RET; | |
198 | ||
98272660 SS |
199 | cx = _fill_cstate_usage(dev, 1); |
200 | cx->cpu_state = PWRDM_POWER_OFF; | |
201 | cx->mpu_state = PWRDM_POWER_RET; | |
202 | cx->mpu_logic_state = PWRDM_POWER_RET; | |
203 | ||
98272660 SS |
204 | cx = _fill_cstate_usage(dev, 2); |
205 | cx->cpu_state = PWRDM_POWER_OFF; | |
206 | cx->mpu_state = PWRDM_POWER_RET; | |
207 | cx->mpu_logic_state = PWRDM_POWER_OFF; | |
208 | ||
98272660 SS |
209 | cpuidle_register_driver(&omap4_idle_driver); |
210 | ||
98272660 SS |
211 | if (cpuidle_register_device(dev)) { |
212 | pr_err("%s: CPUidle register device failed\n", __func__); | |
78e9016f DL |
213 | return -EIO; |
214 | } | |
98272660 SS |
215 | |
216 | return 0; | |
217 | } | |
218 | #else | |
219 | int __init omap4_idle_init(void) | |
220 | { | |
221 | return 0; | |
222 | } | |
223 | #endif /* CONFIG_CPU_IDLE */ |