[deliverable/linux.git] / arch / arm / mach-omap2 / cpuidle44xx.c

/*
 * OMAP4 CPU idle Routines
 *
 * Copyright (C) 2011 Texas Instruments, Inc.
 * Santosh Shilimkar <santosh.shilimkar@ti.com>
 * Rajendra Nayak <rnayak@ti.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/sched.h>
#include <linux/cpuidle.h>
#include <linux/cpu_pm.h>
#include <linux/export.h>
#include <linux/clockchips.h>

#include <asm/proc-fns.h>

#include "common.h"
#include "pm.h"
#include "prm.h"

#ifdef CONFIG_CPU_IDLE

/* Machine specific information to be recorded in the C-state driver_data */
struct omap4_idle_statedata {
	u32 cpu_state;
	u32 mpu_logic_state;
	u32 mpu_state;
};

static struct cpuidle_params cpuidle_params_table[] = {
	/* C1 - CPU0 ON + CPU1 ON + MPU ON */
	{.exit_latency = 2 + 2 , .target_residency = 5 },
	/* C2- CPU0 OFF + CPU1 OFF + MPU CSWR */
	{.exit_latency = 328 + 440 , .target_residency = 960 },
	/* C3 - CPU0 OFF + CPU1 OFF + MPU OSWR */
	{.exit_latency = 460 + 518 , .target_residency = 1100 },
};

#define OMAP4_NUM_STATES ARRAY_SIZE(cpuidle_params_table)

struct omap4_idle_statedata omap4_idle_data[OMAP4_NUM_STATES];
static struct powerdomain *mpu_pd, *cpu0_pd, *cpu1_pd;

/**
 * omap4_enter_idle - Programs OMAP4 to enter the specified state
 * @dev: cpuidle device
 * @drv: cpuidle driver
 * @index: the index of state to be entered
 *
 * Called from the CPUidle framework to program the device to the
 * specified low power state selected by the governor.
 * Returns the amount of time spent in the low power state.
 */
static int omap4_enter_idle(struct cpuidle_device *dev,
			struct cpuidle_driver *drv,
			int index)
{
	struct omap4_idle_statedata *cx =
			cpuidle_get_statedata(&dev->states_usage[index]);
	u32 cpu1_state;
	int cpu_id = smp_processor_id();

	local_fiq_disable();

	/*
	 * CPU0 has to stay ON (i.e in C1) until CPU1 is OFF state.
	 * This is necessary to honour hardware recommondation
	 * of triggeing all the possible low power modes once CPU1 is
	 * out of coherency and in OFF mode.
	 * Update dev->last_state so that governor stats reflects right
	 * data.
	 */
	cpu1_state = pwrdm_read_pwrst(cpu1_pd);
	if (cpu1_state != PWRDM_POWER_OFF) {
		index = drv->safe_state_index;
		cx = cpuidle_get_statedata(&dev->states_usage[index]);
	}

	if (index > 0)
		clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &cpu_id);

	/*
	 * Call idle CPU PM enter notifier chain so that
	 * VFP and per CPU interrupt context is saved.
	 */
	if (cx->cpu_state == PWRDM_POWER_OFF)
		cpu_pm_enter();

	pwrdm_set_logic_retst(mpu_pd, cx->mpu_logic_state);
	omap_set_pwrdm_state(mpu_pd, cx->mpu_state);

	/*
	 * Call idle CPU cluster PM enter notifier chain
	 * to save GIC and wakeupgen context.
	 */
	if ((cx->mpu_state == PWRDM_POWER_RET) &&
		(cx->mpu_logic_state == PWRDM_POWER_OFF))
			cpu_cluster_pm_enter();

	omap4_enter_lowpower(dev->cpu, cx->cpu_state);

	/*
	 * Call idle CPU PM exit notifier chain to restore
	 * VFP and per CPU IRQ context. Only CPU0 state is
	 * considered since CPU1 is managed by CPU hotplug.
	 */
	if (pwrdm_read_prev_pwrst(cpu0_pd) == PWRDM_POWER_OFF)
		cpu_pm_exit();

	/*
	 * Call idle CPU cluster PM exit notifier chain
	 * to restore GIC and wakeupgen context.
	 */
	if (omap4_mpuss_read_prev_context_state())
		cpu_cluster_pm_exit();

	if (index > 0)
		clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &cpu_id);

	local_fiq_enable();

	return index;
}

DEFINE_PER_CPU(struct cpuidle_device, omap4_idle_dev);

struct cpuidle_driver omap4_idle_driver = {
	.name				= "omap4_idle",
	.owner				= THIS_MODULE,
	.en_core_tk_irqen		= 1,
};

static inline void _fill_cstate(struct cpuidle_driver *drv,
					int idx, const char *descr)
{
	struct cpuidle_state *state = &drv->states[idx];

	state->exit_latency	= cpuidle_params_table[idx].exit_latency;
	state->target_residency	= cpuidle_params_table[idx].target_residency;
	state->flags		= CPUIDLE_FLAG_TIME_VALID;
	state->enter		= omap4_enter_idle;
	sprintf(state->name, "C%d", idx + 1);
	strncpy(state->desc, descr, CPUIDLE_DESC_LEN);
}

static inline struct omap4_idle_statedata *_fill_cstate_usage(
					struct cpuidle_device *dev,
					int idx)
{
	struct omap4_idle_statedata *cx = &omap4_idle_data[idx];
	struct cpuidle_state_usage *state_usage = &dev->states_usage[idx];

	cpuidle_set_statedata(state_usage, cx);

	return cx;
}


/**
 * omap4_idle_init - Init routine for OMAP4 idle
 *
 * Registers the OMAP4 specific cpuidle driver to the cpuidle
 * framework with the valid set of states.
 */
int __init omap4_idle_init(void)
{
	struct omap4_idle_statedata *cx;
	struct cpuidle_device *dev;
	struct cpuidle_driver *drv = &omap4_idle_driver;
	unsigned int cpu_id = 0;

	mpu_pd = pwrdm_lookup("mpu_pwrdm");
	cpu0_pd = pwrdm_lookup("cpu0_pwrdm");
	cpu1_pd = pwrdm_lookup("cpu1_pwrdm");
	if ((!mpu_pd) || (!cpu0_pd) || (!cpu1_pd))
		return -ENODEV;


	drv->safe_state_index = -1;
	dev = &per_cpu(omap4_idle_dev, cpu_id);
	dev->cpu = cpu_id;

	/* C1 - CPU0 ON + CPU1 ON + MPU ON */
	_fill_cstate(drv, 0, "MPUSS ON");
	drv->safe_state_index = 0;
	cx = _fill_cstate_usage(dev, 0);
	cx->cpu_state = PWRDM_POWER_ON;
	cx->mpu_state = PWRDM_POWER_ON;
	cx->mpu_logic_state = PWRDM_POWER_RET;

	/* C2 - CPU0 OFF + CPU1 OFF + MPU CSWR */
	_fill_cstate(drv, 1, "MPUSS CSWR");
	cx = _fill_cstate_usage(dev, 1);
	cx->cpu_state = PWRDM_POWER_OFF;
	cx->mpu_state = PWRDM_POWER_RET;
	cx->mpu_logic_state = PWRDM_POWER_RET;

	/* C3 - CPU0 OFF + CPU1 OFF + MPU OSWR */
	_fill_cstate(drv, 2, "MPUSS OSWR");
	cx = _fill_cstate_usage(dev, 2);
	cx->cpu_state = PWRDM_POWER_OFF;
	cx->mpu_state = PWRDM_POWER_RET;
	cx->mpu_logic_state = PWRDM_POWER_OFF;

	drv->state_count = OMAP4_NUM_STATES;
	cpuidle_register_driver(&omap4_idle_driver);

	dev->state_count = OMAP4_NUM_STATES;
	if (cpuidle_register_device(dev)) {
		pr_err("%s: CPUidle register device failed\n", __func__);
			return -EIO;
		}

	return 0;
}
#else
int __init omap4_idle_init(void)
{
	return 0;
}
#endif /* CONFIG_CPU_IDLE */
Commit	Line	Data
98272660 SS	1	/*
	2	* OMAP4 CPU idle Routines
	3	*
	4	* Copyright (C) 2011 Texas Instruments, Inc.
	5	* Santosh Shilimkar <santosh.shilimkar@ti.com>
	6	* Rajendra Nayak <rnayak@ti.com>
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License version 2 as
	10	* published by the Free Software Foundation.
	11	*/
	12
	13	#include <linux/sched.h>
	14	#include <linux/cpuidle.h>
	15	#include <linux/cpu_pm.h>
	16	#include <linux/export.h>
98be0dde	17	#include <linux/clockchips.h>
98272660 SS	18
	19	#include <asm/proc-fns.h>
	20
	21	#include "common.h"
	22	#include "pm.h"
	23	#include "prm.h"
	24
	25	#ifdef CONFIG_CPU_IDLE
	26
	27	/* Machine specific information to be recorded in the C-state driver_data */
	28	struct omap4_idle_statedata {
	29	u32 cpu_state;
	30	u32 mpu_logic_state;
	31	u32 mpu_state;
98272660 SS	32	};
	33
	34	static struct cpuidle_params cpuidle_params_table[] = {
	35	/* C1 - CPU0 ON + CPU1 ON + MPU ON */
65d284d5	36	{.exit_latency = 2 + 2 , .target_residency = 5 },
98272660	37	/* C2- CPU0 OFF + CPU1 OFF + MPU CSWR */
65d284d5	38	{.exit_latency = 328 + 440 , .target_residency = 960 },
98272660	39	/* C3 - CPU0 OFF + CPU1 OFF + MPU OSWR */
65d284d5	40	{.exit_latency = 460 + 518 , .target_residency = 1100 },
98272660 SS	41	};
	42
	43	#define OMAP4_NUM_STATES ARRAY_SIZE(cpuidle_params_table)
	44
	45	struct omap4_idle_statedata omap4_idle_data[OMAP4_NUM_STATES];
	46	static struct powerdomain mpu_pd, cpu0_pd, *cpu1_pd;
	47
	48	/**
	49	* omap4_enter_idle - Programs OMAP4 to enter the specified state
	50	* @dev: cpuidle device
	51	* @drv: cpuidle driver
	52	* @index: the index of state to be entered
	53	*
	54	* Called from the CPUidle framework to program the device to the
	55	* specified low power state selected by the governor.
	56	* Returns the amount of time spent in the low power state.
	57	*/
	58	static int omap4_enter_idle(struct cpuidle_device *dev,
	59	struct cpuidle_driver *drv,
	60	int index)
	61	{
	62	struct omap4_idle_statedata *cx =
	63	cpuidle_get_statedata(&dev->states_usage[index]);
98272660	64	u32 cpu1_state;
98be0dde	65	int cpu_id = smp_processor_id();
98272660	66
98272660 SS	67	local_fiq_disable();
	68
	69	/*
	70	* CPU0 has to stay ON (i.e in C1) until CPU1 is OFF state.
	71	* This is necessary to honour hardware recommondation
	72	* of triggeing all the possible low power modes once CPU1 is
	73	* out of coherency and in OFF mode.
	74	* Update dev->last_state so that governor stats reflects right
	75	* data.
	76	*/
	77	cpu1_state = pwrdm_read_pwrst(cpu1_pd);
	78	if (cpu1_state != PWRDM_POWER_OFF) {
03e4fd6e SS	79	index = drv->safe_state_index;
03e4fd6e SS	80	cx = cpuidle_get_statedata(&dev->states_usage[index]);
98272660 SS	81	}
98272660 SS	82
98be0dde SS	83	if (index > 0)
	84	clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &cpu_id);
	85
98272660 SS	86	/*
	87	* Call idle CPU PM enter notifier chain so that
	88	* VFP and per CPU interrupt context is saved.
	89	*/
	90	if (cx->cpu_state == PWRDM_POWER_OFF)
	91	cpu_pm_enter();
	92
	93	pwrdm_set_logic_retst(mpu_pd, cx->mpu_logic_state);
	94	omap_set_pwrdm_state(mpu_pd, cx->mpu_state);
	95
	96	/*
	97	* Call idle CPU cluster PM enter notifier chain
	98	* to save GIC and wakeupgen context.
	99	*/
	100	if ((cx->mpu_state == PWRDM_POWER_RET) &&
	101	(cx->mpu_logic_state == PWRDM_POWER_OFF))
	102	cpu_cluster_pm_enter();
	103
	104	omap4_enter_lowpower(dev->cpu, cx->cpu_state);
	105
	106	/*
	107	* Call idle CPU PM exit notifier chain to restore
	108	* VFP and per CPU IRQ context. Only CPU0 state is
	109	* considered since CPU1 is managed by CPU hotplug.
	110	*/
	111	if (pwrdm_read_prev_pwrst(cpu0_pd) == PWRDM_POWER_OFF)
	112	cpu_pm_exit();
	113
	114	/*
	115	* Call idle CPU cluster PM exit notifier chain
	116	* to restore GIC and wakeupgen context.
	117	*/
	118	if (omap4_mpuss_read_prev_context_state())
	119	cpu_cluster_pm_exit();
	120
98be0dde SS	121	if (index > 0)
	122	clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &cpu_id);
	123
98272660 SS	124	local_fiq_enable();
98272660 SS	125
98272660 SS	126	return index;
	127	}
	128
	129	DEFINE_PER_CPU(struct cpuidle_device, omap4_idle_dev);
	130
	131	struct cpuidle_driver omap4_idle_driver = {
d13e9261 RL	132	.name = "omap4_idle",
	133	.owner = THIS_MODULE,
	134	.en_core_tk_irqen = 1,
98272660 SS	135	};
	136
	137	static inline void _fill_cstate(struct cpuidle_driver *drv,
	138	int idx, const char *descr)
	139	{
	140	struct cpuidle_state *state = &drv->states[idx];
	141
	142	state->exit_latency = cpuidle_params_table[idx].exit_latency;
	143	state->target_residency = cpuidle_params_table[idx].target_residency;
	144	state->flags = CPUIDLE_FLAG_TIME_VALID;
	145	state->enter = omap4_enter_idle;
	146	sprintf(state->name, "C%d", idx + 1);
	147	strncpy(state->desc, descr, CPUIDLE_DESC_LEN);
	148	}
	149
	150	static inline struct omap4_idle_statedata *_fill_cstate_usage(
	151	struct cpuidle_device *dev,
	152	int idx)
	153	{
	154	struct omap4_idle_statedata *cx = &omap4_idle_data[idx];
	155	struct cpuidle_state_usage *state_usage = &dev->states_usage[idx];
	156
98272660 SS	157	cpuidle_set_statedata(state_usage, cx);
	158
	159	return cx;
	160	}
	161
	162
	163
	164	/**
	165	* omap4_idle_init - Init routine for OMAP4 idle
	166	*
	167	* Registers the OMAP4 specific cpuidle driver to the cpuidle
	168	* framework with the valid set of states.
	169	*/
	170	int __init omap4_idle_init(void)
	171	{
	172	struct omap4_idle_statedata *cx;
	173	struct cpuidle_device *dev;
	174	struct cpuidle_driver *drv = &omap4_idle_driver;
	175	unsigned int cpu_id = 0;
	176
	177	mpu_pd = pwrdm_lookup("mpu_pwrdm");
	178	cpu0_pd = pwrdm_lookup("cpu0_pwrdm");
	179	cpu1_pd = pwrdm_lookup("cpu1_pwrdm");
	180	if ((!mpu_pd) \|\| (!cpu0_pd) \|\| (!cpu1_pd))
	181	return -ENODEV;
	182
	183
	184	drv->safe_state_index = -1;
	185	dev = &per_cpu(omap4_idle_dev, cpu_id);
	186	dev->cpu = cpu_id;
	187
	188	/* C1 - CPU0 ON + CPU1 ON + MPU ON */
	189	_fill_cstate(drv, 0, "MPUSS ON");
	190	drv->safe_state_index = 0;
	191	cx = _fill_cstate_usage(dev, 0);
98272660 SS	192	cx->cpu_state = PWRDM_POWER_ON;
	193	cx->mpu_state = PWRDM_POWER_ON;
	194	cx->mpu_logic_state = PWRDM_POWER_RET;
	195
	196	/* C2 - CPU0 OFF + CPU1 OFF + MPU CSWR */
	197	_fill_cstate(drv, 1, "MPUSS CSWR");
	198	cx = _fill_cstate_usage(dev, 1);
	199	cx->cpu_state = PWRDM_POWER_OFF;
	200	cx->mpu_state = PWRDM_POWER_RET;
	201	cx->mpu_logic_state = PWRDM_POWER_RET;
	202
	203	/* C3 - CPU0 OFF + CPU1 OFF + MPU OSWR */
	204	_fill_cstate(drv, 2, "MPUSS OSWR");
	205	cx = _fill_cstate_usage(dev, 2);
	206	cx->cpu_state = PWRDM_POWER_OFF;
	207	cx->mpu_state = PWRDM_POWER_RET;
	208	cx->mpu_logic_state = PWRDM_POWER_OFF;
	209
	210	drv->state_count = OMAP4_NUM_STATES;
	211	cpuidle_register_driver(&omap4_idle_driver);
	212
	213	dev->state_count = OMAP4_NUM_STATES;
	214	if (cpuidle_register_device(dev)) {
	215	pr_err("%s: CPUidle register device failed\n", __func__);
	216	return -EIO;
	217	}
	218
	219	return 0;
	220	}
	221	#else
	222	int __init omap4_idle_init(void)
	223	{
	224	return 0;
	225	}
	226	#endif /* CONFIG_CPU_IDLE */