[deliverable/linux.git] / arch / arm / mach-omap2 / cpuidle44xx.c

/*
 * OMAP4 CPU idle Routines
 *
 * Copyright (C) 2011 Texas Instruments, Inc.
 * Santosh Shilimkar <santosh.shilimkar@ti.com>
 * Rajendra Nayak <rnayak@ti.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/sched.h>
#include <linux/cpuidle.h>
#include <linux/cpu_pm.h>
#include <linux/export.h>
#include <linux/clockchips.h>

#include <asm/proc-fns.h>

#include "common.h"
#include "pm.h"
#include "prm.h"
#include "clockdomain.h"

/* Machine specific information */
struct omap4_idle_statedata {
	u32 cpu_state;
	u32 mpu_logic_state;
	u32 mpu_state;
};

static struct omap4_idle_statedata omap4_idle_data[] = {
	{
		.cpu_state = PWRDM_POWER_ON,
		.mpu_state = PWRDM_POWER_ON,
		.mpu_logic_state = PWRDM_POWER_RET,
	},
	{
		.cpu_state = PWRDM_POWER_OFF,
		.mpu_state = PWRDM_POWER_RET,
		.mpu_logic_state = PWRDM_POWER_RET,
	},
	{
		.cpu_state = PWRDM_POWER_OFF,
		.mpu_state = PWRDM_POWER_RET,
		.mpu_logic_state = PWRDM_POWER_OFF,
	},
};

static struct powerdomain *mpu_pd, *cpu_pd[NR_CPUS];
static struct clockdomain *cpu_clkdm[NR_CPUS];

static atomic_t abort_barrier;
static bool cpu_done[NR_CPUS];

/* Private functions */

/**
 * omap4_enter_idle_coupled_[simple/coupled] - OMAP4 cpuidle entry functions
 * @dev: cpuidle device
 * @drv: cpuidle driver
 * @index: the index of state to be entered
 *
 * Called from the CPUidle framework to program the device to the
 * specified low power state selected by the governor.
 * Returns the amount of time spent in the low power state.
 */
static int omap4_enter_idle_simple(struct cpuidle_device *dev,
			struct cpuidle_driver *drv,
			int index)
{
	omap_do_wfi();
	return index;
}

static int omap4_enter_idle_coupled(struct cpuidle_device *dev,
			struct cpuidle_driver *drv,
			int index)
{
	struct omap4_idle_statedata *cx = &omap4_idle_data[index];
	int cpu_id = smp_processor_id();

	/*
	 * CPU0 has to wait and stay ON until CPU1 is OFF state.
	 * This is necessary to honour hardware recommondation
	 * of triggeing all the possible low power modes once CPU1 is
	 * out of coherency and in OFF mode.
	 */
	if (dev->cpu == 0 && cpumask_test_cpu(1, cpu_online_mask)) {
		while (pwrdm_read_pwrst(cpu_pd[1]) != PWRDM_POWER_OFF) {
			cpu_relax();

			/*
			 * CPU1 could have already entered & exited idle
			 * without hitting off because of a wakeup
			 * or a failed attempt to hit off mode.  Check for
			 * that here, otherwise we could spin forever
			 * waiting for CPU1 off.
			 */
			if (cpu_done[1])
			    goto fail;

		}
	}

	clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &cpu_id);

	/*
	 * Call idle CPU PM enter notifier chain so that
	 * VFP and per CPU interrupt context is saved.
	 */
	cpu_pm_enter();

	if (dev->cpu == 0) {
		pwrdm_set_logic_retst(mpu_pd, cx->mpu_logic_state);
		omap_set_pwrdm_state(mpu_pd, cx->mpu_state);

		/*
		 * Call idle CPU cluster PM enter notifier chain
		 * to save GIC and wakeupgen context.
		 */
		if ((cx->mpu_state == PWRDM_POWER_RET) &&
			(cx->mpu_logic_state == PWRDM_POWER_OFF))
				cpu_cluster_pm_enter();
	}

	omap4_enter_lowpower(dev->cpu, cx->cpu_state);
	cpu_done[dev->cpu] = true;

	/* Wakeup CPU1 only if it is not offlined */
	if (dev->cpu == 0 && cpumask_test_cpu(1, cpu_online_mask)) {
		clkdm_wakeup(cpu_clkdm[1]);
		clkdm_allow_idle(cpu_clkdm[1]);
	}

	/*
	 * Call idle CPU PM exit notifier chain to restore
	 * VFP and per CPU IRQ context.
	 */
	cpu_pm_exit();

	/*
	 * Call idle CPU cluster PM exit notifier chain
	 * to restore GIC and wakeupgen context.
	 */
	if (omap4_mpuss_read_prev_context_state())
		cpu_cluster_pm_exit();

	clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &cpu_id);

fail:
	cpuidle_coupled_parallel_barrier(dev, &abort_barrier);
	cpu_done[dev->cpu] = false;

	return index;
}

/*
 * For each cpu, setup the broadcast timer because local timers
 * stops for the states above C1.
 */
static void omap_setup_broadcast_timer(void *arg)
{
	int cpu = smp_processor_id();
	clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ON, &cpu);
}

static DEFINE_PER_CPU(struct cpuidle_device, omap4_idle_dev);

static struct cpuidle_driver omap4_idle_driver = {
	.name				= "omap4_idle",
	.owner				= THIS_MODULE,
	.en_core_tk_irqen		= 1,
	.states = {
		{
			/* C1 - CPU0 ON + CPU1 ON + MPU ON */
			.exit_latency = 2 + 2,
			.target_residency = 5,
			.flags = CPUIDLE_FLAG_TIME_VALID,
			.enter = omap4_enter_idle_simple,
			.name = "C1",
			.desc = "MPUSS ON"
		},
		{
			/* C2 - CPU0 OFF + CPU1 OFF + MPU CSWR */
			.exit_latency = 328 + 440,
			.target_residency = 960,
			.flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_COUPLED,
			.enter = omap4_enter_idle_coupled,
			.name = "C2",
			.desc = "MPUSS CSWR",
		},
		{
			/* C3 - CPU0 OFF + CPU1 OFF + MPU OSWR */
			.exit_latency = 460 + 518,
			.target_residency = 1100,
			.flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_COUPLED,
			.enter = omap4_enter_idle_coupled,
			.name = "C3",
			.desc = "MPUSS OSWR",
		},
	},
	.state_count = ARRAY_SIZE(omap4_idle_data),
	.safe_state_index = 0,
};

/* Public functions */

/**
 * omap4_idle_init - Init routine for OMAP4 idle
 *
 * Registers the OMAP4 specific cpuidle driver to the cpuidle
 * framework with the valid set of states.
 */
int __init omap4_idle_init(void)
{
	struct cpuidle_device *dev;
	unsigned int cpu_id = 0;

	mpu_pd = pwrdm_lookup("mpu_pwrdm");
	cpu_pd[0] = pwrdm_lookup("cpu0_pwrdm");
	cpu_pd[1] = pwrdm_lookup("cpu1_pwrdm");
	if ((!mpu_pd) || (!cpu_pd[0]) || (!cpu_pd[1]))
		return -ENODEV;

	cpu_clkdm[0] = clkdm_lookup("mpu0_clkdm");
	cpu_clkdm[1] = clkdm_lookup("mpu1_clkdm");
	if (!cpu_clkdm[0] || !cpu_clkdm[1])
		return -ENODEV;

	/* Configure the broadcast timer on each cpu */
	on_each_cpu(omap_setup_broadcast_timer, NULL, 1);

	for_each_cpu(cpu_id, cpu_online_mask) {
		dev = &per_cpu(omap4_idle_dev, cpu_id);
		dev->cpu = cpu_id;
#ifdef CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED
		dev->coupled_cpus = *cpu_online_mask;
#endif
		cpuidle_register_driver(&omap4_idle_driver);

		if (cpuidle_register_device(dev)) {
			pr_err("%s: CPUidle register failed\n", __func__);
			return -EIO;
		}
	}

	return 0;
}
Commit	Line	Data
98272660 SS	1	/*
	2	* OMAP4 CPU idle Routines
	3	*
	4	* Copyright (C) 2011 Texas Instruments, Inc.
	5	* Santosh Shilimkar <santosh.shilimkar@ti.com>
	6	* Rajendra Nayak <rnayak@ti.com>
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License version 2 as
	10	* published by the Free Software Foundation.
	11	*/
	12
	13	#include <linux/sched.h>
	14	#include <linux/cpuidle.h>
	15	#include <linux/cpu_pm.h>
	16	#include <linux/export.h>
98be0dde	17	#include <linux/clockchips.h>
98272660 SS	18
	19	#include <asm/proc-fns.h>
	20
	21	#include "common.h"
	22	#include "pm.h"
	23	#include "prm.h"
dd3ad97c	24	#include "clockdomain.h"
98272660	25
7aeb658d	26	/* Machine specific information */
98272660 SS	27	struct omap4_idle_statedata {
	28	u32 cpu_state;
	29	u32 mpu_logic_state;
	30	u32 mpu_state;
98272660 SS	31	};
98272660 SS	32
d0d133d9 DL	33	static struct omap4_idle_statedata omap4_idle_data[] = {
	34	{
	35	.cpu_state = PWRDM_POWER_ON,
	36	.mpu_state = PWRDM_POWER_ON,
	37	.mpu_logic_state = PWRDM_POWER_RET,
	38	},
	39	{
	40	.cpu_state = PWRDM_POWER_OFF,
	41	.mpu_state = PWRDM_POWER_RET,
	42	.mpu_logic_state = PWRDM_POWER_RET,
	43	},
	44	{
	45	.cpu_state = PWRDM_POWER_OFF,
	46	.mpu_state = PWRDM_POWER_RET,
	47	.mpu_logic_state = PWRDM_POWER_OFF,
	48	},
	49	};
98272660	50
dd3ad97c SS	51	static struct powerdomain mpu_pd, cpu_pd[NR_CPUS];
dd3ad97c SS	52	static struct clockdomain *cpu_clkdm[NR_CPUS];
98272660	53
5b4d5bcc KH	54	static atomic_t abort_barrier;
5b4d5bcc KH	55	static bool cpu_done[NR_CPUS];
98272660	56
9db316b6 PW	57	/* Private functions */
9db316b6 PW	58
98272660	59	/**
dd3ad97c	60	* omap4_enter_idle_coupled_[simple/coupled] - OMAP4 cpuidle entry functions
98272660 SS	61	* @dev: cpuidle device
	62	* @drv: cpuidle driver
	63	* @index: the index of state to be entered
	64	*
	65	* Called from the CPUidle framework to program the device to the
	66	* specified low power state selected by the governor.
	67	* Returns the amount of time spent in the low power state.
	68	*/
dd3ad97c SS	69	static int omap4_enter_idle_simple(struct cpuidle_device *dev,
	70	struct cpuidle_driver *drv,
	71	int index)
	72	{
dd3ad97c	73	omap_do_wfi();
dd3ad97c SS	74	return index;
	75	}
	76
	77	static int omap4_enter_idle_coupled(struct cpuidle_device *dev,
98272660 SS	78	struct cpuidle_driver *drv,
	79	int index)
	80	{
7aeb658d	81	struct omap4_idle_statedata *cx = &omap4_idle_data[index];
98be0dde	82	int cpu_id = smp_processor_id();
98272660	83
98272660	84	/*
dd3ad97c	85	* CPU0 has to wait and stay ON until CPU1 is OFF state.
98272660 SS	86	* This is necessary to honour hardware recommondation
	87	* of triggeing all the possible low power modes once CPU1 is
	88	* out of coherency and in OFF mode.
98272660	89	*/
dd3ad97c	90	if (dev->cpu == 0 && cpumask_test_cpu(1, cpu_online_mask)) {
5b4d5bcc	91	while (pwrdm_read_pwrst(cpu_pd[1]) != PWRDM_POWER_OFF) {
dd3ad97c	92	cpu_relax();
5b4d5bcc KH	93
	94	/*
	95	* CPU1 could have already entered & exited idle
	96	* without hitting off because of a wakeup
	97	* or a failed attempt to hit off mode. Check for
	98	* that here, otherwise we could spin forever
	99	* waiting for CPU1 off.
	100	*/
	101	if (cpu_done[1])
	102	goto fail;
	103
	104	}
98272660 SS	105	}
98272660 SS	106
dd3ad97c	107	clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &cpu_id);
98be0dde	108
98272660 SS	109	/*
	110	* Call idle CPU PM enter notifier chain so that
	111	* VFP and per CPU interrupt context is saved.
	112	*/
dd3ad97c SS	113	cpu_pm_enter();
	114
	115	if (dev->cpu == 0) {
	116	pwrdm_set_logic_retst(mpu_pd, cx->mpu_logic_state);
	117	omap_set_pwrdm_state(mpu_pd, cx->mpu_state);
	118
	119	/*
	120	* Call idle CPU cluster PM enter notifier chain
	121	* to save GIC and wakeupgen context.
	122	*/
	123	if ((cx->mpu_state == PWRDM_POWER_RET) &&
	124	(cx->mpu_logic_state == PWRDM_POWER_OFF))
	125	cpu_cluster_pm_enter();
	126	}
98272660 SS	127
98272660 SS	128	omap4_enter_lowpower(dev->cpu, cx->cpu_state);
5b4d5bcc	129	cpu_done[dev->cpu] = true;
98272660	130
dd3ad97c SS	131	/* Wakeup CPU1 only if it is not offlined */
	132	if (dev->cpu == 0 && cpumask_test_cpu(1, cpu_online_mask)) {
	133	clkdm_wakeup(cpu_clkdm[1]);
	134	clkdm_allow_idle(cpu_clkdm[1]);
	135	}
98272660 SS	136
	137	/*
	138	* Call idle CPU PM exit notifier chain to restore
dd3ad97c	139	* VFP and per CPU IRQ context.
98272660	140	*/
dd3ad97c	141	cpu_pm_exit();
98272660 SS	142
	143	/*
	144	* Call idle CPU cluster PM exit notifier chain
	145	* to restore GIC and wakeupgen context.
	146	*/
	147	if (omap4_mpuss_read_prev_context_state())
	148	cpu_cluster_pm_exit();
	149
dd3ad97c	150	clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &cpu_id);
98be0dde	151
5b4d5bcc KH	152	fail:
	153	cpuidle_coupled_parallel_barrier(dev, &abort_barrier);
	154	cpu_done[dev->cpu] = false;
98be0dde	155
98272660 SS	156	return index;
	157	}
	158
9db316b6 PW	159	/*
	160	* For each cpu, setup the broadcast timer because local timers
	161	* stops for the states above C1.
	162	*/
	163	static void omap_setup_broadcast_timer(void *arg)
	164	{
	165	int cpu = smp_processor_id();
	166	clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ON, &cpu);
	167	}
	168
	169	static DEFINE_PER_CPU(struct cpuidle_device, omap4_idle_dev);
98272660	170
9db316b6	171	static struct cpuidle_driver omap4_idle_driver = {
d13e9261 RL	172	.name = "omap4_idle",
	173	.owner = THIS_MODULE,
	174	.en_core_tk_irqen = 1,
78e9016f DL	175	.states = {
	176	{
	177	/* C1 - CPU0 ON + CPU1 ON + MPU ON */
	178	.exit_latency = 2 + 2,
	179	.target_residency = 5,
	180	.flags = CPUIDLE_FLAG_TIME_VALID,
dd3ad97c	181	.enter = omap4_enter_idle_simple,
78e9016f DL	182	.name = "C1",
	183	.desc = "MPUSS ON"
	184	},
	185	{
9db316b6	186	/* C2 - CPU0 OFF + CPU1 OFF + MPU CSWR */
78e9016f DL	187	.exit_latency = 328 + 440,
78e9016f DL	188	.target_residency = 960,
dd3ad97c SS	189	.flags = CPUIDLE_FLAG_TIME_VALID \| CPUIDLE_FLAG_COUPLED,
dd3ad97c SS	190	.enter = omap4_enter_idle_coupled,
78e9016f DL	191	.name = "C2",
	192	.desc = "MPUSS CSWR",
	193	},
	194	{
	195	/* C3 - CPU0 OFF + CPU1 OFF + MPU OSWR */
	196	.exit_latency = 460 + 518,
	197	.target_residency = 1100,
dd3ad97c SS	198	.flags = CPUIDLE_FLAG_TIME_VALID \| CPUIDLE_FLAG_COUPLED,
dd3ad97c SS	199	.enter = omap4_enter_idle_coupled,
78e9016f DL	200	.name = "C3",
	201	.desc = "MPUSS OSWR",
	202	},
	203	},
d0d133d9	204	.state_count = ARRAY_SIZE(omap4_idle_data),
78e9016f	205	.safe_state_index = 0,
98272660 SS	206	};
98272660 SS	207
9db316b6	208	/* Public functions */
b93d70ae	209
98272660 SS	210	/**
	211	* omap4_idle_init - Init routine for OMAP4 idle
	212	*
	213	* Registers the OMAP4 specific cpuidle driver to the cpuidle
	214	* framework with the valid set of states.
	215	*/
	216	int __init omap4_idle_init(void)
	217	{
98272660	218	struct cpuidle_device *dev;
98272660 SS	219	unsigned int cpu_id = 0;
	220
	221	mpu_pd = pwrdm_lookup("mpu_pwrdm");
dd3ad97c SS	222	cpu_pd[0] = pwrdm_lookup("cpu0_pwrdm");
	223	cpu_pd[1] = pwrdm_lookup("cpu1_pwrdm");
	224	if ((!mpu_pd) \|\| (!cpu_pd[0]) \|\| (!cpu_pd[1]))
98272660 SS	225	return -ENODEV;
98272660 SS	226
dd3ad97c SS	227	cpu_clkdm[0] = clkdm_lookup("mpu0_clkdm");
	228	cpu_clkdm[1] = clkdm_lookup("mpu1_clkdm");
	229	if (!cpu_clkdm[0] \|\| !cpu_clkdm[1])
98272660 SS	230	return -ENODEV;
98272660 SS	231
b93d70ae SS	232	/* Configure the broadcast timer on each cpu */
	233	on_each_cpu(omap_setup_broadcast_timer, NULL, 1);
	234
dd3ad97c SS	235	for_each_cpu(cpu_id, cpu_online_mask) {
	236	dev = &per_cpu(omap4_idle_dev, cpu_id);
	237	dev->cpu = cpu_id;
c7a9b09b	238	#ifdef CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED
dd3ad97c	239	dev->coupled_cpus = *cpu_online_mask;
c7a9b09b	240	#endif
dd3ad97c	241	cpuidle_register_driver(&omap4_idle_driver);
98272660	242
dd3ad97c SS	243	if (cpuidle_register_device(dev)) {
	244	pr_err("%s: CPUidle register failed\n", __func__);
	245	return -EIO;
	246	}
78e9016f	247	}
98272660 SS	248
	249	return 0;
	250	}