Commit | Line | Data |
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98272660 SS |
1 | /* |
2 | * OMAP4 CPU idle Routines | |
3 | * | |
4 | * Copyright (C) 2011 Texas Instruments, Inc. | |
5 | * Santosh Shilimkar <santosh.shilimkar@ti.com> | |
6 | * Rajendra Nayak <rnayak@ti.com> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | */ | |
12 | ||
13 | #include <linux/sched.h> | |
14 | #include <linux/cpuidle.h> | |
15 | #include <linux/cpu_pm.h> | |
16 | #include <linux/export.h> | |
17 | ||
18 | #include <asm/proc-fns.h> | |
19 | ||
20 | #include "common.h" | |
21 | #include "pm.h" | |
22 | #include "prm.h" | |
dd3ad97c | 23 | #include "clockdomain.h" |
98272660 | 24 | |
7aeb658d | 25 | /* Machine specific information */ |
98272660 SS |
26 | struct omap4_idle_statedata { |
27 | u32 cpu_state; | |
28 | u32 mpu_logic_state; | |
29 | u32 mpu_state; | |
98272660 SS |
30 | }; |
31 | ||
d0d133d9 DL |
32 | static struct omap4_idle_statedata omap4_idle_data[] = { |
33 | { | |
34 | .cpu_state = PWRDM_POWER_ON, | |
35 | .mpu_state = PWRDM_POWER_ON, | |
36 | .mpu_logic_state = PWRDM_POWER_RET, | |
37 | }, | |
38 | { | |
39 | .cpu_state = PWRDM_POWER_OFF, | |
40 | .mpu_state = PWRDM_POWER_RET, | |
41 | .mpu_logic_state = PWRDM_POWER_RET, | |
42 | }, | |
43 | { | |
44 | .cpu_state = PWRDM_POWER_OFF, | |
45 | .mpu_state = PWRDM_POWER_RET, | |
46 | .mpu_logic_state = PWRDM_POWER_OFF, | |
47 | }, | |
48 | }; | |
98272660 | 49 | |
dd3ad97c SS |
50 | static struct powerdomain *mpu_pd, *cpu_pd[NR_CPUS]; |
51 | static struct clockdomain *cpu_clkdm[NR_CPUS]; | |
98272660 | 52 | |
5b4d5bcc KH |
53 | static atomic_t abort_barrier; |
54 | static bool cpu_done[NR_CPUS]; | |
98272660 | 55 | |
9db316b6 PW |
56 | /* Private functions */ |
57 | ||
98272660 | 58 | /** |
dd3ad97c | 59 | * omap4_enter_idle_coupled_[simple/coupled] - OMAP4 cpuidle entry functions |
98272660 SS |
60 | * @dev: cpuidle device |
61 | * @drv: cpuidle driver | |
62 | * @index: the index of state to be entered | |
63 | * | |
64 | * Called from the CPUidle framework to program the device to the | |
65 | * specified low power state selected by the governor. | |
66 | * Returns the amount of time spent in the low power state. | |
67 | */ | |
dd3ad97c SS |
68 | static int omap4_enter_idle_simple(struct cpuidle_device *dev, |
69 | struct cpuidle_driver *drv, | |
70 | int index) | |
71 | { | |
72 | local_fiq_disable(); | |
73 | omap_do_wfi(); | |
74 | local_fiq_enable(); | |
75 | ||
76 | return index; | |
77 | } | |
78 | ||
79 | static int omap4_enter_idle_coupled(struct cpuidle_device *dev, | |
98272660 SS |
80 | struct cpuidle_driver *drv, |
81 | int index) | |
82 | { | |
7aeb658d | 83 | struct omap4_idle_statedata *cx = &omap4_idle_data[index]; |
98272660 | 84 | |
98272660 SS |
85 | local_fiq_disable(); |
86 | ||
87 | /* | |
dd3ad97c | 88 | * CPU0 has to wait and stay ON until CPU1 is OFF state. |
98272660 SS |
89 | * This is necessary to honour hardware recommondation |
90 | * of triggeing all the possible low power modes once CPU1 is | |
91 | * out of coherency and in OFF mode. | |
98272660 | 92 | */ |
dd3ad97c | 93 | if (dev->cpu == 0 && cpumask_test_cpu(1, cpu_online_mask)) { |
5b4d5bcc | 94 | while (pwrdm_read_pwrst(cpu_pd[1]) != PWRDM_POWER_OFF) { |
dd3ad97c | 95 | cpu_relax(); |
5b4d5bcc KH |
96 | |
97 | /* | |
98 | * CPU1 could have already entered & exited idle | |
99 | * without hitting off because of a wakeup | |
100 | * or a failed attempt to hit off mode. Check for | |
101 | * that here, otherwise we could spin forever | |
102 | * waiting for CPU1 off. | |
103 | */ | |
104 | if (cpu_done[1]) | |
105 | goto fail; | |
106 | ||
107 | } | |
98272660 SS |
108 | } |
109 | ||
110 | /* | |
111 | * Call idle CPU PM enter notifier chain so that | |
112 | * VFP and per CPU interrupt context is saved. | |
113 | */ | |
dd3ad97c SS |
114 | cpu_pm_enter(); |
115 | ||
116 | if (dev->cpu == 0) { | |
117 | pwrdm_set_logic_retst(mpu_pd, cx->mpu_logic_state); | |
118 | omap_set_pwrdm_state(mpu_pd, cx->mpu_state); | |
119 | ||
120 | /* | |
121 | * Call idle CPU cluster PM enter notifier chain | |
122 | * to save GIC and wakeupgen context. | |
123 | */ | |
124 | if ((cx->mpu_state == PWRDM_POWER_RET) && | |
125 | (cx->mpu_logic_state == PWRDM_POWER_OFF)) | |
126 | cpu_cluster_pm_enter(); | |
127 | } | |
98272660 SS |
128 | |
129 | omap4_enter_lowpower(dev->cpu, cx->cpu_state); | |
5b4d5bcc | 130 | cpu_done[dev->cpu] = true; |
98272660 | 131 | |
dd3ad97c SS |
132 | /* Wakeup CPU1 only if it is not offlined */ |
133 | if (dev->cpu == 0 && cpumask_test_cpu(1, cpu_online_mask)) { | |
134 | clkdm_wakeup(cpu_clkdm[1]); | |
135 | clkdm_allow_idle(cpu_clkdm[1]); | |
136 | } | |
98272660 SS |
137 | |
138 | /* | |
139 | * Call idle CPU PM exit notifier chain to restore | |
dd3ad97c | 140 | * VFP and per CPU IRQ context. |
98272660 | 141 | */ |
dd3ad97c | 142 | cpu_pm_exit(); |
98272660 SS |
143 | |
144 | /* | |
145 | * Call idle CPU cluster PM exit notifier chain | |
146 | * to restore GIC and wakeupgen context. | |
147 | */ | |
e7457253 SS |
148 | if ((cx->mpu_state == PWRDM_POWER_RET) && |
149 | (cx->mpu_logic_state == PWRDM_POWER_OFF)) | |
98272660 SS |
150 | cpu_cluster_pm_exit(); |
151 | ||
5b4d5bcc KH |
152 | fail: |
153 | cpuidle_coupled_parallel_barrier(dev, &abort_barrier); | |
154 | cpu_done[dev->cpu] = false; | |
98be0dde | 155 | |
98272660 SS |
156 | local_fiq_enable(); |
157 | ||
98272660 SS |
158 | return index; |
159 | } | |
160 | ||
9db316b6 | 161 | static DEFINE_PER_CPU(struct cpuidle_device, omap4_idle_dev); |
98272660 | 162 | |
9db316b6 | 163 | static struct cpuidle_driver omap4_idle_driver = { |
d13e9261 RL |
164 | .name = "omap4_idle", |
165 | .owner = THIS_MODULE, | |
166 | .en_core_tk_irqen = 1, | |
78e9016f DL |
167 | .states = { |
168 | { | |
169 | /* C1 - CPU0 ON + CPU1 ON + MPU ON */ | |
170 | .exit_latency = 2 + 2, | |
171 | .target_residency = 5, | |
172 | .flags = CPUIDLE_FLAG_TIME_VALID, | |
dd3ad97c | 173 | .enter = omap4_enter_idle_simple, |
78e9016f | 174 | .name = "C1", |
eb495d33 | 175 | .desc = "CPUx ON, MPUSS ON" |
78e9016f DL |
176 | }, |
177 | { | |
9db316b6 | 178 | /* C2 - CPU0 OFF + CPU1 OFF + MPU CSWR */ |
78e9016f DL |
179 | .exit_latency = 328 + 440, |
180 | .target_residency = 960, | |
cb7094e8 DL |
181 | .flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_COUPLED | |
182 | CPUIDLE_FLAG_TIMER_STOP, | |
dd3ad97c | 183 | .enter = omap4_enter_idle_coupled, |
78e9016f | 184 | .name = "C2", |
eb495d33 | 185 | .desc = "CPUx OFF, MPUSS CSWR", |
78e9016f DL |
186 | }, |
187 | { | |
188 | /* C3 - CPU0 OFF + CPU1 OFF + MPU OSWR */ | |
189 | .exit_latency = 460 + 518, | |
190 | .target_residency = 1100, | |
cb7094e8 DL |
191 | .flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_COUPLED | |
192 | CPUIDLE_FLAG_TIMER_STOP, | |
dd3ad97c | 193 | .enter = omap4_enter_idle_coupled, |
78e9016f | 194 | .name = "C3", |
eb495d33 | 195 | .desc = "CPUx OFF, MPUSS OSWR", |
78e9016f DL |
196 | }, |
197 | }, | |
d0d133d9 | 198 | .state_count = ARRAY_SIZE(omap4_idle_data), |
78e9016f | 199 | .safe_state_index = 0, |
98272660 SS |
200 | }; |
201 | ||
9db316b6 | 202 | /* Public functions */ |
b93d70ae | 203 | |
98272660 SS |
204 | /** |
205 | * omap4_idle_init - Init routine for OMAP4 idle | |
206 | * | |
207 | * Registers the OMAP4 specific cpuidle driver to the cpuidle | |
208 | * framework with the valid set of states. | |
209 | */ | |
210 | int __init omap4_idle_init(void) | |
211 | { | |
98272660 | 212 | struct cpuidle_device *dev; |
98272660 SS |
213 | unsigned int cpu_id = 0; |
214 | ||
215 | mpu_pd = pwrdm_lookup("mpu_pwrdm"); | |
dd3ad97c SS |
216 | cpu_pd[0] = pwrdm_lookup("cpu0_pwrdm"); |
217 | cpu_pd[1] = pwrdm_lookup("cpu1_pwrdm"); | |
218 | if ((!mpu_pd) || (!cpu_pd[0]) || (!cpu_pd[1])) | |
98272660 SS |
219 | return -ENODEV; |
220 | ||
dd3ad97c SS |
221 | cpu_clkdm[0] = clkdm_lookup("mpu0_clkdm"); |
222 | cpu_clkdm[1] = clkdm_lookup("mpu1_clkdm"); | |
223 | if (!cpu_clkdm[0] || !cpu_clkdm[1]) | |
98272660 SS |
224 | return -ENODEV; |
225 | ||
63b951ed SS |
226 | if (cpuidle_register_driver(&omap4_idle_driver)) { |
227 | pr_err("%s: CPUidle driver register failed\n", __func__); | |
228 | return -EIO; | |
229 | } | |
dbd1ba6a | 230 | |
dd3ad97c SS |
231 | for_each_cpu(cpu_id, cpu_online_mask) { |
232 | dev = &per_cpu(omap4_idle_dev, cpu_id); | |
233 | dev->cpu = cpu_id; | |
c7a9b09b | 234 | #ifdef CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED |
dd3ad97c | 235 | dev->coupled_cpus = *cpu_online_mask; |
c7a9b09b | 236 | #endif |
dd3ad97c SS |
237 | if (cpuidle_register_device(dev)) { |
238 | pr_err("%s: CPUidle register failed\n", __func__); | |
63b951ed | 239 | cpuidle_unregister_driver(&omap4_idle_driver); |
dd3ad97c SS |
240 | return -EIO; |
241 | } | |
78e9016f | 242 | } |
98272660 SS |
243 | |
244 | return 0; | |
245 | } |