Commit | Line | Data |
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1dbae815 TL |
1 | /* |
2 | * linux/arch/arm/mach-omap2/devices.c | |
3 | * | |
4 | * OMAP2 platform device setup/initialization | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License, or | |
9 | * (at your option) any later version. | |
10 | */ | |
11 | ||
1dbae815 TL |
12 | #include <linux/kernel.h> |
13 | #include <linux/init.h> | |
14 | #include <linux/platform_device.h> | |
fced80c7 | 15 | #include <linux/io.h> |
917fa280 | 16 | #include <linux/clk.h> |
f2ce6231 | 17 | #include <linux/err.h> |
1dbae815 | 18 | |
a09e64fb | 19 | #include <mach/hardware.h> |
88341334 | 20 | #include <mach/irqs.h> |
1dbae815 TL |
21 | #include <asm/mach-types.h> |
22 | #include <asm/mach/map.h> | |
88341334 | 23 | #include <asm/pmu.h> |
1dbae815 | 24 | |
ce491cf8 TL |
25 | #include <plat/tc.h> |
26 | #include <plat/board.h> | |
a09f73fa | 27 | #include <plat/mcbsp.h> |
a09e64fb | 28 | #include <mach/gpio.h> |
ce491cf8 | 29 | #include <plat/mmc.h> |
ee5500c4 | 30 | #include <plat/dma.h> |
f2ce6231 VC |
31 | #include <plat/omap_hwmod.h> |
32 | #include <plat/omap_device.h> | |
1dbae815 | 33 | |
4896e394 | 34 | #include "mux.h" |
4814ced5 | 35 | #include "control.h" |
4896e394 | 36 | |
828c707e | 37 | #if defined(CONFIG_VIDEO_OMAP2) || defined(CONFIG_VIDEO_OMAP2_MODULE) |
c40fae95 | 38 | |
828c707e | 39 | static struct resource cam_resources[] = { |
c40fae95 | 40 | { |
828c707e TL |
41 | .start = OMAP24XX_CAMERA_BASE, |
42 | .end = OMAP24XX_CAMERA_BASE + 0xfff, | |
43 | .flags = IORESOURCE_MEM, | |
44 | }, | |
45 | { | |
46 | .start = INT_24XX_CAM_IRQ, | |
47 | .flags = IORESOURCE_IRQ, | |
48 | } | |
49 | }; | |
50 | ||
51 | static struct platform_device omap_cam_device = { | |
52 | .name = "omap24xxcam", | |
53 | .id = -1, | |
54 | .num_resources = ARRAY_SIZE(cam_resources), | |
55 | .resource = cam_resources, | |
56 | }; | |
57 | ||
58 | static inline void omap_init_camera(void) | |
59 | { | |
60 | platform_device_register(&omap_cam_device); | |
61 | } | |
62 | ||
63 | #elif defined(CONFIG_VIDEO_OMAP3) || defined(CONFIG_VIDEO_OMAP3_MODULE) | |
64 | ||
65 | static struct resource omap3isp_resources[] = { | |
66 | { | |
67 | .start = OMAP3430_ISP_BASE, | |
68 | .end = OMAP3430_ISP_END, | |
69 | .flags = IORESOURCE_MEM, | |
70 | }, | |
71 | { | |
72 | .start = OMAP3430_ISP_CBUFF_BASE, | |
73 | .end = OMAP3430_ISP_CBUFF_END, | |
74 | .flags = IORESOURCE_MEM, | |
75 | }, | |
76 | { | |
77 | .start = OMAP3430_ISP_CCP2_BASE, | |
78 | .end = OMAP3430_ISP_CCP2_END, | |
79 | .flags = IORESOURCE_MEM, | |
80 | }, | |
81 | { | |
82 | .start = OMAP3430_ISP_CCDC_BASE, | |
83 | .end = OMAP3430_ISP_CCDC_END, | |
84 | .flags = IORESOURCE_MEM, | |
85 | }, | |
86 | { | |
87 | .start = OMAP3430_ISP_HIST_BASE, | |
88 | .end = OMAP3430_ISP_HIST_END, | |
89 | .flags = IORESOURCE_MEM, | |
90 | }, | |
91 | { | |
92 | .start = OMAP3430_ISP_H3A_BASE, | |
93 | .end = OMAP3430_ISP_H3A_END, | |
94 | .flags = IORESOURCE_MEM, | |
95 | }, | |
96 | { | |
97 | .start = OMAP3430_ISP_PREV_BASE, | |
98 | .end = OMAP3430_ISP_PREV_END, | |
99 | .flags = IORESOURCE_MEM, | |
100 | }, | |
101 | { | |
102 | .start = OMAP3430_ISP_RESZ_BASE, | |
103 | .end = OMAP3430_ISP_RESZ_END, | |
104 | .flags = IORESOURCE_MEM, | |
105 | }, | |
106 | { | |
107 | .start = OMAP3430_ISP_SBL_BASE, | |
108 | .end = OMAP3430_ISP_SBL_END, | |
109 | .flags = IORESOURCE_MEM, | |
110 | }, | |
111 | { | |
112 | .start = OMAP3430_ISP_CSI2A_BASE, | |
113 | .end = OMAP3430_ISP_CSI2A_END, | |
114 | .flags = IORESOURCE_MEM, | |
115 | }, | |
116 | { | |
117 | .start = OMAP3430_ISP_CSI2PHY_BASE, | |
118 | .end = OMAP3430_ISP_CSI2PHY_END, | |
119 | .flags = IORESOURCE_MEM, | |
120 | }, | |
121 | { | |
122 | .start = INT_34XX_CAM_IRQ, | |
123 | .flags = IORESOURCE_IRQ, | |
124 | } | |
125 | }; | |
126 | ||
127 | static struct platform_device omap3isp_device = { | |
128 | .name = "omap3isp", | |
129 | .id = -1, | |
130 | .num_resources = ARRAY_SIZE(omap3isp_resources), | |
131 | .resource = omap3isp_resources, | |
132 | }; | |
133 | ||
134 | static inline void omap_init_camera(void) | |
135 | { | |
136 | platform_device_register(&omap3isp_device); | |
137 | } | |
138 | #else | |
139 | static inline void omap_init_camera(void) | |
140 | { | |
141 | } | |
142 | #endif | |
143 | ||
6c20a683 | 144 | #if defined(CONFIG_OMAP_MBOX_FWK) || defined(CONFIG_OMAP_MBOX_FWK_MODULE) |
c40fae95 | 145 | |
454bf340 | 146 | #define MBOX_REG_SIZE 0x120 |
6c20a683 | 147 | |
454bf340 | 148 | #ifdef CONFIG_ARCH_OMAP2 |
d10f2b6e | 149 | static struct resource omap2_mbox_resources[] = { |
c40fae95 | 150 | { |
6c20a683 HD |
151 | .start = OMAP24XX_MAILBOX_BASE, |
152 | .end = OMAP24XX_MAILBOX_BASE + MBOX_REG_SIZE - 1, | |
c40fae95 TL |
153 | .flags = IORESOURCE_MEM, |
154 | }, | |
155 | { | |
156 | .start = INT_24XX_MAIL_U0_MPU, | |
157 | .flags = IORESOURCE_IRQ, | |
1f2c4dfd | 158 | .name = "dsp", |
c40fae95 TL |
159 | }, |
160 | { | |
161 | .start = INT_24XX_MAIL_U3_MPU, | |
162 | .flags = IORESOURCE_IRQ, | |
1f2c4dfd | 163 | .name = "iva", |
c40fae95 TL |
164 | }, |
165 | }; | |
d10f2b6e TL |
166 | static int omap2_mbox_resources_sz = ARRAY_SIZE(omap2_mbox_resources); |
167 | #else | |
168 | #define omap2_mbox_resources NULL | |
169 | #define omap2_mbox_resources_sz 0 | |
454bf340 | 170 | #endif |
c40fae95 | 171 | |
454bf340 | 172 | #ifdef CONFIG_ARCH_OMAP3 |
d10f2b6e | 173 | static struct resource omap3_mbox_resources[] = { |
6c20a683 HD |
174 | { |
175 | .start = OMAP34XX_MAILBOX_BASE, | |
176 | .end = OMAP34XX_MAILBOX_BASE + MBOX_REG_SIZE - 1, | |
177 | .flags = IORESOURCE_MEM, | |
178 | }, | |
179 | { | |
180 | .start = INT_24XX_MAIL_U0_MPU, | |
181 | .flags = IORESOURCE_IRQ, | |
1f2c4dfd | 182 | .name = "dsp", |
6c20a683 HD |
183 | }, |
184 | }; | |
d10f2b6e TL |
185 | static int omap3_mbox_resources_sz = ARRAY_SIZE(omap3_mbox_resources); |
186 | #else | |
187 | #define omap3_mbox_resources NULL | |
188 | #define omap3_mbox_resources_sz 0 | |
454bf340 S |
189 | #endif |
190 | ||
191 | #ifdef CONFIG_ARCH_OMAP4 | |
192 | ||
193 | #define OMAP4_MBOX_REG_SIZE 0x130 | |
d10f2b6e | 194 | static struct resource omap4_mbox_resources[] = { |
454bf340 S |
195 | { |
196 | .start = OMAP44XX_MAILBOX_BASE, | |
197 | .end = OMAP44XX_MAILBOX_BASE + | |
198 | OMAP4_MBOX_REG_SIZE - 1, | |
199 | .flags = IORESOURCE_MEM, | |
200 | }, | |
201 | { | |
5772ca7d | 202 | .start = OMAP44XX_IRQ_MAIL_U0, |
454bf340 | 203 | .flags = IORESOURCE_IRQ, |
1f2c4dfd | 204 | .name = "mbox", |
454bf340 S |
205 | }, |
206 | }; | |
d10f2b6e TL |
207 | static int omap4_mbox_resources_sz = ARRAY_SIZE(omap4_mbox_resources); |
208 | #else | |
209 | #define omap4_mbox_resources NULL | |
210 | #define omap4_mbox_resources_sz 0 | |
454bf340 | 211 | #endif |
6c20a683 | 212 | |
c40fae95 | 213 | static struct platform_device mbox_device = { |
d742709e | 214 | .name = "omap-mailbox", |
c40fae95 | 215 | .id = -1, |
c40fae95 TL |
216 | }; |
217 | ||
218 | static inline void omap_init_mbox(void) | |
219 | { | |
d10f2b6e TL |
220 | if (cpu_is_omap24xx()) { |
221 | mbox_device.resource = omap2_mbox_resources; | |
222 | mbox_device.num_resources = omap2_mbox_resources_sz; | |
223 | } else if (cpu_is_omap34xx()) { | |
224 | mbox_device.resource = omap3_mbox_resources; | |
225 | mbox_device.num_resources = omap3_mbox_resources_sz; | |
226 | } else if (cpu_is_omap44xx()) { | |
227 | mbox_device.resource = omap4_mbox_resources; | |
228 | mbox_device.num_resources = omap4_mbox_resources_sz; | |
6c20a683 HD |
229 | } else { |
230 | pr_err("%s: platform not supported\n", __func__); | |
231 | return; | |
232 | } | |
c40fae95 TL |
233 | platform_device_register(&mbox_device); |
234 | } | |
235 | #else | |
236 | static inline void omap_init_mbox(void) { } | |
6c20a683 | 237 | #endif /* CONFIG_OMAP_MBOX_FWK */ |
c40fae95 | 238 | |
9b6553cd | 239 | static inline void omap_init_sti(void) {} |
9b6553cd | 240 | |
f0fba2ad LG |
241 | #if defined(CONFIG_SND_SOC) || defined(CONFIG_SND_SOC_MODULE) |
242 | ||
243 | static struct platform_device omap_pcm = { | |
244 | .name = "omap-pcm-audio", | |
245 | .id = -1, | |
246 | }; | |
247 | ||
248 | /* | |
249 | * OMAP2420 has 2 McBSP ports | |
250 | * OMAP2430 has 5 McBSP ports | |
251 | * OMAP3 has 5 McBSP ports | |
252 | * OMAP4 has 4 McBSP ports | |
253 | */ | |
254 | OMAP_MCBSP_PLATFORM_DEVICE(1); | |
255 | OMAP_MCBSP_PLATFORM_DEVICE(2); | |
256 | OMAP_MCBSP_PLATFORM_DEVICE(3); | |
257 | OMAP_MCBSP_PLATFORM_DEVICE(4); | |
258 | OMAP_MCBSP_PLATFORM_DEVICE(5); | |
259 | ||
260 | static void omap_init_audio(void) | |
261 | { | |
262 | platform_device_register(&omap_mcbsp1); | |
263 | platform_device_register(&omap_mcbsp2); | |
264 | if (cpu_is_omap243x() || cpu_is_omap34xx() || cpu_is_omap44xx()) { | |
265 | platform_device_register(&omap_mcbsp3); | |
266 | platform_device_register(&omap_mcbsp4); | |
267 | } | |
268 | if (cpu_is_omap243x() || cpu_is_omap34xx()) | |
269 | platform_device_register(&omap_mcbsp5); | |
270 | ||
271 | platform_device_register(&omap_pcm); | |
272 | } | |
273 | ||
274 | #else | |
275 | static inline void omap_init_audio(void) {} | |
276 | #endif | |
277 | ||
646e3ed1 | 278 | #if defined(CONFIG_SPI_OMAP24XX) || defined(CONFIG_SPI_OMAP24XX_MODULE) |
ed7eb9d9 | 279 | |
ce491cf8 | 280 | #include <plat/mcspi.h> |
ed7eb9d9 JY |
281 | |
282 | #define OMAP2_MCSPI1_BASE 0x48098000 | |
283 | #define OMAP2_MCSPI2_BASE 0x4809a000 | |
646e3ed1 TL |
284 | #define OMAP2_MCSPI3_BASE 0x480b8000 |
285 | #define OMAP2_MCSPI4_BASE 0x480ba000 | |
ed7eb9d9 | 286 | |
7869c0b9 SR |
287 | #define OMAP4_MCSPI1_BASE 0x48098100 |
288 | #define OMAP4_MCSPI2_BASE 0x4809a100 | |
289 | #define OMAP4_MCSPI3_BASE 0x480b8100 | |
290 | #define OMAP4_MCSPI4_BASE 0x480ba100 | |
291 | ||
ed7eb9d9 | 292 | static struct omap2_mcspi_platform_config omap2_mcspi1_config = { |
ed7eb9d9 JY |
293 | .num_cs = 4, |
294 | }; | |
295 | ||
c40fae95 TL |
296 | static struct resource omap2_mcspi1_resources[] = { |
297 | { | |
298 | .start = OMAP2_MCSPI1_BASE, | |
299 | .end = OMAP2_MCSPI1_BASE + 0xff, | |
300 | .flags = IORESOURCE_MEM, | |
301 | }, | |
302 | }; | |
303 | ||
646e3ed1 | 304 | static struct platform_device omap2_mcspi1 = { |
ed7eb9d9 JY |
305 | .name = "omap2_mcspi", |
306 | .id = 1, | |
c40fae95 TL |
307 | .num_resources = ARRAY_SIZE(omap2_mcspi1_resources), |
308 | .resource = omap2_mcspi1_resources, | |
ed7eb9d9 JY |
309 | .dev = { |
310 | .platform_data = &omap2_mcspi1_config, | |
311 | }, | |
312 | }; | |
313 | ||
314 | static struct omap2_mcspi_platform_config omap2_mcspi2_config = { | |
ed7eb9d9 JY |
315 | .num_cs = 2, |
316 | }; | |
317 | ||
c40fae95 TL |
318 | static struct resource omap2_mcspi2_resources[] = { |
319 | { | |
320 | .start = OMAP2_MCSPI2_BASE, | |
321 | .end = OMAP2_MCSPI2_BASE + 0xff, | |
322 | .flags = IORESOURCE_MEM, | |
323 | }, | |
324 | }; | |
325 | ||
646e3ed1 | 326 | static struct platform_device omap2_mcspi2 = { |
ed7eb9d9 JY |
327 | .name = "omap2_mcspi", |
328 | .id = 2, | |
c40fae95 TL |
329 | .num_resources = ARRAY_SIZE(omap2_mcspi2_resources), |
330 | .resource = omap2_mcspi2_resources, | |
ed7eb9d9 JY |
331 | .dev = { |
332 | .platform_data = &omap2_mcspi2_config, | |
333 | }, | |
334 | }; | |
335 | ||
59b479e0 | 336 | #if defined(CONFIG_SOC_OMAP2430) || defined(CONFIG_ARCH_OMAP3) || \ |
7869c0b9 | 337 | defined(CONFIG_ARCH_OMAP4) |
646e3ed1 TL |
338 | static struct omap2_mcspi_platform_config omap2_mcspi3_config = { |
339 | .num_cs = 2, | |
340 | }; | |
341 | ||
342 | static struct resource omap2_mcspi3_resources[] = { | |
343 | { | |
344 | .start = OMAP2_MCSPI3_BASE, | |
345 | .end = OMAP2_MCSPI3_BASE + 0xff, | |
346 | .flags = IORESOURCE_MEM, | |
347 | }, | |
348 | }; | |
349 | ||
350 | static struct platform_device omap2_mcspi3 = { | |
351 | .name = "omap2_mcspi", | |
352 | .id = 3, | |
353 | .num_resources = ARRAY_SIZE(omap2_mcspi3_resources), | |
354 | .resource = omap2_mcspi3_resources, | |
355 | .dev = { | |
356 | .platform_data = &omap2_mcspi3_config, | |
357 | }, | |
358 | }; | |
359 | #endif | |
360 | ||
7869c0b9 | 361 | #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4) |
646e3ed1 TL |
362 | static struct omap2_mcspi_platform_config omap2_mcspi4_config = { |
363 | .num_cs = 1, | |
364 | }; | |
365 | ||
366 | static struct resource omap2_mcspi4_resources[] = { | |
367 | { | |
368 | .start = OMAP2_MCSPI4_BASE, | |
369 | .end = OMAP2_MCSPI4_BASE + 0xff, | |
370 | .flags = IORESOURCE_MEM, | |
371 | }, | |
372 | }; | |
373 | ||
374 | static struct platform_device omap2_mcspi4 = { | |
375 | .name = "omap2_mcspi", | |
376 | .id = 4, | |
377 | .num_resources = ARRAY_SIZE(omap2_mcspi4_resources), | |
378 | .resource = omap2_mcspi4_resources, | |
379 | .dev = { | |
380 | .platform_data = &omap2_mcspi4_config, | |
381 | }, | |
382 | }; | |
383 | #endif | |
384 | ||
af41a12f TL |
385 | #ifdef CONFIG_ARCH_OMAP4 |
386 | static inline void omap4_mcspi_fixup(void) | |
ed7eb9d9 | 387 | { |
af41a12f TL |
388 | omap2_mcspi1_resources[0].start = OMAP4_MCSPI1_BASE; |
389 | omap2_mcspi1_resources[0].end = OMAP4_MCSPI1_BASE + 0xff; | |
390 | omap2_mcspi2_resources[0].start = OMAP4_MCSPI2_BASE; | |
391 | omap2_mcspi2_resources[0].end = OMAP4_MCSPI2_BASE + 0xff; | |
392 | omap2_mcspi3_resources[0].start = OMAP4_MCSPI3_BASE; | |
393 | omap2_mcspi3_resources[0].end = OMAP4_MCSPI3_BASE + 0xff; | |
394 | omap2_mcspi4_resources[0].start = OMAP4_MCSPI4_BASE; | |
395 | omap2_mcspi4_resources[0].end = OMAP4_MCSPI4_BASE + 0xff; | |
396 | } | |
397 | #else | |
398 | static inline void omap4_mcspi_fixup(void) | |
399 | { | |
400 | } | |
401 | #endif | |
402 | ||
59b479e0 | 403 | #if defined(CONFIG_SOC_OMAP2430) || defined(CONFIG_ARCH_OMAP3) || \ |
7869c0b9 | 404 | defined(CONFIG_ARCH_OMAP4) |
af41a12f TL |
405 | static inline void omap2_mcspi3_init(void) |
406 | { | |
407 | platform_device_register(&omap2_mcspi3); | |
408 | } | |
409 | #else | |
410 | static inline void omap2_mcspi3_init(void) | |
411 | { | |
412 | } | |
646e3ed1 | 413 | #endif |
af41a12f | 414 | |
7869c0b9 | 415 | #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4) |
af41a12f TL |
416 | static inline void omap2_mcspi4_init(void) |
417 | { | |
418 | platform_device_register(&omap2_mcspi4); | |
419 | } | |
420 | #else | |
421 | static inline void omap2_mcspi4_init(void) | |
422 | { | |
423 | } | |
646e3ed1 | 424 | #endif |
af41a12f TL |
425 | |
426 | static void omap_init_mcspi(void) | |
427 | { | |
428 | if (cpu_is_omap44xx()) | |
429 | omap4_mcspi_fixup(); | |
430 | ||
431 | platform_device_register(&omap2_mcspi1); | |
432 | platform_device_register(&omap2_mcspi2); | |
433 | ||
434 | if (cpu_is_omap2430() || cpu_is_omap343x() || cpu_is_omap44xx()) | |
435 | omap2_mcspi3_init(); | |
436 | ||
437 | if (cpu_is_omap343x() || cpu_is_omap44xx()) | |
438 | omap2_mcspi4_init(); | |
ed7eb9d9 JY |
439 | } |
440 | ||
441 | #else | |
442 | static inline void omap_init_mcspi(void) {} | |
443 | #endif | |
444 | ||
88341334 WD |
445 | static struct resource omap2_pmu_resource = { |
446 | .start = 3, | |
447 | .end = 3, | |
448 | .flags = IORESOURCE_IRQ, | |
449 | }; | |
450 | ||
451 | static struct resource omap3_pmu_resource = { | |
452 | .start = INT_34XX_BENCH_MPU_EMUL, | |
453 | .end = INT_34XX_BENCH_MPU_EMUL, | |
454 | .flags = IORESOURCE_IRQ, | |
455 | }; | |
456 | ||
457 | static struct platform_device omap_pmu_device = { | |
458 | .name = "arm-pmu", | |
459 | .id = ARM_PMU_DEVICE_CPU, | |
460 | .num_resources = 1, | |
461 | }; | |
462 | ||
463 | static void omap_init_pmu(void) | |
464 | { | |
465 | if (cpu_is_omap24xx()) | |
466 | omap_pmu_device.resource = &omap2_pmu_resource; | |
467 | else if (cpu_is_omap34xx()) | |
468 | omap_pmu_device.resource = &omap3_pmu_resource; | |
469 | else | |
470 | return; | |
471 | ||
472 | platform_device_register(&omap_pmu_device); | |
473 | } | |
474 | ||
475 | ||
ee5500c4 DK |
476 | #if defined(CONFIG_CRYPTO_DEV_OMAP_SHAM) || defined(CONFIG_CRYPTO_DEV_OMAP_SHAM_MODULE) |
477 | ||
edc774ed | 478 | #ifdef CONFIG_ARCH_OMAP2 |
ee5500c4 | 479 | static struct resource omap2_sham_resources[] = { |
646e3ed1 TL |
480 | { |
481 | .start = OMAP24XX_SEC_SHA1MD5_BASE, | |
482 | .end = OMAP24XX_SEC_SHA1MD5_BASE + 0x64, | |
483 | .flags = IORESOURCE_MEM, | |
484 | }, | |
485 | { | |
486 | .start = INT_24XX_SHA1MD5, | |
487 | .flags = IORESOURCE_IRQ, | |
488 | } | |
489 | }; | |
ee5500c4 DK |
490 | static int omap2_sham_resources_sz = ARRAY_SIZE(omap2_sham_resources); |
491 | #else | |
492 | #define omap2_sham_resources NULL | |
493 | #define omap2_sham_resources_sz 0 | |
494 | #endif | |
646e3ed1 | 495 | |
edc774ed | 496 | #ifdef CONFIG_ARCH_OMAP3 |
ee5500c4 DK |
497 | static struct resource omap3_sham_resources[] = { |
498 | { | |
499 | .start = OMAP34XX_SEC_SHA1MD5_BASE, | |
500 | .end = OMAP34XX_SEC_SHA1MD5_BASE + 0x64, | |
501 | .flags = IORESOURCE_MEM, | |
502 | }, | |
503 | { | |
504 | .start = INT_34XX_SHA1MD52_IRQ, | |
505 | .flags = IORESOURCE_IRQ, | |
506 | }, | |
507 | { | |
508 | .start = OMAP34XX_DMA_SHA1MD5_RX, | |
509 | .flags = IORESOURCE_DMA, | |
510 | } | |
511 | }; | |
512 | static int omap3_sham_resources_sz = ARRAY_SIZE(omap3_sham_resources); | |
513 | #else | |
514 | #define omap3_sham_resources NULL | |
515 | #define omap3_sham_resources_sz 0 | |
516 | #endif | |
517 | ||
518 | static struct platform_device sham_device = { | |
519 | .name = "omap-sham", | |
646e3ed1 | 520 | .id = -1, |
646e3ed1 TL |
521 | }; |
522 | ||
ee5500c4 | 523 | static void omap_init_sham(void) |
646e3ed1 | 524 | { |
ee5500c4 DK |
525 | if (cpu_is_omap24xx()) { |
526 | sham_device.resource = omap2_sham_resources; | |
527 | sham_device.num_resources = omap2_sham_resources_sz; | |
528 | } else if (cpu_is_omap34xx()) { | |
529 | sham_device.resource = omap3_sham_resources; | |
530 | sham_device.num_resources = omap3_sham_resources_sz; | |
531 | } else { | |
532 | pr_err("%s: platform not supported\n", __func__); | |
533 | return; | |
534 | } | |
535 | platform_device_register(&sham_device); | |
646e3ed1 TL |
536 | } |
537 | #else | |
ee5500c4 | 538 | static inline void omap_init_sham(void) { } |
646e3ed1 TL |
539 | #endif |
540 | ||
b744c679 DK |
541 | #if defined(CONFIG_CRYPTO_DEV_OMAP_AES) || defined(CONFIG_CRYPTO_DEV_OMAP_AES_MODULE) |
542 | ||
82a0c149 | 543 | #ifdef CONFIG_ARCH_OMAP2 |
b744c679 DK |
544 | static struct resource omap2_aes_resources[] = { |
545 | { | |
546 | .start = OMAP24XX_SEC_AES_BASE, | |
547 | .end = OMAP24XX_SEC_AES_BASE + 0x4C, | |
548 | .flags = IORESOURCE_MEM, | |
549 | }, | |
550 | { | |
551 | .start = OMAP24XX_DMA_AES_TX, | |
552 | .flags = IORESOURCE_DMA, | |
553 | }, | |
554 | { | |
555 | .start = OMAP24XX_DMA_AES_RX, | |
556 | .flags = IORESOURCE_DMA, | |
557 | } | |
558 | }; | |
559 | static int omap2_aes_resources_sz = ARRAY_SIZE(omap2_aes_resources); | |
560 | #else | |
561 | #define omap2_aes_resources NULL | |
562 | #define omap2_aes_resources_sz 0 | |
563 | #endif | |
564 | ||
82a0c149 | 565 | #ifdef CONFIG_ARCH_OMAP3 |
b744c679 DK |
566 | static struct resource omap3_aes_resources[] = { |
567 | { | |
568 | .start = OMAP34XX_SEC_AES_BASE, | |
569 | .end = OMAP34XX_SEC_AES_BASE + 0x4C, | |
570 | .flags = IORESOURCE_MEM, | |
571 | }, | |
572 | { | |
573 | .start = OMAP34XX_DMA_AES2_TX, | |
574 | .flags = IORESOURCE_DMA, | |
575 | }, | |
576 | { | |
577 | .start = OMAP34XX_DMA_AES2_RX, | |
578 | .flags = IORESOURCE_DMA, | |
579 | } | |
580 | }; | |
581 | static int omap3_aes_resources_sz = ARRAY_SIZE(omap3_aes_resources); | |
582 | #else | |
583 | #define omap3_aes_resources NULL | |
584 | #define omap3_aes_resources_sz 0 | |
585 | #endif | |
586 | ||
587 | static struct platform_device aes_device = { | |
588 | .name = "omap-aes", | |
589 | .id = -1, | |
590 | }; | |
591 | ||
592 | static void omap_init_aes(void) | |
593 | { | |
594 | if (cpu_is_omap24xx()) { | |
595 | aes_device.resource = omap2_aes_resources; | |
596 | aes_device.num_resources = omap2_aes_resources_sz; | |
597 | } else if (cpu_is_omap34xx()) { | |
598 | aes_device.resource = omap3_aes_resources; | |
599 | aes_device.num_resources = omap3_aes_resources_sz; | |
600 | } else { | |
601 | pr_err("%s: platform not supported\n", __func__); | |
602 | return; | |
603 | } | |
604 | platform_device_register(&aes_device); | |
605 | } | |
606 | ||
607 | #else | |
608 | static inline void omap_init_aes(void) { } | |
609 | #endif | |
610 | ||
d8874665 TL |
611 | /*-------------------------------------------------------------------------*/ |
612 | ||
82cf818d | 613 | #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4) |
917fa280 KH |
614 | |
615 | #define MMCHS_SYSCONFIG 0x0010 | |
616 | #define MMCHS_SYSCONFIG_SWRESET (1 << 1) | |
617 | #define MMCHS_SYSSTATUS 0x0014 | |
618 | #define MMCHS_SYSSTATUS_RESETDONE (1 << 0) | |
619 | ||
620 | static struct platform_device dummy_pdev = { | |
621 | .dev = { | |
622 | .bus = &platform_bus_type, | |
623 | }, | |
624 | }; | |
625 | ||
626 | /** | |
627 | * omap_hsmmc_reset() - Full reset of each HS-MMC controller | |
628 | * | |
629 | * Ensure that each MMC controller is fully reset. Controllers | |
630 | * left in an unknown state (by bootloader) may prevent retention | |
631 | * or OFF-mode. This is especially important in cases where the | |
632 | * MMC driver is not enabled, _or_ built as a module. | |
633 | * | |
634 | * In order for reset to work, interface, functional and debounce | |
635 | * clocks must be enabled. The debounce clock comes from func_32k_clk | |
636 | * and is not under SW control, so we only enable i- and f-clocks. | |
637 | **/ | |
638 | static void __init omap_hsmmc_reset(void) | |
639 | { | |
4323e9f7 | 640 | u32 i, nr_controllers; |
434c23a7 | 641 | struct clk *iclk, *fclk; |
4323e9f7 TL |
642 | |
643 | if (cpu_is_omap242x()) | |
644 | return; | |
645 | ||
646 | nr_controllers = cpu_is_omap44xx() ? OMAP44XX_NR_MMC : | |
82cf818d | 647 | (cpu_is_omap34xx() ? OMAP34XX_NR_MMC : OMAP24XX_NR_MMC); |
917fa280 KH |
648 | |
649 | for (i = 0; i < nr_controllers; i++) { | |
650 | u32 v, base = 0; | |
917fa280 KH |
651 | struct device *dev = &dummy_pdev.dev; |
652 | ||
653 | switch (i) { | |
654 | case 0: | |
655 | base = OMAP2_MMC1_BASE; | |
656 | break; | |
657 | case 1: | |
658 | base = OMAP2_MMC2_BASE; | |
659 | break; | |
660 | case 2: | |
661 | base = OMAP3_MMC3_BASE; | |
662 | break; | |
82cf818d | 663 | case 3: |
664 | if (!cpu_is_omap44xx()) | |
665 | return; | |
666 | base = OMAP4_MMC4_BASE; | |
667 | break; | |
668 | case 4: | |
669 | if (!cpu_is_omap44xx()) | |
670 | return; | |
671 | base = OMAP4_MMC5_BASE; | |
672 | break; | |
917fa280 KH |
673 | } |
674 | ||
82cf818d | 675 | if (cpu_is_omap44xx()) |
676 | base += OMAP4_MMC_REG_OFFSET; | |
677 | ||
917fa280 | 678 | dummy_pdev.id = i; |
1e98ffa8 | 679 | dev_set_name(&dummy_pdev.dev, "mmci-omap-hs.%d", i); |
6f7607cc | 680 | iclk = clk_get(dev, "ick"); |
434c23a7 AK |
681 | if (IS_ERR(iclk)) |
682 | goto err1; | |
683 | if (clk_enable(iclk)) | |
684 | goto err2; | |
917fa280 | 685 | |
6f7607cc | 686 | fclk = clk_get(dev, "fck"); |
434c23a7 AK |
687 | if (IS_ERR(fclk)) |
688 | goto err3; | |
689 | if (clk_enable(fclk)) | |
690 | goto err4; | |
917fa280 KH |
691 | |
692 | omap_writel(MMCHS_SYSCONFIG_SWRESET, base + MMCHS_SYSCONFIG); | |
693 | v = omap_readl(base + MMCHS_SYSSTATUS); | |
694 | while (!(omap_readl(base + MMCHS_SYSSTATUS) & | |
695 | MMCHS_SYSSTATUS_RESETDONE)) | |
696 | cpu_relax(); | |
697 | ||
434c23a7 AK |
698 | clk_disable(fclk); |
699 | clk_put(fclk); | |
700 | clk_disable(iclk); | |
701 | clk_put(iclk); | |
917fa280 | 702 | } |
434c23a7 AK |
703 | return; |
704 | ||
705 | err4: | |
706 | clk_put(fclk); | |
707 | err3: | |
708 | clk_disable(iclk); | |
709 | err2: | |
710 | clk_put(iclk); | |
711 | err1: | |
712 | printk(KERN_WARNING "%s: Unable to enable clocks for MMC%d, " | |
713 | "cannot reset.\n", __func__, i); | |
917fa280 KH |
714 | } |
715 | #else | |
716 | static inline void omap_hsmmc_reset(void) {} | |
717 | #endif | |
718 | ||
d8874665 TL |
719 | #if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE) || \ |
720 | defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE) | |
721 | ||
722 | static inline void omap2_mmc_mux(struct omap_mmc_platform_data *mmc_controller, | |
723 | int controller_nr) | |
724 | { | |
ed8303fc | 725 | if ((mmc_controller->slots[0].switch_pin > 0) && \ |
726 | (mmc_controller->slots[0].switch_pin < OMAP_MAX_GPIO_LINES)) | |
727 | omap_mux_init_gpio(mmc_controller->slots[0].switch_pin, | |
728 | OMAP_PIN_INPUT_PULLUP); | |
729 | if ((mmc_controller->slots[0].gpio_wp > 0) && \ | |
730 | (mmc_controller->slots[0].gpio_wp < OMAP_MAX_GPIO_LINES)) | |
731 | omap_mux_init_gpio(mmc_controller->slots[0].gpio_wp, | |
732 | OMAP_PIN_INPUT_PULLUP); | |
733 | ||
d8874665 | 734 | if (cpu_is_omap2420() && controller_nr == 0) { |
f99bf16d TL |
735 | omap_mux_init_signal("sdmmc_cmd", 0); |
736 | omap_mux_init_signal("sdmmc_clki", 0); | |
737 | omap_mux_init_signal("sdmmc_clko", 0); | |
738 | omap_mux_init_signal("sdmmc_dat0", 0); | |
739 | omap_mux_init_signal("sdmmc_dat_dir0", 0); | |
740 | omap_mux_init_signal("sdmmc_cmd_dir", 0); | |
3a63833e | 741 | if (mmc_controller->slots[0].caps & MMC_CAP_4_BIT_DATA) { |
f99bf16d TL |
742 | omap_mux_init_signal("sdmmc_dat1", 0); |
743 | omap_mux_init_signal("sdmmc_dat2", 0); | |
744 | omap_mux_init_signal("sdmmc_dat3", 0); | |
745 | omap_mux_init_signal("sdmmc_dat_dir1", 0); | |
746 | omap_mux_init_signal("sdmmc_dat_dir2", 0); | |
747 | omap_mux_init_signal("sdmmc_dat_dir3", 0); | |
d8874665 TL |
748 | } |
749 | ||
750 | /* | |
751 | * Use internal loop-back in MMC/SDIO Module Input Clock | |
752 | * selection | |
753 | */ | |
754 | if (mmc_controller->slots[0].internal_clock) { | |
755 | u32 v = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0); | |
756 | v |= (1 << 24); | |
757 | omap_ctrl_writel(v, OMAP2_CONTROL_DEVCONF0); | |
758 | } | |
759 | } | |
57b9daa0 | 760 | |
4596d14a | 761 | if (cpu_is_omap34xx()) { |
57b9daa0 | 762 | if (controller_nr == 0) { |
4896e394 TL |
763 | omap_mux_init_signal("sdmmc1_clk", |
764 | OMAP_PIN_INPUT_PULLUP); | |
765 | omap_mux_init_signal("sdmmc1_cmd", | |
766 | OMAP_PIN_INPUT_PULLUP); | |
767 | omap_mux_init_signal("sdmmc1_dat0", | |
768 | OMAP_PIN_INPUT_PULLUP); | |
3a63833e SG |
769 | if (mmc_controller->slots[0].caps & |
770 | (MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA)) { | |
4896e394 TL |
771 | omap_mux_init_signal("sdmmc1_dat1", |
772 | OMAP_PIN_INPUT_PULLUP); | |
773 | omap_mux_init_signal("sdmmc1_dat2", | |
774 | OMAP_PIN_INPUT_PULLUP); | |
775 | omap_mux_init_signal("sdmmc1_dat3", | |
776 | OMAP_PIN_INPUT_PULLUP); | |
57b9daa0 | 777 | } |
3a63833e SG |
778 | if (mmc_controller->slots[0].caps & |
779 | MMC_CAP_8_BIT_DATA) { | |
4896e394 TL |
780 | omap_mux_init_signal("sdmmc1_dat4", |
781 | OMAP_PIN_INPUT_PULLUP); | |
782 | omap_mux_init_signal("sdmmc1_dat5", | |
783 | OMAP_PIN_INPUT_PULLUP); | |
784 | omap_mux_init_signal("sdmmc1_dat6", | |
785 | OMAP_PIN_INPUT_PULLUP); | |
786 | omap_mux_init_signal("sdmmc1_dat7", | |
787 | OMAP_PIN_INPUT_PULLUP); | |
57b9daa0 VP |
788 | } |
789 | } | |
790 | if (controller_nr == 1) { | |
791 | /* MMC2 */ | |
4896e394 TL |
792 | omap_mux_init_signal("sdmmc2_clk", |
793 | OMAP_PIN_INPUT_PULLUP); | |
794 | omap_mux_init_signal("sdmmc2_cmd", | |
795 | OMAP_PIN_INPUT_PULLUP); | |
796 | omap_mux_init_signal("sdmmc2_dat0", | |
797 | OMAP_PIN_INPUT_PULLUP); | |
57b9daa0 VP |
798 | |
799 | /* | |
800 | * For 8 wire configurations, Lines DAT4, 5, 6 and 7 need to be muxed | |
801 | * in the board-*.c files | |
802 | */ | |
3a63833e SG |
803 | if (mmc_controller->slots[0].caps & |
804 | (MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA)) { | |
4896e394 TL |
805 | omap_mux_init_signal("sdmmc2_dat1", |
806 | OMAP_PIN_INPUT_PULLUP); | |
807 | omap_mux_init_signal("sdmmc2_dat2", | |
808 | OMAP_PIN_INPUT_PULLUP); | |
809 | omap_mux_init_signal("sdmmc2_dat3", | |
810 | OMAP_PIN_INPUT_PULLUP); | |
57b9daa0 | 811 | } |
3a63833e SG |
812 | if (mmc_controller->slots[0].caps & |
813 | MMC_CAP_8_BIT_DATA) { | |
4896e394 TL |
814 | omap_mux_init_signal("sdmmc2_dat4.sdmmc2_dat4", |
815 | OMAP_PIN_INPUT_PULLUP); | |
816 | omap_mux_init_signal("sdmmc2_dat5.sdmmc2_dat5", | |
817 | OMAP_PIN_INPUT_PULLUP); | |
818 | omap_mux_init_signal("sdmmc2_dat6.sdmmc2_dat6", | |
819 | OMAP_PIN_INPUT_PULLUP); | |
820 | omap_mux_init_signal("sdmmc2_dat7.sdmmc2_dat7", | |
821 | OMAP_PIN_INPUT_PULLUP); | |
4679232d | 822 | } |
57b9daa0 VP |
823 | } |
824 | ||
825 | /* | |
826 | * For MMC3 the pins need to be muxed in the board-*.c files | |
827 | */ | |
828 | } | |
d8874665 TL |
829 | } |
830 | ||
831 | void __init omap2_init_mmc(struct omap_mmc_platform_data **mmc_data, | |
832 | int nr_controllers) | |
833 | { | |
834 | int i; | |
0dffb5c5 | 835 | char *name; |
d8874665 TL |
836 | |
837 | for (i = 0; i < nr_controllers; i++) { | |
838 | unsigned long base, size; | |
839 | unsigned int irq = 0; | |
840 | ||
841 | if (!mmc_data[i]) | |
842 | continue; | |
843 | ||
844 | omap2_mmc_mux(mmc_data[i], i); | |
845 | ||
846 | switch (i) { | |
847 | case 0: | |
848 | base = OMAP2_MMC1_BASE; | |
849 | irq = INT_24XX_MMC_IRQ; | |
850 | break; | |
851 | case 1: | |
852 | base = OMAP2_MMC2_BASE; | |
853 | irq = INT_24XX_MMC2_IRQ; | |
854 | break; | |
855 | case 2: | |
82cf818d | 856 | if (!cpu_is_omap44xx() && !cpu_is_omap34xx()) |
d8874665 TL |
857 | return; |
858 | base = OMAP3_MMC3_BASE; | |
859 | irq = INT_34XX_MMC3_IRQ; | |
860 | break; | |
82cf818d | 861 | case 3: |
862 | if (!cpu_is_omap44xx()) | |
863 | return; | |
91a0b089 | 864 | base = OMAP4_MMC4_BASE; |
5772ca7d | 865 | irq = OMAP44XX_IRQ_MMC4; |
82cf818d | 866 | break; |
867 | case 4: | |
868 | if (!cpu_is_omap44xx()) | |
869 | return; | |
91a0b089 | 870 | base = OMAP4_MMC5_BASE; |
9df76b7f | 871 | irq = OMAP44XX_IRQ_MMC5; |
82cf818d | 872 | break; |
d8874665 TL |
873 | default: |
874 | continue; | |
875 | } | |
876 | ||
0dffb5c5 | 877 | if (cpu_is_omap2420()) { |
d8874665 | 878 | size = OMAP2420_MMC_SIZE; |
0dffb5c5 | 879 | name = "mmci-omap"; |
82cf818d | 880 | } else if (cpu_is_omap44xx()) { |
91a0b089 | 881 | if (i < 3) |
5772ca7d | 882 | irq += OMAP44XX_IRQ_GIC_START; |
82cf818d | 883 | size = OMAP4_HSMMC_SIZE; |
884 | name = "mmci-omap-hs"; | |
0dffb5c5 | 885 | } else { |
82cf818d | 886 | size = OMAP3_HSMMC_SIZE; |
0dffb5c5 TL |
887 | name = "mmci-omap-hs"; |
888 | } | |
889 | omap_mmc_add(name, i, base, size, irq, mmc_data[i]); | |
d8874665 TL |
890 | }; |
891 | } | |
892 | ||
893 | #endif | |
894 | ||
895 | /*-------------------------------------------------------------------------*/ | |
896 | ||
646e3ed1 | 897 | #if defined(CONFIG_HDQ_MASTER_OMAP) || defined(CONFIG_HDQ_MASTER_OMAP_MODULE) |
59b479e0 | 898 | #if defined(CONFIG_SOC_OMAP2430) || defined(CONFIG_SOC_OMAP3430) |
646e3ed1 TL |
899 | #define OMAP_HDQ_BASE 0x480B2000 |
900 | #endif | |
901 | static struct resource omap_hdq_resources[] = { | |
902 | { | |
903 | .start = OMAP_HDQ_BASE, | |
904 | .end = OMAP_HDQ_BASE + 0x1C, | |
905 | .flags = IORESOURCE_MEM, | |
906 | }, | |
907 | { | |
908 | .start = INT_24XX_HDQ_IRQ, | |
909 | .flags = IORESOURCE_IRQ, | |
910 | }, | |
911 | }; | |
912 | static struct platform_device omap_hdq_dev = { | |
913 | .name = "omap_hdq", | |
914 | .id = 0, | |
915 | .dev = { | |
916 | .platform_data = NULL, | |
917 | }, | |
918 | .num_resources = ARRAY_SIZE(omap_hdq_resources), | |
919 | .resource = omap_hdq_resources, | |
920 | }; | |
921 | static inline void omap_hdq_init(void) | |
922 | { | |
923 | (void) platform_device_register(&omap_hdq_dev); | |
924 | } | |
925 | #else | |
926 | static inline void omap_hdq_init(void) {} | |
927 | #endif | |
928 | ||
b227358d VH |
929 | /*---------------------------------------------------------------------------*/ |
930 | ||
931 | #if defined(CONFIG_VIDEO_OMAP2_VOUT) || \ | |
932 | defined(CONFIG_VIDEO_OMAP2_VOUT_MODULE) | |
933 | #if defined(CONFIG_FB_OMAP2) || defined(CONFIG_FB_OMAP2_MODULE) | |
934 | static struct resource omap_vout_resource[3 - CONFIG_FB_OMAP2_NUM_FBS] = { | |
935 | }; | |
936 | #else | |
937 | static struct resource omap_vout_resource[2] = { | |
938 | }; | |
939 | #endif | |
940 | ||
941 | static struct platform_device omap_vout_device = { | |
942 | .name = "omap_vout", | |
943 | .num_resources = ARRAY_SIZE(omap_vout_resource), | |
944 | .resource = &omap_vout_resource[0], | |
945 | .id = -1, | |
946 | }; | |
947 | static void omap_init_vout(void) | |
948 | { | |
949 | if (platform_device_register(&omap_vout_device) < 0) | |
950 | printk(KERN_ERR "Unable to register OMAP-VOUT device\n"); | |
951 | } | |
952 | #else | |
953 | static inline void omap_init_vout(void) {} | |
954 | #endif | |
955 | ||
1dbae815 TL |
956 | /*-------------------------------------------------------------------------*/ |
957 | ||
958 | static int __init omap2_init_devices(void) | |
959 | { | |
81fbc5ef PW |
960 | /* |
961 | * please keep these calls, and their implementations above, | |
1dbae815 TL |
962 | * in alphabetical order so they're easier to sort through. |
963 | */ | |
917fa280 | 964 | omap_hsmmc_reset(); |
f0fba2ad | 965 | omap_init_audio(); |
828c707e | 966 | omap_init_camera(); |
c40fae95 | 967 | omap_init_mbox(); |
ed7eb9d9 | 968 | omap_init_mcspi(); |
88341334 | 969 | omap_init_pmu(); |
646e3ed1 | 970 | omap_hdq_init(); |
9b6553cd | 971 | omap_init_sti(); |
ee5500c4 | 972 | omap_init_sham(); |
b744c679 | 973 | omap_init_aes(); |
b227358d | 974 | omap_init_vout(); |
1dbae815 TL |
975 | |
976 | return 0; | |
977 | } | |
978 | arch_initcall(omap2_init_devices); | |
f2ce6231 VC |
979 | |
980 | #if defined(CONFIG_OMAP_WATCHDOG) || defined(CONFIG_OMAP_WATCHDOG_MODULE) | |
a9b365bd | 981 | static struct omap_device_pm_latency omap_wdt_latency[] = { |
f2ce6231 VC |
982 | [0] = { |
983 | .deactivate_func = omap_device_idle_hwmods, | |
984 | .activate_func = omap_device_enable_hwmods, | |
985 | .flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST, | |
986 | }, | |
987 | }; | |
988 | ||
989 | static int __init omap_init_wdt(void) | |
990 | { | |
991 | int id = -1; | |
992 | struct omap_device *od; | |
993 | struct omap_hwmod *oh; | |
994 | char *oh_name = "wd_timer2"; | |
995 | char *dev_name = "omap_wdt"; | |
996 | ||
997 | if (!cpu_class_is_omap2()) | |
998 | return 0; | |
999 | ||
1000 | oh = omap_hwmod_lookup(oh_name); | |
1001 | if (!oh) { | |
1002 | pr_err("Could not look up wd_timer%d hwmod\n", id); | |
1003 | return -EINVAL; | |
1004 | } | |
1005 | ||
1006 | od = omap_device_build(dev_name, id, oh, NULL, 0, | |
1007 | omap_wdt_latency, | |
1008 | ARRAY_SIZE(omap_wdt_latency), 0); | |
1009 | WARN(IS_ERR(od), "Cant build omap_device for %s:%s.\n", | |
1010 | dev_name, oh->name); | |
1011 | return 0; | |
1012 | } | |
1013 | subsys_initcall(omap_init_wdt); | |
1014 | #endif |