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1dbae815 TL |
1 | /* |
2 | * linux/arch/arm/mach-omap2/devices.c | |
3 | * | |
4 | * OMAP2 platform device setup/initialization | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License, or | |
9 | * (at your option) any later version. | |
10 | */ | |
11 | ||
1dbae815 TL |
12 | #include <linux/kernel.h> |
13 | #include <linux/init.h> | |
14 | #include <linux/platform_device.h> | |
fced80c7 | 15 | #include <linux/io.h> |
917fa280 | 16 | #include <linux/clk.h> |
f2ce6231 | 17 | #include <linux/err.h> |
1a5d8190 | 18 | #include <linux/slab.h> |
1dbae815 | 19 | |
a09e64fb | 20 | #include <mach/hardware.h> |
88341334 | 21 | #include <mach/irqs.h> |
1dbae815 TL |
22 | #include <asm/mach-types.h> |
23 | #include <asm/mach/map.h> | |
88341334 | 24 | #include <asm/pmu.h> |
1dbae815 | 25 | |
ce491cf8 TL |
26 | #include <plat/tc.h> |
27 | #include <plat/board.h> | |
a09f73fa | 28 | #include <plat/mcbsp.h> |
a09e64fb | 29 | #include <mach/gpio.h> |
ce491cf8 | 30 | #include <plat/mmc.h> |
ee5500c4 | 31 | #include <plat/dma.h> |
f2ce6231 VC |
32 | #include <plat/omap_hwmod.h> |
33 | #include <plat/omap_device.h> | |
59556765 | 34 | #include <plat/omap4-keypad.h> |
1dbae815 | 35 | |
4896e394 | 36 | #include "mux.h" |
4814ced5 | 37 | #include "control.h" |
4896e394 | 38 | |
828c707e | 39 | #if defined(CONFIG_VIDEO_OMAP2) || defined(CONFIG_VIDEO_OMAP2_MODULE) |
c40fae95 | 40 | |
828c707e | 41 | static struct resource cam_resources[] = { |
c40fae95 | 42 | { |
828c707e TL |
43 | .start = OMAP24XX_CAMERA_BASE, |
44 | .end = OMAP24XX_CAMERA_BASE + 0xfff, | |
45 | .flags = IORESOURCE_MEM, | |
46 | }, | |
47 | { | |
48 | .start = INT_24XX_CAM_IRQ, | |
49 | .flags = IORESOURCE_IRQ, | |
50 | } | |
51 | }; | |
52 | ||
53 | static struct platform_device omap_cam_device = { | |
54 | .name = "omap24xxcam", | |
55 | .id = -1, | |
56 | .num_resources = ARRAY_SIZE(cam_resources), | |
57 | .resource = cam_resources, | |
58 | }; | |
59 | ||
60 | static inline void omap_init_camera(void) | |
61 | { | |
62 | platform_device_register(&omap_cam_device); | |
63 | } | |
64 | ||
65 | #elif defined(CONFIG_VIDEO_OMAP3) || defined(CONFIG_VIDEO_OMAP3_MODULE) | |
66 | ||
67 | static struct resource omap3isp_resources[] = { | |
68 | { | |
69 | .start = OMAP3430_ISP_BASE, | |
70 | .end = OMAP3430_ISP_END, | |
71 | .flags = IORESOURCE_MEM, | |
72 | }, | |
73 | { | |
74 | .start = OMAP3430_ISP_CBUFF_BASE, | |
75 | .end = OMAP3430_ISP_CBUFF_END, | |
76 | .flags = IORESOURCE_MEM, | |
77 | }, | |
78 | { | |
79 | .start = OMAP3430_ISP_CCP2_BASE, | |
80 | .end = OMAP3430_ISP_CCP2_END, | |
81 | .flags = IORESOURCE_MEM, | |
82 | }, | |
83 | { | |
84 | .start = OMAP3430_ISP_CCDC_BASE, | |
85 | .end = OMAP3430_ISP_CCDC_END, | |
86 | .flags = IORESOURCE_MEM, | |
87 | }, | |
88 | { | |
89 | .start = OMAP3430_ISP_HIST_BASE, | |
90 | .end = OMAP3430_ISP_HIST_END, | |
91 | .flags = IORESOURCE_MEM, | |
92 | }, | |
93 | { | |
94 | .start = OMAP3430_ISP_H3A_BASE, | |
95 | .end = OMAP3430_ISP_H3A_END, | |
96 | .flags = IORESOURCE_MEM, | |
97 | }, | |
98 | { | |
99 | .start = OMAP3430_ISP_PREV_BASE, | |
100 | .end = OMAP3430_ISP_PREV_END, | |
101 | .flags = IORESOURCE_MEM, | |
102 | }, | |
103 | { | |
104 | .start = OMAP3430_ISP_RESZ_BASE, | |
105 | .end = OMAP3430_ISP_RESZ_END, | |
106 | .flags = IORESOURCE_MEM, | |
107 | }, | |
108 | { | |
109 | .start = OMAP3430_ISP_SBL_BASE, | |
110 | .end = OMAP3430_ISP_SBL_END, | |
111 | .flags = IORESOURCE_MEM, | |
112 | }, | |
113 | { | |
114 | .start = OMAP3430_ISP_CSI2A_BASE, | |
115 | .end = OMAP3430_ISP_CSI2A_END, | |
116 | .flags = IORESOURCE_MEM, | |
117 | }, | |
118 | { | |
119 | .start = OMAP3430_ISP_CSI2PHY_BASE, | |
120 | .end = OMAP3430_ISP_CSI2PHY_END, | |
121 | .flags = IORESOURCE_MEM, | |
122 | }, | |
123 | { | |
124 | .start = INT_34XX_CAM_IRQ, | |
125 | .flags = IORESOURCE_IRQ, | |
126 | } | |
127 | }; | |
128 | ||
129 | static struct platform_device omap3isp_device = { | |
130 | .name = "omap3isp", | |
131 | .id = -1, | |
132 | .num_resources = ARRAY_SIZE(omap3isp_resources), | |
133 | .resource = omap3isp_resources, | |
134 | }; | |
135 | ||
136 | static inline void omap_init_camera(void) | |
137 | { | |
138 | platform_device_register(&omap3isp_device); | |
139 | } | |
140 | #else | |
141 | static inline void omap_init_camera(void) | |
142 | { | |
143 | } | |
144 | #endif | |
145 | ||
59556765 SR |
146 | struct omap_device_pm_latency omap_keyboard_latency[] = { |
147 | { | |
148 | .deactivate_func = omap_device_idle_hwmods, | |
149 | .activate_func = omap_device_enable_hwmods, | |
150 | .flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST, | |
151 | }, | |
152 | }; | |
153 | ||
154 | int __init omap4_keyboard_init(struct omap4_keypad_platform_data | |
155 | *sdp4430_keypad_data) | |
156 | { | |
157 | struct omap_device *od; | |
158 | struct omap_hwmod *oh; | |
159 | struct omap4_keypad_platform_data *keypad_data; | |
160 | unsigned int id = -1; | |
161 | char *oh_name = "kbd"; | |
162 | char *name = "omap4-keypad"; | |
163 | ||
164 | oh = omap_hwmod_lookup(oh_name); | |
165 | if (!oh) { | |
166 | pr_err("Could not look up %s\n", oh_name); | |
167 | return -ENODEV; | |
168 | } | |
169 | ||
170 | keypad_data = sdp4430_keypad_data; | |
171 | ||
172 | od = omap_device_build(name, id, oh, keypad_data, | |
173 | sizeof(struct omap4_keypad_platform_data), | |
174 | omap_keyboard_latency, | |
175 | ARRAY_SIZE(omap_keyboard_latency), 0); | |
176 | ||
177 | if (IS_ERR(od)) { | |
178 | WARN(1, "Cant build omap_device for %s:%s.\n", | |
179 | name, oh->name); | |
180 | return PTR_ERR(od); | |
181 | } | |
182 | ||
183 | return 0; | |
184 | } | |
185 | ||
6c20a683 | 186 | #if defined(CONFIG_OMAP_MBOX_FWK) || defined(CONFIG_OMAP_MBOX_FWK_MODULE) |
c40fae95 | 187 | |
454bf340 | 188 | #define MBOX_REG_SIZE 0x120 |
6c20a683 | 189 | |
454bf340 | 190 | #ifdef CONFIG_ARCH_OMAP2 |
d10f2b6e | 191 | static struct resource omap2_mbox_resources[] = { |
c40fae95 | 192 | { |
6c20a683 HD |
193 | .start = OMAP24XX_MAILBOX_BASE, |
194 | .end = OMAP24XX_MAILBOX_BASE + MBOX_REG_SIZE - 1, | |
c40fae95 TL |
195 | .flags = IORESOURCE_MEM, |
196 | }, | |
197 | { | |
198 | .start = INT_24XX_MAIL_U0_MPU, | |
199 | .flags = IORESOURCE_IRQ, | |
1f2c4dfd | 200 | .name = "dsp", |
c40fae95 TL |
201 | }, |
202 | { | |
203 | .start = INT_24XX_MAIL_U3_MPU, | |
204 | .flags = IORESOURCE_IRQ, | |
1f2c4dfd | 205 | .name = "iva", |
c40fae95 TL |
206 | }, |
207 | }; | |
d10f2b6e TL |
208 | static int omap2_mbox_resources_sz = ARRAY_SIZE(omap2_mbox_resources); |
209 | #else | |
210 | #define omap2_mbox_resources NULL | |
211 | #define omap2_mbox_resources_sz 0 | |
454bf340 | 212 | #endif |
c40fae95 | 213 | |
454bf340 | 214 | #ifdef CONFIG_ARCH_OMAP3 |
d10f2b6e | 215 | static struct resource omap3_mbox_resources[] = { |
6c20a683 HD |
216 | { |
217 | .start = OMAP34XX_MAILBOX_BASE, | |
218 | .end = OMAP34XX_MAILBOX_BASE + MBOX_REG_SIZE - 1, | |
219 | .flags = IORESOURCE_MEM, | |
220 | }, | |
221 | { | |
222 | .start = INT_24XX_MAIL_U0_MPU, | |
223 | .flags = IORESOURCE_IRQ, | |
1f2c4dfd | 224 | .name = "dsp", |
6c20a683 HD |
225 | }, |
226 | }; | |
d10f2b6e TL |
227 | static int omap3_mbox_resources_sz = ARRAY_SIZE(omap3_mbox_resources); |
228 | #else | |
229 | #define omap3_mbox_resources NULL | |
230 | #define omap3_mbox_resources_sz 0 | |
454bf340 S |
231 | #endif |
232 | ||
233 | #ifdef CONFIG_ARCH_OMAP4 | |
234 | ||
235 | #define OMAP4_MBOX_REG_SIZE 0x130 | |
d10f2b6e | 236 | static struct resource omap4_mbox_resources[] = { |
454bf340 S |
237 | { |
238 | .start = OMAP44XX_MAILBOX_BASE, | |
239 | .end = OMAP44XX_MAILBOX_BASE + | |
240 | OMAP4_MBOX_REG_SIZE - 1, | |
241 | .flags = IORESOURCE_MEM, | |
242 | }, | |
243 | { | |
5772ca7d | 244 | .start = OMAP44XX_IRQ_MAIL_U0, |
454bf340 | 245 | .flags = IORESOURCE_IRQ, |
1f2c4dfd | 246 | .name = "mbox", |
454bf340 S |
247 | }, |
248 | }; | |
d10f2b6e TL |
249 | static int omap4_mbox_resources_sz = ARRAY_SIZE(omap4_mbox_resources); |
250 | #else | |
251 | #define omap4_mbox_resources NULL | |
252 | #define omap4_mbox_resources_sz 0 | |
454bf340 | 253 | #endif |
6c20a683 | 254 | |
c40fae95 | 255 | static struct platform_device mbox_device = { |
d742709e | 256 | .name = "omap-mailbox", |
c40fae95 | 257 | .id = -1, |
c40fae95 TL |
258 | }; |
259 | ||
260 | static inline void omap_init_mbox(void) | |
261 | { | |
d10f2b6e TL |
262 | if (cpu_is_omap24xx()) { |
263 | mbox_device.resource = omap2_mbox_resources; | |
264 | mbox_device.num_resources = omap2_mbox_resources_sz; | |
265 | } else if (cpu_is_omap34xx()) { | |
266 | mbox_device.resource = omap3_mbox_resources; | |
267 | mbox_device.num_resources = omap3_mbox_resources_sz; | |
268 | } else if (cpu_is_omap44xx()) { | |
269 | mbox_device.resource = omap4_mbox_resources; | |
270 | mbox_device.num_resources = omap4_mbox_resources_sz; | |
6c20a683 HD |
271 | } else { |
272 | pr_err("%s: platform not supported\n", __func__); | |
273 | return; | |
274 | } | |
c40fae95 TL |
275 | platform_device_register(&mbox_device); |
276 | } | |
277 | #else | |
278 | static inline void omap_init_mbox(void) { } | |
6c20a683 | 279 | #endif /* CONFIG_OMAP_MBOX_FWK */ |
c40fae95 | 280 | |
9b6553cd | 281 | static inline void omap_init_sti(void) {} |
9b6553cd | 282 | |
f0fba2ad LG |
283 | #if defined(CONFIG_SND_SOC) || defined(CONFIG_SND_SOC_MODULE) |
284 | ||
285 | static struct platform_device omap_pcm = { | |
286 | .name = "omap-pcm-audio", | |
287 | .id = -1, | |
288 | }; | |
289 | ||
290 | /* | |
291 | * OMAP2420 has 2 McBSP ports | |
292 | * OMAP2430 has 5 McBSP ports | |
293 | * OMAP3 has 5 McBSP ports | |
294 | * OMAP4 has 4 McBSP ports | |
295 | */ | |
296 | OMAP_MCBSP_PLATFORM_DEVICE(1); | |
297 | OMAP_MCBSP_PLATFORM_DEVICE(2); | |
298 | OMAP_MCBSP_PLATFORM_DEVICE(3); | |
299 | OMAP_MCBSP_PLATFORM_DEVICE(4); | |
300 | OMAP_MCBSP_PLATFORM_DEVICE(5); | |
301 | ||
302 | static void omap_init_audio(void) | |
303 | { | |
304 | platform_device_register(&omap_mcbsp1); | |
305 | platform_device_register(&omap_mcbsp2); | |
306 | if (cpu_is_omap243x() || cpu_is_omap34xx() || cpu_is_omap44xx()) { | |
307 | platform_device_register(&omap_mcbsp3); | |
308 | platform_device_register(&omap_mcbsp4); | |
309 | } | |
310 | if (cpu_is_omap243x() || cpu_is_omap34xx()) | |
311 | platform_device_register(&omap_mcbsp5); | |
312 | ||
313 | platform_device_register(&omap_pcm); | |
314 | } | |
315 | ||
316 | #else | |
317 | static inline void omap_init_audio(void) {} | |
318 | #endif | |
319 | ||
646e3ed1 | 320 | #if defined(CONFIG_SPI_OMAP24XX) || defined(CONFIG_SPI_OMAP24XX_MODULE) |
ed7eb9d9 | 321 | |
ce491cf8 | 322 | #include <plat/mcspi.h> |
ed7eb9d9 | 323 | |
1a5d8190 C |
324 | struct omap_device_pm_latency omap_mcspi_latency[] = { |
325 | [0] = { | |
326 | .deactivate_func = omap_device_idle_hwmods, | |
327 | .activate_func = omap_device_enable_hwmods, | |
328 | .flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST, | |
646e3ed1 TL |
329 | }, |
330 | }; | |
646e3ed1 | 331 | |
1a5d8190 | 332 | static int omap_mcspi_init(struct omap_hwmod *oh, void *unused) |
af41a12f | 333 | { |
1a5d8190 C |
334 | struct omap_device *od; |
335 | char *name = "omap2_mcspi"; | |
336 | struct omap2_mcspi_platform_config *pdata; | |
337 | static int spi_num; | |
338 | struct omap2_mcspi_dev_attr *mcspi_attrib = oh->dev_attr; | |
339 | ||
340 | pdata = kzalloc(sizeof(*pdata), GFP_KERNEL); | |
341 | if (!pdata) { | |
342 | pr_err("Memory allocation for McSPI device failed\n"); | |
343 | return -ENOMEM; | |
344 | } | |
af41a12f | 345 | |
1a5d8190 C |
346 | pdata->num_cs = mcspi_attrib->num_chipselect; |
347 | switch (oh->class->rev) { | |
348 | case OMAP2_MCSPI_REV: | |
349 | case OMAP3_MCSPI_REV: | |
350 | pdata->regs_offset = 0; | |
351 | break; | |
352 | case OMAP4_MCSPI_REV: | |
353 | pdata->regs_offset = OMAP4_MCSPI_REG_OFFSET; | |
354 | break; | |
355 | default: | |
356 | pr_err("Invalid McSPI Revision value\n"); | |
357 | return -EINVAL; | |
358 | } | |
af41a12f | 359 | |
1a5d8190 C |
360 | spi_num++; |
361 | od = omap_device_build(name, spi_num, oh, pdata, | |
362 | sizeof(*pdata), omap_mcspi_latency, | |
363 | ARRAY_SIZE(omap_mcspi_latency), 0); | |
364 | WARN(IS_ERR(od), "Cant build omap_device for %s:%s\n", | |
365 | name, oh->name); | |
366 | kfree(pdata); | |
367 | return 0; | |
af41a12f | 368 | } |
af41a12f TL |
369 | |
370 | static void omap_init_mcspi(void) | |
371 | { | |
1a5d8190 | 372 | omap_hwmod_for_each_by_class("mcspi", omap_mcspi_init, NULL); |
ed7eb9d9 JY |
373 | } |
374 | ||
375 | #else | |
376 | static inline void omap_init_mcspi(void) {} | |
377 | #endif | |
378 | ||
88341334 WD |
379 | static struct resource omap2_pmu_resource = { |
380 | .start = 3, | |
381 | .end = 3, | |
382 | .flags = IORESOURCE_IRQ, | |
383 | }; | |
384 | ||
385 | static struct resource omap3_pmu_resource = { | |
386 | .start = INT_34XX_BENCH_MPU_EMUL, | |
387 | .end = INT_34XX_BENCH_MPU_EMUL, | |
388 | .flags = IORESOURCE_IRQ, | |
389 | }; | |
390 | ||
391 | static struct platform_device omap_pmu_device = { | |
392 | .name = "arm-pmu", | |
393 | .id = ARM_PMU_DEVICE_CPU, | |
394 | .num_resources = 1, | |
395 | }; | |
396 | ||
397 | static void omap_init_pmu(void) | |
398 | { | |
399 | if (cpu_is_omap24xx()) | |
400 | omap_pmu_device.resource = &omap2_pmu_resource; | |
401 | else if (cpu_is_omap34xx()) | |
402 | omap_pmu_device.resource = &omap3_pmu_resource; | |
403 | else | |
404 | return; | |
405 | ||
406 | platform_device_register(&omap_pmu_device); | |
407 | } | |
408 | ||
409 | ||
ee5500c4 DK |
410 | #if defined(CONFIG_CRYPTO_DEV_OMAP_SHAM) || defined(CONFIG_CRYPTO_DEV_OMAP_SHAM_MODULE) |
411 | ||
edc774ed | 412 | #ifdef CONFIG_ARCH_OMAP2 |
ee5500c4 | 413 | static struct resource omap2_sham_resources[] = { |
646e3ed1 TL |
414 | { |
415 | .start = OMAP24XX_SEC_SHA1MD5_BASE, | |
416 | .end = OMAP24XX_SEC_SHA1MD5_BASE + 0x64, | |
417 | .flags = IORESOURCE_MEM, | |
418 | }, | |
419 | { | |
420 | .start = INT_24XX_SHA1MD5, | |
421 | .flags = IORESOURCE_IRQ, | |
422 | } | |
423 | }; | |
ee5500c4 DK |
424 | static int omap2_sham_resources_sz = ARRAY_SIZE(omap2_sham_resources); |
425 | #else | |
426 | #define omap2_sham_resources NULL | |
427 | #define omap2_sham_resources_sz 0 | |
428 | #endif | |
646e3ed1 | 429 | |
edc774ed | 430 | #ifdef CONFIG_ARCH_OMAP3 |
ee5500c4 DK |
431 | static struct resource omap3_sham_resources[] = { |
432 | { | |
433 | .start = OMAP34XX_SEC_SHA1MD5_BASE, | |
434 | .end = OMAP34XX_SEC_SHA1MD5_BASE + 0x64, | |
435 | .flags = IORESOURCE_MEM, | |
436 | }, | |
437 | { | |
438 | .start = INT_34XX_SHA1MD52_IRQ, | |
439 | .flags = IORESOURCE_IRQ, | |
440 | }, | |
441 | { | |
442 | .start = OMAP34XX_DMA_SHA1MD5_RX, | |
443 | .flags = IORESOURCE_DMA, | |
444 | } | |
445 | }; | |
446 | static int omap3_sham_resources_sz = ARRAY_SIZE(omap3_sham_resources); | |
447 | #else | |
448 | #define omap3_sham_resources NULL | |
449 | #define omap3_sham_resources_sz 0 | |
450 | #endif | |
451 | ||
452 | static struct platform_device sham_device = { | |
453 | .name = "omap-sham", | |
646e3ed1 | 454 | .id = -1, |
646e3ed1 TL |
455 | }; |
456 | ||
ee5500c4 | 457 | static void omap_init_sham(void) |
646e3ed1 | 458 | { |
ee5500c4 DK |
459 | if (cpu_is_omap24xx()) { |
460 | sham_device.resource = omap2_sham_resources; | |
461 | sham_device.num_resources = omap2_sham_resources_sz; | |
462 | } else if (cpu_is_omap34xx()) { | |
463 | sham_device.resource = omap3_sham_resources; | |
464 | sham_device.num_resources = omap3_sham_resources_sz; | |
465 | } else { | |
466 | pr_err("%s: platform not supported\n", __func__); | |
467 | return; | |
468 | } | |
469 | platform_device_register(&sham_device); | |
646e3ed1 TL |
470 | } |
471 | #else | |
ee5500c4 | 472 | static inline void omap_init_sham(void) { } |
646e3ed1 TL |
473 | #endif |
474 | ||
b744c679 DK |
475 | #if defined(CONFIG_CRYPTO_DEV_OMAP_AES) || defined(CONFIG_CRYPTO_DEV_OMAP_AES_MODULE) |
476 | ||
82a0c149 | 477 | #ifdef CONFIG_ARCH_OMAP2 |
b744c679 DK |
478 | static struct resource omap2_aes_resources[] = { |
479 | { | |
480 | .start = OMAP24XX_SEC_AES_BASE, | |
481 | .end = OMAP24XX_SEC_AES_BASE + 0x4C, | |
482 | .flags = IORESOURCE_MEM, | |
483 | }, | |
484 | { | |
485 | .start = OMAP24XX_DMA_AES_TX, | |
486 | .flags = IORESOURCE_DMA, | |
487 | }, | |
488 | { | |
489 | .start = OMAP24XX_DMA_AES_RX, | |
490 | .flags = IORESOURCE_DMA, | |
491 | } | |
492 | }; | |
493 | static int omap2_aes_resources_sz = ARRAY_SIZE(omap2_aes_resources); | |
494 | #else | |
495 | #define omap2_aes_resources NULL | |
496 | #define omap2_aes_resources_sz 0 | |
497 | #endif | |
498 | ||
82a0c149 | 499 | #ifdef CONFIG_ARCH_OMAP3 |
b744c679 DK |
500 | static struct resource omap3_aes_resources[] = { |
501 | { | |
502 | .start = OMAP34XX_SEC_AES_BASE, | |
503 | .end = OMAP34XX_SEC_AES_BASE + 0x4C, | |
504 | .flags = IORESOURCE_MEM, | |
505 | }, | |
506 | { | |
507 | .start = OMAP34XX_DMA_AES2_TX, | |
508 | .flags = IORESOURCE_DMA, | |
509 | }, | |
510 | { | |
511 | .start = OMAP34XX_DMA_AES2_RX, | |
512 | .flags = IORESOURCE_DMA, | |
513 | } | |
514 | }; | |
515 | static int omap3_aes_resources_sz = ARRAY_SIZE(omap3_aes_resources); | |
516 | #else | |
517 | #define omap3_aes_resources NULL | |
518 | #define omap3_aes_resources_sz 0 | |
519 | #endif | |
520 | ||
521 | static struct platform_device aes_device = { | |
522 | .name = "omap-aes", | |
523 | .id = -1, | |
524 | }; | |
525 | ||
526 | static void omap_init_aes(void) | |
527 | { | |
528 | if (cpu_is_omap24xx()) { | |
529 | aes_device.resource = omap2_aes_resources; | |
530 | aes_device.num_resources = omap2_aes_resources_sz; | |
531 | } else if (cpu_is_omap34xx()) { | |
532 | aes_device.resource = omap3_aes_resources; | |
533 | aes_device.num_resources = omap3_aes_resources_sz; | |
534 | } else { | |
535 | pr_err("%s: platform not supported\n", __func__); | |
536 | return; | |
537 | } | |
538 | platform_device_register(&aes_device); | |
539 | } | |
540 | ||
541 | #else | |
542 | static inline void omap_init_aes(void) { } | |
543 | #endif | |
544 | ||
d8874665 TL |
545 | /*-------------------------------------------------------------------------*/ |
546 | ||
82cf818d | 547 | #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4) |
917fa280 KH |
548 | |
549 | #define MMCHS_SYSCONFIG 0x0010 | |
550 | #define MMCHS_SYSCONFIG_SWRESET (1 << 1) | |
551 | #define MMCHS_SYSSTATUS 0x0014 | |
552 | #define MMCHS_SYSSTATUS_RESETDONE (1 << 0) | |
553 | ||
554 | static struct platform_device dummy_pdev = { | |
555 | .dev = { | |
556 | .bus = &platform_bus_type, | |
557 | }, | |
558 | }; | |
559 | ||
560 | /** | |
561 | * omap_hsmmc_reset() - Full reset of each HS-MMC controller | |
562 | * | |
563 | * Ensure that each MMC controller is fully reset. Controllers | |
564 | * left in an unknown state (by bootloader) may prevent retention | |
565 | * or OFF-mode. This is especially important in cases where the | |
566 | * MMC driver is not enabled, _or_ built as a module. | |
567 | * | |
568 | * In order for reset to work, interface, functional and debounce | |
569 | * clocks must be enabled. The debounce clock comes from func_32k_clk | |
570 | * and is not under SW control, so we only enable i- and f-clocks. | |
571 | **/ | |
572 | static void __init omap_hsmmc_reset(void) | |
573 | { | |
4323e9f7 | 574 | u32 i, nr_controllers; |
434c23a7 | 575 | struct clk *iclk, *fclk; |
4323e9f7 TL |
576 | |
577 | if (cpu_is_omap242x()) | |
578 | return; | |
579 | ||
580 | nr_controllers = cpu_is_omap44xx() ? OMAP44XX_NR_MMC : | |
82cf818d | 581 | (cpu_is_omap34xx() ? OMAP34XX_NR_MMC : OMAP24XX_NR_MMC); |
917fa280 KH |
582 | |
583 | for (i = 0; i < nr_controllers; i++) { | |
584 | u32 v, base = 0; | |
917fa280 KH |
585 | struct device *dev = &dummy_pdev.dev; |
586 | ||
587 | switch (i) { | |
588 | case 0: | |
589 | base = OMAP2_MMC1_BASE; | |
590 | break; | |
591 | case 1: | |
592 | base = OMAP2_MMC2_BASE; | |
593 | break; | |
594 | case 2: | |
595 | base = OMAP3_MMC3_BASE; | |
596 | break; | |
82cf818d | 597 | case 3: |
598 | if (!cpu_is_omap44xx()) | |
599 | return; | |
600 | base = OMAP4_MMC4_BASE; | |
601 | break; | |
602 | case 4: | |
603 | if (!cpu_is_omap44xx()) | |
604 | return; | |
605 | base = OMAP4_MMC5_BASE; | |
606 | break; | |
917fa280 KH |
607 | } |
608 | ||
82cf818d | 609 | if (cpu_is_omap44xx()) |
610 | base += OMAP4_MMC_REG_OFFSET; | |
611 | ||
917fa280 | 612 | dummy_pdev.id = i; |
1e98ffa8 | 613 | dev_set_name(&dummy_pdev.dev, "mmci-omap-hs.%d", i); |
6f7607cc | 614 | iclk = clk_get(dev, "ick"); |
434c23a7 AK |
615 | if (IS_ERR(iclk)) |
616 | goto err1; | |
617 | if (clk_enable(iclk)) | |
618 | goto err2; | |
917fa280 | 619 | |
6f7607cc | 620 | fclk = clk_get(dev, "fck"); |
434c23a7 AK |
621 | if (IS_ERR(fclk)) |
622 | goto err3; | |
623 | if (clk_enable(fclk)) | |
624 | goto err4; | |
917fa280 KH |
625 | |
626 | omap_writel(MMCHS_SYSCONFIG_SWRESET, base + MMCHS_SYSCONFIG); | |
627 | v = omap_readl(base + MMCHS_SYSSTATUS); | |
628 | while (!(omap_readl(base + MMCHS_SYSSTATUS) & | |
629 | MMCHS_SYSSTATUS_RESETDONE)) | |
630 | cpu_relax(); | |
631 | ||
434c23a7 AK |
632 | clk_disable(fclk); |
633 | clk_put(fclk); | |
634 | clk_disable(iclk); | |
635 | clk_put(iclk); | |
917fa280 | 636 | } |
434c23a7 AK |
637 | return; |
638 | ||
639 | err4: | |
640 | clk_put(fclk); | |
641 | err3: | |
642 | clk_disable(iclk); | |
643 | err2: | |
644 | clk_put(iclk); | |
645 | err1: | |
646 | printk(KERN_WARNING "%s: Unable to enable clocks for MMC%d, " | |
647 | "cannot reset.\n", __func__, i); | |
917fa280 KH |
648 | } |
649 | #else | |
650 | static inline void omap_hsmmc_reset(void) {} | |
651 | #endif | |
652 | ||
d8874665 TL |
653 | #if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE) || \ |
654 | defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE) | |
655 | ||
656 | static inline void omap2_mmc_mux(struct omap_mmc_platform_data *mmc_controller, | |
657 | int controller_nr) | |
658 | { | |
ed8303fc | 659 | if ((mmc_controller->slots[0].switch_pin > 0) && \ |
660 | (mmc_controller->slots[0].switch_pin < OMAP_MAX_GPIO_LINES)) | |
661 | omap_mux_init_gpio(mmc_controller->slots[0].switch_pin, | |
662 | OMAP_PIN_INPUT_PULLUP); | |
663 | if ((mmc_controller->slots[0].gpio_wp > 0) && \ | |
664 | (mmc_controller->slots[0].gpio_wp < OMAP_MAX_GPIO_LINES)) | |
665 | omap_mux_init_gpio(mmc_controller->slots[0].gpio_wp, | |
666 | OMAP_PIN_INPUT_PULLUP); | |
667 | ||
d8874665 | 668 | if (cpu_is_omap2420() && controller_nr == 0) { |
f99bf16d TL |
669 | omap_mux_init_signal("sdmmc_cmd", 0); |
670 | omap_mux_init_signal("sdmmc_clki", 0); | |
671 | omap_mux_init_signal("sdmmc_clko", 0); | |
672 | omap_mux_init_signal("sdmmc_dat0", 0); | |
673 | omap_mux_init_signal("sdmmc_dat_dir0", 0); | |
674 | omap_mux_init_signal("sdmmc_cmd_dir", 0); | |
3a63833e | 675 | if (mmc_controller->slots[0].caps & MMC_CAP_4_BIT_DATA) { |
f99bf16d TL |
676 | omap_mux_init_signal("sdmmc_dat1", 0); |
677 | omap_mux_init_signal("sdmmc_dat2", 0); | |
678 | omap_mux_init_signal("sdmmc_dat3", 0); | |
679 | omap_mux_init_signal("sdmmc_dat_dir1", 0); | |
680 | omap_mux_init_signal("sdmmc_dat_dir2", 0); | |
681 | omap_mux_init_signal("sdmmc_dat_dir3", 0); | |
d8874665 TL |
682 | } |
683 | ||
684 | /* | |
685 | * Use internal loop-back in MMC/SDIO Module Input Clock | |
686 | * selection | |
687 | */ | |
688 | if (mmc_controller->slots[0].internal_clock) { | |
689 | u32 v = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0); | |
690 | v |= (1 << 24); | |
691 | omap_ctrl_writel(v, OMAP2_CONTROL_DEVCONF0); | |
692 | } | |
693 | } | |
57b9daa0 | 694 | |
4596d14a | 695 | if (cpu_is_omap34xx()) { |
57b9daa0 | 696 | if (controller_nr == 0) { |
4896e394 TL |
697 | omap_mux_init_signal("sdmmc1_clk", |
698 | OMAP_PIN_INPUT_PULLUP); | |
699 | omap_mux_init_signal("sdmmc1_cmd", | |
700 | OMAP_PIN_INPUT_PULLUP); | |
701 | omap_mux_init_signal("sdmmc1_dat0", | |
702 | OMAP_PIN_INPUT_PULLUP); | |
3a63833e SG |
703 | if (mmc_controller->slots[0].caps & |
704 | (MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA)) { | |
4896e394 TL |
705 | omap_mux_init_signal("sdmmc1_dat1", |
706 | OMAP_PIN_INPUT_PULLUP); | |
707 | omap_mux_init_signal("sdmmc1_dat2", | |
708 | OMAP_PIN_INPUT_PULLUP); | |
709 | omap_mux_init_signal("sdmmc1_dat3", | |
710 | OMAP_PIN_INPUT_PULLUP); | |
57b9daa0 | 711 | } |
3a63833e SG |
712 | if (mmc_controller->slots[0].caps & |
713 | MMC_CAP_8_BIT_DATA) { | |
4896e394 TL |
714 | omap_mux_init_signal("sdmmc1_dat4", |
715 | OMAP_PIN_INPUT_PULLUP); | |
716 | omap_mux_init_signal("sdmmc1_dat5", | |
717 | OMAP_PIN_INPUT_PULLUP); | |
718 | omap_mux_init_signal("sdmmc1_dat6", | |
719 | OMAP_PIN_INPUT_PULLUP); | |
720 | omap_mux_init_signal("sdmmc1_dat7", | |
721 | OMAP_PIN_INPUT_PULLUP); | |
57b9daa0 VP |
722 | } |
723 | } | |
724 | if (controller_nr == 1) { | |
725 | /* MMC2 */ | |
4896e394 TL |
726 | omap_mux_init_signal("sdmmc2_clk", |
727 | OMAP_PIN_INPUT_PULLUP); | |
728 | omap_mux_init_signal("sdmmc2_cmd", | |
729 | OMAP_PIN_INPUT_PULLUP); | |
730 | omap_mux_init_signal("sdmmc2_dat0", | |
731 | OMAP_PIN_INPUT_PULLUP); | |
57b9daa0 VP |
732 | |
733 | /* | |
734 | * For 8 wire configurations, Lines DAT4, 5, 6 and 7 need to be muxed | |
735 | * in the board-*.c files | |
736 | */ | |
3a63833e SG |
737 | if (mmc_controller->slots[0].caps & |
738 | (MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA)) { | |
4896e394 TL |
739 | omap_mux_init_signal("sdmmc2_dat1", |
740 | OMAP_PIN_INPUT_PULLUP); | |
741 | omap_mux_init_signal("sdmmc2_dat2", | |
742 | OMAP_PIN_INPUT_PULLUP); | |
743 | omap_mux_init_signal("sdmmc2_dat3", | |
744 | OMAP_PIN_INPUT_PULLUP); | |
57b9daa0 | 745 | } |
3a63833e SG |
746 | if (mmc_controller->slots[0].caps & |
747 | MMC_CAP_8_BIT_DATA) { | |
4896e394 TL |
748 | omap_mux_init_signal("sdmmc2_dat4.sdmmc2_dat4", |
749 | OMAP_PIN_INPUT_PULLUP); | |
750 | omap_mux_init_signal("sdmmc2_dat5.sdmmc2_dat5", | |
751 | OMAP_PIN_INPUT_PULLUP); | |
752 | omap_mux_init_signal("sdmmc2_dat6.sdmmc2_dat6", | |
753 | OMAP_PIN_INPUT_PULLUP); | |
754 | omap_mux_init_signal("sdmmc2_dat7.sdmmc2_dat7", | |
755 | OMAP_PIN_INPUT_PULLUP); | |
4679232d | 756 | } |
57b9daa0 VP |
757 | } |
758 | ||
759 | /* | |
760 | * For MMC3 the pins need to be muxed in the board-*.c files | |
761 | */ | |
762 | } | |
d8874665 TL |
763 | } |
764 | ||
765 | void __init omap2_init_mmc(struct omap_mmc_platform_data **mmc_data, | |
766 | int nr_controllers) | |
767 | { | |
768 | int i; | |
0dffb5c5 | 769 | char *name; |
d8874665 TL |
770 | |
771 | for (i = 0; i < nr_controllers; i++) { | |
772 | unsigned long base, size; | |
773 | unsigned int irq = 0; | |
774 | ||
775 | if (!mmc_data[i]) | |
776 | continue; | |
777 | ||
778 | omap2_mmc_mux(mmc_data[i], i); | |
779 | ||
780 | switch (i) { | |
781 | case 0: | |
782 | base = OMAP2_MMC1_BASE; | |
783 | irq = INT_24XX_MMC_IRQ; | |
784 | break; | |
785 | case 1: | |
786 | base = OMAP2_MMC2_BASE; | |
787 | irq = INT_24XX_MMC2_IRQ; | |
788 | break; | |
789 | case 2: | |
82cf818d | 790 | if (!cpu_is_omap44xx() && !cpu_is_omap34xx()) |
d8874665 TL |
791 | return; |
792 | base = OMAP3_MMC3_BASE; | |
793 | irq = INT_34XX_MMC3_IRQ; | |
794 | break; | |
82cf818d | 795 | case 3: |
796 | if (!cpu_is_omap44xx()) | |
797 | return; | |
91a0b089 | 798 | base = OMAP4_MMC4_BASE; |
5772ca7d | 799 | irq = OMAP44XX_IRQ_MMC4; |
82cf818d | 800 | break; |
801 | case 4: | |
802 | if (!cpu_is_omap44xx()) | |
803 | return; | |
91a0b089 | 804 | base = OMAP4_MMC5_BASE; |
9df76b7f | 805 | irq = OMAP44XX_IRQ_MMC5; |
82cf818d | 806 | break; |
d8874665 TL |
807 | default: |
808 | continue; | |
809 | } | |
810 | ||
0dffb5c5 | 811 | if (cpu_is_omap2420()) { |
d8874665 | 812 | size = OMAP2420_MMC_SIZE; |
0dffb5c5 | 813 | name = "mmci-omap"; |
82cf818d | 814 | } else if (cpu_is_omap44xx()) { |
91a0b089 | 815 | if (i < 3) |
5772ca7d | 816 | irq += OMAP44XX_IRQ_GIC_START; |
82cf818d | 817 | size = OMAP4_HSMMC_SIZE; |
818 | name = "mmci-omap-hs"; | |
0dffb5c5 | 819 | } else { |
82cf818d | 820 | size = OMAP3_HSMMC_SIZE; |
0dffb5c5 TL |
821 | name = "mmci-omap-hs"; |
822 | } | |
823 | omap_mmc_add(name, i, base, size, irq, mmc_data[i]); | |
d8874665 TL |
824 | }; |
825 | } | |
826 | ||
827 | #endif | |
828 | ||
829 | /*-------------------------------------------------------------------------*/ | |
830 | ||
646e3ed1 | 831 | #if defined(CONFIG_HDQ_MASTER_OMAP) || defined(CONFIG_HDQ_MASTER_OMAP_MODULE) |
59b479e0 | 832 | #if defined(CONFIG_SOC_OMAP2430) || defined(CONFIG_SOC_OMAP3430) |
646e3ed1 TL |
833 | #define OMAP_HDQ_BASE 0x480B2000 |
834 | #endif | |
835 | static struct resource omap_hdq_resources[] = { | |
836 | { | |
837 | .start = OMAP_HDQ_BASE, | |
838 | .end = OMAP_HDQ_BASE + 0x1C, | |
839 | .flags = IORESOURCE_MEM, | |
840 | }, | |
841 | { | |
842 | .start = INT_24XX_HDQ_IRQ, | |
843 | .flags = IORESOURCE_IRQ, | |
844 | }, | |
845 | }; | |
846 | static struct platform_device omap_hdq_dev = { | |
847 | .name = "omap_hdq", | |
848 | .id = 0, | |
849 | .dev = { | |
850 | .platform_data = NULL, | |
851 | }, | |
852 | .num_resources = ARRAY_SIZE(omap_hdq_resources), | |
853 | .resource = omap_hdq_resources, | |
854 | }; | |
855 | static inline void omap_hdq_init(void) | |
856 | { | |
857 | (void) platform_device_register(&omap_hdq_dev); | |
858 | } | |
859 | #else | |
860 | static inline void omap_hdq_init(void) {} | |
861 | #endif | |
862 | ||
b227358d VH |
863 | /*---------------------------------------------------------------------------*/ |
864 | ||
865 | #if defined(CONFIG_VIDEO_OMAP2_VOUT) || \ | |
866 | defined(CONFIG_VIDEO_OMAP2_VOUT_MODULE) | |
867 | #if defined(CONFIG_FB_OMAP2) || defined(CONFIG_FB_OMAP2_MODULE) | |
868 | static struct resource omap_vout_resource[3 - CONFIG_FB_OMAP2_NUM_FBS] = { | |
869 | }; | |
870 | #else | |
871 | static struct resource omap_vout_resource[2] = { | |
872 | }; | |
873 | #endif | |
874 | ||
875 | static struct platform_device omap_vout_device = { | |
876 | .name = "omap_vout", | |
877 | .num_resources = ARRAY_SIZE(omap_vout_resource), | |
878 | .resource = &omap_vout_resource[0], | |
879 | .id = -1, | |
880 | }; | |
881 | static void omap_init_vout(void) | |
882 | { | |
883 | if (platform_device_register(&omap_vout_device) < 0) | |
884 | printk(KERN_ERR "Unable to register OMAP-VOUT device\n"); | |
885 | } | |
886 | #else | |
887 | static inline void omap_init_vout(void) {} | |
888 | #endif | |
889 | ||
1dbae815 TL |
890 | /*-------------------------------------------------------------------------*/ |
891 | ||
892 | static int __init omap2_init_devices(void) | |
893 | { | |
81fbc5ef PW |
894 | /* |
895 | * please keep these calls, and their implementations above, | |
1dbae815 TL |
896 | * in alphabetical order so they're easier to sort through. |
897 | */ | |
917fa280 | 898 | omap_hsmmc_reset(); |
f0fba2ad | 899 | omap_init_audio(); |
828c707e | 900 | omap_init_camera(); |
c40fae95 | 901 | omap_init_mbox(); |
ed7eb9d9 | 902 | omap_init_mcspi(); |
88341334 | 903 | omap_init_pmu(); |
646e3ed1 | 904 | omap_hdq_init(); |
9b6553cd | 905 | omap_init_sti(); |
ee5500c4 | 906 | omap_init_sham(); |
b744c679 | 907 | omap_init_aes(); |
b227358d | 908 | omap_init_vout(); |
1dbae815 TL |
909 | |
910 | return 0; | |
911 | } | |
912 | arch_initcall(omap2_init_devices); | |
f2ce6231 VC |
913 | |
914 | #if defined(CONFIG_OMAP_WATCHDOG) || defined(CONFIG_OMAP_WATCHDOG_MODULE) | |
a9b365bd | 915 | static struct omap_device_pm_latency omap_wdt_latency[] = { |
f2ce6231 VC |
916 | [0] = { |
917 | .deactivate_func = omap_device_idle_hwmods, | |
918 | .activate_func = omap_device_enable_hwmods, | |
919 | .flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST, | |
920 | }, | |
921 | }; | |
922 | ||
923 | static int __init omap_init_wdt(void) | |
924 | { | |
925 | int id = -1; | |
926 | struct omap_device *od; | |
927 | struct omap_hwmod *oh; | |
928 | char *oh_name = "wd_timer2"; | |
929 | char *dev_name = "omap_wdt"; | |
930 | ||
931 | if (!cpu_class_is_omap2()) | |
932 | return 0; | |
933 | ||
934 | oh = omap_hwmod_lookup(oh_name); | |
935 | if (!oh) { | |
936 | pr_err("Could not look up wd_timer%d hwmod\n", id); | |
937 | return -EINVAL; | |
938 | } | |
939 | ||
940 | od = omap_device_build(dev_name, id, oh, NULL, 0, | |
941 | omap_wdt_latency, | |
942 | ARRAY_SIZE(omap_wdt_latency), 0); | |
943 | WARN(IS_ERR(od), "Cant build omap_device for %s:%s.\n", | |
944 | dev_name, oh->name); | |
945 | return 0; | |
946 | } | |
947 | subsys_initcall(omap_init_wdt); | |
948 | #endif |