projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
omap: mailbox: only compile for configured archs
[deliverable/linux.git] / arch / arm / mach-omap2 / devices.c
CommitLineData
1dbae815
TL		 1/*
2 * linux/arch/arm/mach-omap2/devices.c
3 *
4 * OMAP2 platform device setup/initialization
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 */
11
1dbae815
TL		 12#include <linux/module.h>
13#include <linux/kernel.h>
14#include <linux/init.h>
15#include <linux/platform_device.h>
fced80c7 16#include <linux/io.h>
917fa280 17#include <linux/clk.h>
1dbae815 18
a09e64fb 19#include <mach/hardware.h>
88341334 20#include <mach/irqs.h>
1dbae815
TL		 21#include <asm/mach-types.h>
22#include <asm/mach/map.h>
88341334 23#include <asm/pmu.h>
1dbae815 24
ce491cf8
TL		 25#include <plat/control.h>
26#include <plat/tc.h>
27#include <plat/board.h>
28#include <plat/mux.h>
a09e64fb 29#include <mach/gpio.h>
ce491cf8 30#include <plat/mmc.h>
ee5500c4 31#include <plat/dma.h>
1dbae815 32
4896e394
TL		 33#include "mux.h"
34
828c707e 35#if defined(CONFIG_VIDEO_OMAP2) || defined(CONFIG_VIDEO_OMAP2_MODULE)
c40fae95 36
828c707e 37static struct resource cam_resources[] = {
c40fae95 38 {
828c707e
TL		 39 .start = OMAP24XX_CAMERA_BASE,
40 .end = OMAP24XX_CAMERA_BASE + 0xfff,
41 .flags = IORESOURCE_MEM,
42 },
43 {
44 .start = INT_24XX_CAM_IRQ,
45 .flags = IORESOURCE_IRQ,
46 }
47};
48
49static struct platform_device omap_cam_device = {
50 .name = "omap24xxcam",
51 .id = -1,
52 .num_resources = ARRAY_SIZE(cam_resources),
53 .resource = cam_resources,
54};
55
56static inline void omap_init_camera(void)
57{
58 platform_device_register(&omap_cam_device);
59}
60
61#elif defined(CONFIG_VIDEO_OMAP3) || defined(CONFIG_VIDEO_OMAP3_MODULE)
62
63static struct resource omap3isp_resources[] = {
64 {
65 .start = OMAP3430_ISP_BASE,
66 .end = OMAP3430_ISP_END,
67 .flags = IORESOURCE_MEM,
68 },
69 {
70 .start = OMAP3430_ISP_CBUFF_BASE,
71 .end = OMAP3430_ISP_CBUFF_END,
72 .flags = IORESOURCE_MEM,
73 },
74 {
75 .start = OMAP3430_ISP_CCP2_BASE,
76 .end = OMAP3430_ISP_CCP2_END,
77 .flags = IORESOURCE_MEM,
78 },
79 {
80 .start = OMAP3430_ISP_CCDC_BASE,
81 .end = OMAP3430_ISP_CCDC_END,
82 .flags = IORESOURCE_MEM,
83 },
84 {
85 .start = OMAP3430_ISP_HIST_BASE,
86 .end = OMAP3430_ISP_HIST_END,
87 .flags = IORESOURCE_MEM,
88 },
89 {
90 .start = OMAP3430_ISP_H3A_BASE,
91 .end = OMAP3430_ISP_H3A_END,
92 .flags = IORESOURCE_MEM,
93 },
94 {
95 .start = OMAP3430_ISP_PREV_BASE,
96 .end = OMAP3430_ISP_PREV_END,
97 .flags = IORESOURCE_MEM,
98 },
99 {
100 .start = OMAP3430_ISP_RESZ_BASE,
101 .end = OMAP3430_ISP_RESZ_END,
102 .flags = IORESOURCE_MEM,
103 },
104 {
105 .start = OMAP3430_ISP_SBL_BASE,
106 .end = OMAP3430_ISP_SBL_END,
107 .flags = IORESOURCE_MEM,
108 },
109 {
110 .start = OMAP3430_ISP_CSI2A_BASE,
111 .end = OMAP3430_ISP_CSI2A_END,
112 .flags = IORESOURCE_MEM,
113 },
114 {
115 .start = OMAP3430_ISP_CSI2PHY_BASE,
116 .end = OMAP3430_ISP_CSI2PHY_END,
117 .flags = IORESOURCE_MEM,
118 },
119 {
120 .start = INT_34XX_CAM_IRQ,
121 .flags = IORESOURCE_IRQ,
122 }
123};
124
125static struct platform_device omap3isp_device = {
126 .name = "omap3isp",
127 .id = -1,
128 .num_resources = ARRAY_SIZE(omap3isp_resources),
129 .resource = omap3isp_resources,
130};
131
132static inline void omap_init_camera(void)
133{
134 platform_device_register(&omap3isp_device);
135}
136#else
137static inline void omap_init_camera(void)
138{
139}
140#endif
141
6c20a683 142#if defined(CONFIG_OMAP_MBOX_FWK) || defined(CONFIG_OMAP_MBOX_FWK_MODULE)
c40fae95 143
454bf340 144#define MBOX_REG_SIZE 0x120
6c20a683 145
454bf340 146#ifdef CONFIG_ARCH_OMAP2
d10f2b6e 147static struct resource omap2_mbox_resources[] = {
c40fae95 148 {
6c20a683
HD		 149 .start = OMAP24XX_MAILBOX_BASE,
150 .end = OMAP24XX_MAILBOX_BASE + MBOX_REG_SIZE - 1,
c40fae95
TL		 151 .flags = IORESOURCE_MEM,
152 },
153 {
154 .start = INT_24XX_MAIL_U0_MPU,
155 .flags = IORESOURCE_IRQ,
1f2c4dfd 156 .name = "dsp",
c40fae95
TL		 157 },
158 {
159 .start = INT_24XX_MAIL_U3_MPU,
160 .flags = IORESOURCE_IRQ,
1f2c4dfd 161 .name = "iva",
c40fae95
TL		 162 },
163};
d10f2b6e
TL		 164static int omap2_mbox_resources_sz = ARRAY_SIZE(omap2_mbox_resources);
165#else
166#define omap2_mbox_resources NULL
167#define omap2_mbox_resources_sz 0
454bf340 168#endif
c40fae95 169
454bf340 170#ifdef CONFIG_ARCH_OMAP3
d10f2b6e 171static struct resource omap3_mbox_resources[] = {
6c20a683
HD		 172 {
173 .start = OMAP34XX_MAILBOX_BASE,
174 .end = OMAP34XX_MAILBOX_BASE + MBOX_REG_SIZE - 1,
175 .flags = IORESOURCE_MEM,
176 },
177 {
178 .start = INT_24XX_MAIL_U0_MPU,
179 .flags = IORESOURCE_IRQ,
1f2c4dfd 180 .name = "dsp",
6c20a683
HD		 181 },
182};
d10f2b6e
TL		 183static int omap3_mbox_resources_sz = ARRAY_SIZE(omap3_mbox_resources);
184#else
185#define omap3_mbox_resources NULL
186#define omap3_mbox_resources_sz 0
454bf340
S		 187#endif
188
189#ifdef CONFIG_ARCH_OMAP4
190
191#define OMAP4_MBOX_REG_SIZE 0x130
d10f2b6e 192static struct resource omap4_mbox_resources[] = {
454bf340
S		 193 {
194 .start = OMAP44XX_MAILBOX_BASE,
195 .end = OMAP44XX_MAILBOX_BASE +
196 OMAP4_MBOX_REG_SIZE - 1,
197 .flags = IORESOURCE_MEM,
198 },
199 {
5772ca7d 200 .start = OMAP44XX_IRQ_MAIL_U0,
454bf340 201 .flags = IORESOURCE_IRQ,
1f2c4dfd 202 .name = "mbox",
454bf340
S		 203 },
204};
d10f2b6e
TL		 205static int omap4_mbox_resources_sz = ARRAY_SIZE(omap4_mbox_resources);
206#else
207#define omap4_mbox_resources NULL
208#define omap4_mbox_resources_sz 0
454bf340 209#endif
6c20a683 210
c40fae95 211static struct platform_device mbox_device = {
da8cfe03 212 .name = "omap2-mailbox",
c40fae95 213 .id = -1,
c40fae95
TL		 214};
215
216static inline void omap_init_mbox(void)
217{
d10f2b6e
TL		 218 if (cpu_is_omap24xx()) {
219 mbox_device.resource = omap2_mbox_resources;
220 mbox_device.num_resources = omap2_mbox_resources_sz;
221 } else if (cpu_is_omap34xx()) {
222 mbox_device.resource = omap3_mbox_resources;
223 mbox_device.num_resources = omap3_mbox_resources_sz;
224 } else if (cpu_is_omap44xx()) {
225 mbox_device.resource = omap4_mbox_resources;
226 mbox_device.num_resources = omap4_mbox_resources_sz;
6c20a683
HD		 227 } else {
228 pr_err("%s: platform not supported\n", __func__);
229 return;
230 }
c40fae95
TL		 231 platform_device_register(&mbox_device);
232}
233#else
234static inline void omap_init_mbox(void) { }
6c20a683 235#endif /* CONFIG_OMAP_MBOX_FWK */
c40fae95 236
9b6553cd
TL		 237#if defined(CONFIG_OMAP_STI)
238
646e3ed1
TL		 239#if defined(CONFIG_ARCH_OMAP2)
240
241#define OMAP2_STI_BASE 0x48068000
9b6553cd
TL		 242#define OMAP2_STI_CHANNEL_BASE 0x54000000
243#define OMAP2_STI_IRQ 4
244
245static struct resource sti_resources[] = {
246 {
247 .start = OMAP2_STI_BASE,
248 .end = OMAP2_STI_BASE + 0x7ff,
249 .flags = IORESOURCE_MEM,
250 },
251 {
252 .start = OMAP2_STI_CHANNEL_BASE,
253 .end = OMAP2_STI_CHANNEL_BASE + SZ_64K - 1,
254 .flags = IORESOURCE_MEM,
255 },
256 {
257 .start = OMAP2_STI_IRQ,
258 .flags = IORESOURCE_IRQ,
259 }
260};
646e3ed1
TL		 261#elif defined(CONFIG_ARCH_OMAP3)
262
263#define OMAP3_SDTI_BASE 0x54500000
264#define OMAP3_SDTI_CHANNEL_BASE 0x54600000
265
266static struct resource sti_resources[] = {
267 {
268 .start = OMAP3_SDTI_BASE,
269 .end = OMAP3_SDTI_BASE + 0xFFF,
270 .flags = IORESOURCE_MEM,
271 },
272 {
273 .start = OMAP3_SDTI_CHANNEL_BASE,
274 .end = OMAP3_SDTI_CHANNEL_BASE + SZ_1M - 1,
275 .flags = IORESOURCE_MEM,
276 }
277};
278
279#endif
9b6553cd
TL		 280
281static struct platform_device sti_device = {
282 .name = "sti",
283 .id = -1,
9b6553cd
TL		 284 .num_resources = ARRAY_SIZE(sti_resources),
285 .resource = sti_resources,
286};
287
288static inline void omap_init_sti(void)
289{
290 platform_device_register(&sti_device);
291}
292#else
293static inline void omap_init_sti(void) {}
294#endif
295
646e3ed1 296#if defined(CONFIG_SPI_OMAP24XX) || defined(CONFIG_SPI_OMAP24XX_MODULE)
ed7eb9d9 297
ce491cf8 298#include <plat/mcspi.h>
ed7eb9d9
JY		 299
300#define OMAP2_MCSPI1_BASE 0x48098000
301#define OMAP2_MCSPI2_BASE 0x4809a000
646e3ed1
TL		 302#define OMAP2_MCSPI3_BASE 0x480b8000
303#define OMAP2_MCSPI4_BASE 0x480ba000
ed7eb9d9 304
7869c0b9
SR		 305#define OMAP4_MCSPI1_BASE 0x48098100
306#define OMAP4_MCSPI2_BASE 0x4809a100
307#define OMAP4_MCSPI3_BASE 0x480b8100
308#define OMAP4_MCSPI4_BASE 0x480ba100
309
ed7eb9d9 310static struct omap2_mcspi_platform_config omap2_mcspi1_config = {
ed7eb9d9
JY		 311 .num_cs = 4,
312};
313
c40fae95
TL		 314static struct resource omap2_mcspi1_resources[] = {
315 {
316 .start = OMAP2_MCSPI1_BASE,
317 .end = OMAP2_MCSPI1_BASE + 0xff,
318 .flags = IORESOURCE_MEM,
319 },
320};
321
646e3ed1 322static struct platform_device omap2_mcspi1 = {
ed7eb9d9
JY		 323 .name = "omap2_mcspi",
324 .id = 1,
c40fae95
TL		 325 .num_resources = ARRAY_SIZE(omap2_mcspi1_resources),
326 .resource = omap2_mcspi1_resources,
ed7eb9d9
JY		 327 .dev = {
328 .platform_data = &omap2_mcspi1_config,
329 },
330};
331
332static struct omap2_mcspi_platform_config omap2_mcspi2_config = {
ed7eb9d9
JY		 333 .num_cs = 2,
334};
335
c40fae95
TL		 336static struct resource omap2_mcspi2_resources[] = {
337 {
338 .start = OMAP2_MCSPI2_BASE,
339 .end = OMAP2_MCSPI2_BASE + 0xff,
340 .flags = IORESOURCE_MEM,
341 },
342};
343
646e3ed1 344static struct platform_device omap2_mcspi2 = {
ed7eb9d9
JY		 345 .name = "omap2_mcspi",
346 .id = 2,
c40fae95
TL		 347 .num_resources = ARRAY_SIZE(omap2_mcspi2_resources),
348 .resource = omap2_mcspi2_resources,
ed7eb9d9
JY		 349 .dev = {
350 .platform_data = &omap2_mcspi2_config,
351 },
352};
353
7869c0b9
SR		 354#if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3) || \
355 defined(CONFIG_ARCH_OMAP4)
646e3ed1
TL		 356static struct omap2_mcspi_platform_config omap2_mcspi3_config = {
357 .num_cs = 2,
358};
359
360static struct resource omap2_mcspi3_resources[] = {
361 {
362 .start = OMAP2_MCSPI3_BASE,
363 .end = OMAP2_MCSPI3_BASE + 0xff,
364 .flags = IORESOURCE_MEM,
365 },
366};
367
368static struct platform_device omap2_mcspi3 = {
369 .name = "omap2_mcspi",
370 .id = 3,
371 .num_resources = ARRAY_SIZE(omap2_mcspi3_resources),
372 .resource = omap2_mcspi3_resources,
373 .dev = {
374 .platform_data = &omap2_mcspi3_config,
375 },
376};
377#endif
378
7869c0b9 379#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
646e3ed1
TL		 380static struct omap2_mcspi_platform_config omap2_mcspi4_config = {
381 .num_cs = 1,
382};
383
384static struct resource omap2_mcspi4_resources[] = {
385 {
386 .start = OMAP2_MCSPI4_BASE,
387 .end = OMAP2_MCSPI4_BASE + 0xff,
388 .flags = IORESOURCE_MEM,
389 },
390};
391
392static struct platform_device omap2_mcspi4 = {
393 .name = "omap2_mcspi",
394 .id = 4,
395 .num_resources = ARRAY_SIZE(omap2_mcspi4_resources),
396 .resource = omap2_mcspi4_resources,
397 .dev = {
398 .platform_data = &omap2_mcspi4_config,
399 },
400};
401#endif
402
af41a12f
TL		 403#ifdef CONFIG_ARCH_OMAP4
404static inline void omap4_mcspi_fixup(void)
ed7eb9d9 405{
af41a12f
TL		 406 omap2_mcspi1_resources[0].start = OMAP4_MCSPI1_BASE;
407 omap2_mcspi1_resources[0].end = OMAP4_MCSPI1_BASE + 0xff;
408 omap2_mcspi2_resources[0].start = OMAP4_MCSPI2_BASE;
409 omap2_mcspi2_resources[0].end = OMAP4_MCSPI2_BASE + 0xff;
410 omap2_mcspi3_resources[0].start = OMAP4_MCSPI3_BASE;
411 omap2_mcspi3_resources[0].end = OMAP4_MCSPI3_BASE + 0xff;
412 omap2_mcspi4_resources[0].start = OMAP4_MCSPI4_BASE;
413 omap2_mcspi4_resources[0].end = OMAP4_MCSPI4_BASE + 0xff;
414}
415#else
416static inline void omap4_mcspi_fixup(void)
417{
418}
419#endif
420
7869c0b9
SR		 421#if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3) || \
422 defined(CONFIG_ARCH_OMAP4)
af41a12f
TL		 423static inline void omap2_mcspi3_init(void)
424{
425 platform_device_register(&omap2_mcspi3);
426}
427#else
428static inline void omap2_mcspi3_init(void)
429{
430}
646e3ed1 431#endif
af41a12f 432
7869c0b9 433#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
af41a12f
TL		 434static inline void omap2_mcspi4_init(void)
435{
436 platform_device_register(&omap2_mcspi4);
437}
438#else
439static inline void omap2_mcspi4_init(void)
440{
441}
646e3ed1 442#endif
af41a12f
TL		 443
444static void omap_init_mcspi(void)
445{
446 if (cpu_is_omap44xx())
447 omap4_mcspi_fixup();
448
449 platform_device_register(&omap2_mcspi1);
450 platform_device_register(&omap2_mcspi2);
451
452 if (cpu_is_omap2430() || cpu_is_omap343x() || cpu_is_omap44xx())
453 omap2_mcspi3_init();
454
455 if (cpu_is_omap343x() || cpu_is_omap44xx())
456 omap2_mcspi4_init();
ed7eb9d9
JY		 457}
458
459#else
460static inline void omap_init_mcspi(void) {}
461#endif
462
88341334
WD		 463static struct resource omap2_pmu_resource = {
464 .start = 3,
465 .end = 3,
466 .flags = IORESOURCE_IRQ,
467};
468
469static struct resource omap3_pmu_resource = {
470 .start = INT_34XX_BENCH_MPU_EMUL,
471 .end = INT_34XX_BENCH_MPU_EMUL,
472 .flags = IORESOURCE_IRQ,
473};
474
475static struct platform_device omap_pmu_device = {
476 .name = "arm-pmu",
477 .id = ARM_PMU_DEVICE_CPU,
478 .num_resources = 1,
479};
480
481static void omap_init_pmu(void)
482{
483 if (cpu_is_omap24xx())
484 omap_pmu_device.resource = &omap2_pmu_resource;
485 else if (cpu_is_omap34xx())
486 omap_pmu_device.resource = &omap3_pmu_resource;
487 else
488 return;
489
490 platform_device_register(&omap_pmu_device);
491}
492
493
ee5500c4
DK		 494#if defined(CONFIG_CRYPTO_DEV_OMAP_SHAM) || defined(CONFIG_CRYPTO_DEV_OMAP_SHAM_MODULE)
495
edc774ed 496#ifdef CONFIG_ARCH_OMAP2
ee5500c4 497static struct resource omap2_sham_resources[] = {
646e3ed1
TL		 498 {
499 .start = OMAP24XX_SEC_SHA1MD5_BASE,
500 .end = OMAP24XX_SEC_SHA1MD5_BASE + 0x64,
501 .flags = IORESOURCE_MEM,
502 },
503 {
504 .start = INT_24XX_SHA1MD5,
505 .flags = IORESOURCE_IRQ,
506 }
507};
ee5500c4
DK		 508static int omap2_sham_resources_sz = ARRAY_SIZE(omap2_sham_resources);
509#else
510#define omap2_sham_resources NULL
511#define omap2_sham_resources_sz 0
512#endif
646e3ed1 513
edc774ed 514#ifdef CONFIG_ARCH_OMAP3
ee5500c4
DK		 515static struct resource omap3_sham_resources[] = {
516 {
517 .start = OMAP34XX_SEC_SHA1MD5_BASE,
518 .end = OMAP34XX_SEC_SHA1MD5_BASE + 0x64,
519 .flags = IORESOURCE_MEM,
520 },
521 {
522 .start = INT_34XX_SHA1MD52_IRQ,
523 .flags = IORESOURCE_IRQ,
524 },
525 {
526 .start = OMAP34XX_DMA_SHA1MD5_RX,
527 .flags = IORESOURCE_DMA,
528 }
529};
530static int omap3_sham_resources_sz = ARRAY_SIZE(omap3_sham_resources);
531#else
532#define omap3_sham_resources NULL
533#define omap3_sham_resources_sz 0
534#endif
535
536static struct platform_device sham_device = {
537 .name = "omap-sham",
646e3ed1 538 .id = -1,
646e3ed1
TL		 539};
540
ee5500c4 541static void omap_init_sham(void)
646e3ed1 542{
ee5500c4
DK		 543 if (cpu_is_omap24xx()) {
544 sham_device.resource = omap2_sham_resources;
545 sham_device.num_resources = omap2_sham_resources_sz;
546 } else if (cpu_is_omap34xx()) {
547 sham_device.resource = omap3_sham_resources;
548 sham_device.num_resources = omap3_sham_resources_sz;
549 } else {
550 pr_err("%s: platform not supported\n", __func__);
551 return;
552 }
553 platform_device_register(&sham_device);
646e3ed1
TL		 554}
555#else
ee5500c4 556static inline void omap_init_sham(void) { }
646e3ed1
TL		 557#endif
558
d8874665
TL		 559/*-------------------------------------------------------------------------*/
560
82cf818d 561#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
917fa280
KH		 562
563#define MMCHS_SYSCONFIG 0x0010
564#define MMCHS_SYSCONFIG_SWRESET (1 << 1)
565#define MMCHS_SYSSTATUS 0x0014
566#define MMCHS_SYSSTATUS_RESETDONE (1 << 0)
567
568static struct platform_device dummy_pdev = {
569 .dev = {
570 .bus = &platform_bus_type,
571 },
572};
573
574/**
575 * omap_hsmmc_reset() - Full reset of each HS-MMC controller
576 *
577 * Ensure that each MMC controller is fully reset. Controllers
578 * left in an unknown state (by bootloader) may prevent retention
579 * or OFF-mode. This is especially important in cases where the
580 * MMC driver is not enabled, _or_ built as a module.
581 *
582 * In order for reset to work, interface, functional and debounce
583 * clocks must be enabled. The debounce clock comes from func_32k_clk
584 * and is not under SW control, so we only enable i- and f-clocks.
585 **/
586static void __init omap_hsmmc_reset(void)
587{
4323e9f7
TL		 588 u32 i, nr_controllers;
589
590 if (cpu_is_omap242x())
591 return;
592
593 nr_controllers = cpu_is_omap44xx() ? OMAP44XX_NR_MMC :
82cf818d 594 (cpu_is_omap34xx() ? OMAP34XX_NR_MMC : OMAP24XX_NR_MMC);
917fa280
KH		 595
596 for (i = 0; i < nr_controllers; i++) {
597 u32 v, base = 0;
598 struct clk *iclk, *fclk;
599 struct device *dev = &dummy_pdev.dev;
600
601 switch (i) {
602 case 0:
603 base = OMAP2_MMC1_BASE;
604 break;
605 case 1:
606 base = OMAP2_MMC2_BASE;
607 break;
608 case 2:
609 base = OMAP3_MMC3_BASE;
610 break;
82cf818d 611 case 3:
612 if (!cpu_is_omap44xx())
613 return;
614 base = OMAP4_MMC4_BASE;
615 break;
616 case 4:
617 if (!cpu_is_omap44xx())
618 return;
619 base = OMAP4_MMC5_BASE;
620 break;
917fa280
KH		 621 }
622
82cf818d 623 if (cpu_is_omap44xx())
624 base += OMAP4_MMC_REG_OFFSET;
625
917fa280 626 dummy_pdev.id = i;
1e98ffa8 627 dev_set_name(&dummy_pdev.dev, "mmci-omap-hs.%d", i);
6f7607cc 628 iclk = clk_get(dev, "ick");
917fa280
KH		 629 if (iclk && clk_enable(iclk))
630 iclk = NULL;
631
6f7607cc 632 fclk = clk_get(dev, "fck");
917fa280
KH		 633 if (fclk && clk_enable(fclk))
634 fclk = NULL;
635
636 if (!iclk || !fclk) {
637 printk(KERN_WARNING
638 "%s: Unable to enable clocks for MMC%d, "
639 "cannot reset.\n", __func__, i);
640 break;
641 }
642
643 omap_writel(MMCHS_SYSCONFIG_SWRESET, base + MMCHS_SYSCONFIG);
644 v = omap_readl(base + MMCHS_SYSSTATUS);
645 while (!(omap_readl(base + MMCHS_SYSSTATUS) &
646 MMCHS_SYSSTATUS_RESETDONE))
647 cpu_relax();
648
649 if (fclk) {
650 clk_disable(fclk);
651 clk_put(fclk);
652 }
653 if (iclk) {
654 clk_disable(iclk);
655 clk_put(iclk);
656 }
657 }
658}
659#else
660static inline void omap_hsmmc_reset(void) {}
661#endif
662
d8874665
TL		 663#if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE) || \
664 defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE)
665
666static inline void omap2_mmc_mux(struct omap_mmc_platform_data *mmc_controller,
667 int controller_nr)
668{
ed8303fc 669 if ((mmc_controller->slots[0].switch_pin > 0) && \
670 (mmc_controller->slots[0].switch_pin < OMAP_MAX_GPIO_LINES))
671 omap_mux_init_gpio(mmc_controller->slots[0].switch_pin,
672 OMAP_PIN_INPUT_PULLUP);
673 if ((mmc_controller->slots[0].gpio_wp > 0) && \
674 (mmc_controller->slots[0].gpio_wp < OMAP_MAX_GPIO_LINES))
675 omap_mux_init_gpio(mmc_controller->slots[0].gpio_wp,
676 OMAP_PIN_INPUT_PULLUP);
677
d8874665
TL		 678 if (cpu_is_omap2420() && controller_nr == 0) {
679 omap_cfg_reg(H18_24XX_MMC_CMD);
680 omap_cfg_reg(H15_24XX_MMC_CLKI);
681 omap_cfg_reg(G19_24XX_MMC_CLKO);
682 omap_cfg_reg(F20_24XX_MMC_DAT0);
683 omap_cfg_reg(F19_24XX_MMC_DAT_DIR0);
684 omap_cfg_reg(G18_24XX_MMC_CMD_DIR);
90c62bf0 685 if (mmc_controller->slots[0].wires == 4) {
d8874665
TL		 686 omap_cfg_reg(H14_24XX_MMC_DAT1);
687 omap_cfg_reg(E19_24XX_MMC_DAT2);
688 omap_cfg_reg(D19_24XX_MMC_DAT3);
689 omap_cfg_reg(E20_24XX_MMC_DAT_DIR1);
690 omap_cfg_reg(F18_24XX_MMC_DAT_DIR2);
691 omap_cfg_reg(E18_24XX_MMC_DAT_DIR3);
692 }
693
694 /*
695 * Use internal loop-back in MMC/SDIO Module Input Clock
696 * selection
697 */
698 if (mmc_controller->slots[0].internal_clock) {
699 u32 v = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
700 v |= (1 << 24);
701 omap_ctrl_writel(v, OMAP2_CONTROL_DEVCONF0);
702 }
703 }
57b9daa0 704
4596d14a 705 if (cpu_is_omap34xx()) {
57b9daa0 706 if (controller_nr == 0) {
4896e394
TL		 707 omap_mux_init_signal("sdmmc1_clk",
708 OMAP_PIN_INPUT_PULLUP);
709 omap_mux_init_signal("sdmmc1_cmd",
710 OMAP_PIN_INPUT_PULLUP);
711 omap_mux_init_signal("sdmmc1_dat0",
712 OMAP_PIN_INPUT_PULLUP);
57b9daa0
VP		 713 if (mmc_controller->slots[0].wires == 4 ||
714 mmc_controller->slots[0].wires == 8) {
4896e394
TL		 715 omap_mux_init_signal("sdmmc1_dat1",
716 OMAP_PIN_INPUT_PULLUP);
717 omap_mux_init_signal("sdmmc1_dat2",
718 OMAP_PIN_INPUT_PULLUP);
719 omap_mux_init_signal("sdmmc1_dat3",
720 OMAP_PIN_INPUT_PULLUP);
57b9daa0
VP		 721 }
722 if (mmc_controller->slots[0].wires == 8) {
4896e394
TL		 723 omap_mux_init_signal("sdmmc1_dat4",
724 OMAP_PIN_INPUT_PULLUP);
725 omap_mux_init_signal("sdmmc1_dat5",
726 OMAP_PIN_INPUT_PULLUP);
727 omap_mux_init_signal("sdmmc1_dat6",
728 OMAP_PIN_INPUT_PULLUP);
729 omap_mux_init_signal("sdmmc1_dat7",
730 OMAP_PIN_INPUT_PULLUP);
57b9daa0
VP		 731 }
732 }
733 if (controller_nr == 1) {
734 /* MMC2 */
4896e394
TL		 735 omap_mux_init_signal("sdmmc2_clk",
736 OMAP_PIN_INPUT_PULLUP);
737 omap_mux_init_signal("sdmmc2_cmd",
738 OMAP_PIN_INPUT_PULLUP);
739 omap_mux_init_signal("sdmmc2_dat0",
740 OMAP_PIN_INPUT_PULLUP);
57b9daa0
VP		 741
742 /*
743 * For 8 wire configurations, Lines DAT4, 5, 6 and 7 need to be muxed
744 * in the board-*.c files
745 */
746 if (mmc_controller->slots[0].wires == 4 ||
747 mmc_controller->slots[0].wires == 8) {
4896e394
TL		 748 omap_mux_init_signal("sdmmc2_dat1",
749 OMAP_PIN_INPUT_PULLUP);
750 omap_mux_init_signal("sdmmc2_dat2",
751 OMAP_PIN_INPUT_PULLUP);
752 omap_mux_init_signal("sdmmc2_dat3",
753 OMAP_PIN_INPUT_PULLUP);
57b9daa0 754 }
4679232d 755 if (mmc_controller->slots[0].wires == 8) {
4896e394
TL		 756 omap_mux_init_signal("sdmmc2_dat4.sdmmc2_dat4",
757 OMAP_PIN_INPUT_PULLUP);
758 omap_mux_init_signal("sdmmc2_dat5.sdmmc2_dat5",
759 OMAP_PIN_INPUT_PULLUP);
760 omap_mux_init_signal("sdmmc2_dat6.sdmmc2_dat6",
761 OMAP_PIN_INPUT_PULLUP);
762 omap_mux_init_signal("sdmmc2_dat7.sdmmc2_dat7",
763 OMAP_PIN_INPUT_PULLUP);
4679232d 764 }
57b9daa0
VP		 765 }
766
767 /*
768 * For MMC3 the pins need to be muxed in the board-*.c files
769 */
770 }
d8874665
TL		 771}
772
773void __init omap2_init_mmc(struct omap_mmc_platform_data **mmc_data,
774 int nr_controllers)
775{
776 int i;
0dffb5c5 777 char *name;
d8874665
TL		 778
779 for (i = 0; i < nr_controllers; i++) {
780 unsigned long base, size;
781 unsigned int irq = 0;
782
783 if (!mmc_data[i])
784 continue;
785
786 omap2_mmc_mux(mmc_data[i], i);
787
788 switch (i) {
789 case 0:
790 base = OMAP2_MMC1_BASE;
791 irq = INT_24XX_MMC_IRQ;
792 break;
793 case 1:
794 base = OMAP2_MMC2_BASE;
795 irq = INT_24XX_MMC2_IRQ;
796 break;
797 case 2:
82cf818d 798 if (!cpu_is_omap44xx() && !cpu_is_omap34xx())
d8874665
TL		 799 return;
800 base = OMAP3_MMC3_BASE;
801 irq = INT_34XX_MMC3_IRQ;
802 break;
82cf818d 803 case 3:
804 if (!cpu_is_omap44xx())
805 return;
806 base = OMAP4_MMC4_BASE + OMAP4_MMC_REG_OFFSET;
5772ca7d 807 irq = OMAP44XX_IRQ_MMC4;
82cf818d 808 break;
809 case 4:
810 if (!cpu_is_omap44xx())
811 return;
812 base = OMAP4_MMC5_BASE + OMAP4_MMC_REG_OFFSET;
9df76b7f 813 irq = OMAP44XX_IRQ_MMC5;
82cf818d 814 break;
d8874665
TL		 815 default:
816 continue;
817 }
818
0dffb5c5 819 if (cpu_is_omap2420()) {
d8874665 820 size = OMAP2420_MMC_SIZE;
0dffb5c5 821 name = "mmci-omap";
82cf818d 822 } else if (cpu_is_omap44xx()) {
823 if (i < 3) {
824 base += OMAP4_MMC_REG_OFFSET;
5772ca7d 825 irq += OMAP44XX_IRQ_GIC_START;
82cf818d 826 }
827 size = OMAP4_HSMMC_SIZE;
828 name = "mmci-omap-hs";
0dffb5c5 829 } else {
82cf818d 830 size = OMAP3_HSMMC_SIZE;
0dffb5c5
TL		 831 name = "mmci-omap-hs";
832 }
833 omap_mmc_add(name, i, base, size, irq, mmc_data[i]);
d8874665
TL		 834 };
835}
836
837#endif
838
839/*-------------------------------------------------------------------------*/
840
646e3ed1
TL		 841#if defined(CONFIG_HDQ_MASTER_OMAP) || defined(CONFIG_HDQ_MASTER_OMAP_MODULE)
842#if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3430)
843#define OMAP_HDQ_BASE 0x480B2000
844#endif
845static struct resource omap_hdq_resources[] = {
846 {
847 .start = OMAP_HDQ_BASE,
848 .end = OMAP_HDQ_BASE + 0x1C,
849 .flags = IORESOURCE_MEM,
850 },
851 {
852 .start = INT_24XX_HDQ_IRQ,
853 .flags = IORESOURCE_IRQ,
854 },
855};
856static struct platform_device omap_hdq_dev = {
857 .name = "omap_hdq",
858 .id = 0,
859 .dev = {
860 .platform_data = NULL,
861 },
862 .num_resources = ARRAY_SIZE(omap_hdq_resources),
863 .resource = omap_hdq_resources,
864};
865static inline void omap_hdq_init(void)
866{
867 (void) platform_device_register(&omap_hdq_dev);
868}
869#else
870static inline void omap_hdq_init(void) {}
871#endif
872
b227358d
VH		 873/*---------------------------------------------------------------------------*/
874
875#if defined(CONFIG_VIDEO_OMAP2_VOUT) || \
876 defined(CONFIG_VIDEO_OMAP2_VOUT_MODULE)
877#if defined(CONFIG_FB_OMAP2) || defined(CONFIG_FB_OMAP2_MODULE)
878static struct resource omap_vout_resource[3 - CONFIG_FB_OMAP2_NUM_FBS] = {
879};
880#else
881static struct resource omap_vout_resource[2] = {
882};
883#endif
884
885static struct platform_device omap_vout_device = {
886 .name = "omap_vout",
887 .num_resources = ARRAY_SIZE(omap_vout_resource),
888 .resource = &omap_vout_resource[0],
889 .id = -1,
890};
891static void omap_init_vout(void)
892{
893 if (platform_device_register(&omap_vout_device) < 0)
894 printk(KERN_ERR "Unable to register OMAP-VOUT device\n");
895}
896#else
897static inline void omap_init_vout(void) {}
898#endif
899
1dbae815
TL		 900/*-------------------------------------------------------------------------*/
901
902static int __init omap2_init_devices(void)
903{
904 /* please keep these calls, and their implementations above,
905 * in alphabetical order so they're easier to sort through.
906 */
917fa280 907 omap_hsmmc_reset();
828c707e 908 omap_init_camera();
c40fae95 909 omap_init_mbox();
ed7eb9d9 910 omap_init_mcspi();
88341334 911 omap_init_pmu();
646e3ed1 912 omap_hdq_init();
9b6553cd 913 omap_init_sti();
ee5500c4 914 omap_init_sham();
b227358d 915 omap_init_vout();
1dbae815
TL		 916
917 return 0;
918}
919arch_initcall(omap2_init_devices);
Linux kernel - Deliverables
This page took 0.422442 seconds and 5 git commands to generate.