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1dbae815 TL |
1 | /* |
2 | * linux/arch/arm/mach-omap2/devices.c | |
3 | * | |
4 | * OMAP2 platform device setup/initialization | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License, or | |
9 | * (at your option) any later version. | |
10 | */ | |
11 | ||
1dbae815 TL |
12 | #include <linux/kernel.h> |
13 | #include <linux/init.h> | |
14 | #include <linux/platform_device.h> | |
fced80c7 | 15 | #include <linux/io.h> |
917fa280 | 16 | #include <linux/clk.h> |
f2ce6231 | 17 | #include <linux/err.h> |
1dbae815 | 18 | |
a09e64fb | 19 | #include <mach/hardware.h> |
88341334 | 20 | #include <mach/irqs.h> |
1dbae815 TL |
21 | #include <asm/mach-types.h> |
22 | #include <asm/mach/map.h> | |
88341334 | 23 | #include <asm/pmu.h> |
1dbae815 | 24 | |
ce491cf8 TL |
25 | #include <plat/tc.h> |
26 | #include <plat/board.h> | |
a09f73fa | 27 | #include <plat/mcbsp.h> |
a09e64fb | 28 | #include <mach/gpio.h> |
ce491cf8 | 29 | #include <plat/mmc.h> |
ee5500c4 | 30 | #include <plat/dma.h> |
f2ce6231 VC |
31 | #include <plat/omap_hwmod.h> |
32 | #include <plat/omap_device.h> | |
1dbae815 | 33 | |
4896e394 | 34 | #include "mux.h" |
4814ced5 | 35 | #include "control.h" |
81fbc5ef | 36 | #include "wd_timer.h" |
4896e394 | 37 | |
828c707e | 38 | #if defined(CONFIG_VIDEO_OMAP2) || defined(CONFIG_VIDEO_OMAP2_MODULE) |
c40fae95 | 39 | |
828c707e | 40 | static struct resource cam_resources[] = { |
c40fae95 | 41 | { |
828c707e TL |
42 | .start = OMAP24XX_CAMERA_BASE, |
43 | .end = OMAP24XX_CAMERA_BASE + 0xfff, | |
44 | .flags = IORESOURCE_MEM, | |
45 | }, | |
46 | { | |
47 | .start = INT_24XX_CAM_IRQ, | |
48 | .flags = IORESOURCE_IRQ, | |
49 | } | |
50 | }; | |
51 | ||
52 | static struct platform_device omap_cam_device = { | |
53 | .name = "omap24xxcam", | |
54 | .id = -1, | |
55 | .num_resources = ARRAY_SIZE(cam_resources), | |
56 | .resource = cam_resources, | |
57 | }; | |
58 | ||
59 | static inline void omap_init_camera(void) | |
60 | { | |
61 | platform_device_register(&omap_cam_device); | |
62 | } | |
63 | ||
64 | #elif defined(CONFIG_VIDEO_OMAP3) || defined(CONFIG_VIDEO_OMAP3_MODULE) | |
65 | ||
66 | static struct resource omap3isp_resources[] = { | |
67 | { | |
68 | .start = OMAP3430_ISP_BASE, | |
69 | .end = OMAP3430_ISP_END, | |
70 | .flags = IORESOURCE_MEM, | |
71 | }, | |
72 | { | |
73 | .start = OMAP3430_ISP_CBUFF_BASE, | |
74 | .end = OMAP3430_ISP_CBUFF_END, | |
75 | .flags = IORESOURCE_MEM, | |
76 | }, | |
77 | { | |
78 | .start = OMAP3430_ISP_CCP2_BASE, | |
79 | .end = OMAP3430_ISP_CCP2_END, | |
80 | .flags = IORESOURCE_MEM, | |
81 | }, | |
82 | { | |
83 | .start = OMAP3430_ISP_CCDC_BASE, | |
84 | .end = OMAP3430_ISP_CCDC_END, | |
85 | .flags = IORESOURCE_MEM, | |
86 | }, | |
87 | { | |
88 | .start = OMAP3430_ISP_HIST_BASE, | |
89 | .end = OMAP3430_ISP_HIST_END, | |
90 | .flags = IORESOURCE_MEM, | |
91 | }, | |
92 | { | |
93 | .start = OMAP3430_ISP_H3A_BASE, | |
94 | .end = OMAP3430_ISP_H3A_END, | |
95 | .flags = IORESOURCE_MEM, | |
96 | }, | |
97 | { | |
98 | .start = OMAP3430_ISP_PREV_BASE, | |
99 | .end = OMAP3430_ISP_PREV_END, | |
100 | .flags = IORESOURCE_MEM, | |
101 | }, | |
102 | { | |
103 | .start = OMAP3430_ISP_RESZ_BASE, | |
104 | .end = OMAP3430_ISP_RESZ_END, | |
105 | .flags = IORESOURCE_MEM, | |
106 | }, | |
107 | { | |
108 | .start = OMAP3430_ISP_SBL_BASE, | |
109 | .end = OMAP3430_ISP_SBL_END, | |
110 | .flags = IORESOURCE_MEM, | |
111 | }, | |
112 | { | |
113 | .start = OMAP3430_ISP_CSI2A_BASE, | |
114 | .end = OMAP3430_ISP_CSI2A_END, | |
115 | .flags = IORESOURCE_MEM, | |
116 | }, | |
117 | { | |
118 | .start = OMAP3430_ISP_CSI2PHY_BASE, | |
119 | .end = OMAP3430_ISP_CSI2PHY_END, | |
120 | .flags = IORESOURCE_MEM, | |
121 | }, | |
122 | { | |
123 | .start = INT_34XX_CAM_IRQ, | |
124 | .flags = IORESOURCE_IRQ, | |
125 | } | |
126 | }; | |
127 | ||
128 | static struct platform_device omap3isp_device = { | |
129 | .name = "omap3isp", | |
130 | .id = -1, | |
131 | .num_resources = ARRAY_SIZE(omap3isp_resources), | |
132 | .resource = omap3isp_resources, | |
133 | }; | |
134 | ||
135 | static inline void omap_init_camera(void) | |
136 | { | |
137 | platform_device_register(&omap3isp_device); | |
138 | } | |
139 | #else | |
140 | static inline void omap_init_camera(void) | |
141 | { | |
142 | } | |
143 | #endif | |
144 | ||
6c20a683 | 145 | #if defined(CONFIG_OMAP_MBOX_FWK) || defined(CONFIG_OMAP_MBOX_FWK_MODULE) |
c40fae95 | 146 | |
454bf340 | 147 | #define MBOX_REG_SIZE 0x120 |
6c20a683 | 148 | |
454bf340 | 149 | #ifdef CONFIG_ARCH_OMAP2 |
d10f2b6e | 150 | static struct resource omap2_mbox_resources[] = { |
c40fae95 | 151 | { |
6c20a683 HD |
152 | .start = OMAP24XX_MAILBOX_BASE, |
153 | .end = OMAP24XX_MAILBOX_BASE + MBOX_REG_SIZE - 1, | |
c40fae95 TL |
154 | .flags = IORESOURCE_MEM, |
155 | }, | |
156 | { | |
157 | .start = INT_24XX_MAIL_U0_MPU, | |
158 | .flags = IORESOURCE_IRQ, | |
1f2c4dfd | 159 | .name = "dsp", |
c40fae95 TL |
160 | }, |
161 | { | |
162 | .start = INT_24XX_MAIL_U3_MPU, | |
163 | .flags = IORESOURCE_IRQ, | |
1f2c4dfd | 164 | .name = "iva", |
c40fae95 TL |
165 | }, |
166 | }; | |
d10f2b6e TL |
167 | static int omap2_mbox_resources_sz = ARRAY_SIZE(omap2_mbox_resources); |
168 | #else | |
169 | #define omap2_mbox_resources NULL | |
170 | #define omap2_mbox_resources_sz 0 | |
454bf340 | 171 | #endif |
c40fae95 | 172 | |
454bf340 | 173 | #ifdef CONFIG_ARCH_OMAP3 |
d10f2b6e | 174 | static struct resource omap3_mbox_resources[] = { |
6c20a683 HD |
175 | { |
176 | .start = OMAP34XX_MAILBOX_BASE, | |
177 | .end = OMAP34XX_MAILBOX_BASE + MBOX_REG_SIZE - 1, | |
178 | .flags = IORESOURCE_MEM, | |
179 | }, | |
180 | { | |
181 | .start = INT_24XX_MAIL_U0_MPU, | |
182 | .flags = IORESOURCE_IRQ, | |
1f2c4dfd | 183 | .name = "dsp", |
6c20a683 HD |
184 | }, |
185 | }; | |
d10f2b6e TL |
186 | static int omap3_mbox_resources_sz = ARRAY_SIZE(omap3_mbox_resources); |
187 | #else | |
188 | #define omap3_mbox_resources NULL | |
189 | #define omap3_mbox_resources_sz 0 | |
454bf340 S |
190 | #endif |
191 | ||
192 | #ifdef CONFIG_ARCH_OMAP4 | |
193 | ||
194 | #define OMAP4_MBOX_REG_SIZE 0x130 | |
d10f2b6e | 195 | static struct resource omap4_mbox_resources[] = { |
454bf340 S |
196 | { |
197 | .start = OMAP44XX_MAILBOX_BASE, | |
198 | .end = OMAP44XX_MAILBOX_BASE + | |
199 | OMAP4_MBOX_REG_SIZE - 1, | |
200 | .flags = IORESOURCE_MEM, | |
201 | }, | |
202 | { | |
5772ca7d | 203 | .start = OMAP44XX_IRQ_MAIL_U0, |
454bf340 | 204 | .flags = IORESOURCE_IRQ, |
1f2c4dfd | 205 | .name = "mbox", |
454bf340 S |
206 | }, |
207 | }; | |
d10f2b6e TL |
208 | static int omap4_mbox_resources_sz = ARRAY_SIZE(omap4_mbox_resources); |
209 | #else | |
210 | #define omap4_mbox_resources NULL | |
211 | #define omap4_mbox_resources_sz 0 | |
454bf340 | 212 | #endif |
6c20a683 | 213 | |
c40fae95 | 214 | static struct platform_device mbox_device = { |
d742709e | 215 | .name = "omap-mailbox", |
c40fae95 | 216 | .id = -1, |
c40fae95 TL |
217 | }; |
218 | ||
219 | static inline void omap_init_mbox(void) | |
220 | { | |
d10f2b6e TL |
221 | if (cpu_is_omap24xx()) { |
222 | mbox_device.resource = omap2_mbox_resources; | |
223 | mbox_device.num_resources = omap2_mbox_resources_sz; | |
224 | } else if (cpu_is_omap34xx()) { | |
225 | mbox_device.resource = omap3_mbox_resources; | |
226 | mbox_device.num_resources = omap3_mbox_resources_sz; | |
227 | } else if (cpu_is_omap44xx()) { | |
228 | mbox_device.resource = omap4_mbox_resources; | |
229 | mbox_device.num_resources = omap4_mbox_resources_sz; | |
6c20a683 HD |
230 | } else { |
231 | pr_err("%s: platform not supported\n", __func__); | |
232 | return; | |
233 | } | |
c40fae95 TL |
234 | platform_device_register(&mbox_device); |
235 | } | |
236 | #else | |
237 | static inline void omap_init_mbox(void) { } | |
6c20a683 | 238 | #endif /* CONFIG_OMAP_MBOX_FWK */ |
c40fae95 | 239 | |
9b6553cd | 240 | static inline void omap_init_sti(void) {} |
9b6553cd | 241 | |
f0fba2ad LG |
242 | #if defined(CONFIG_SND_SOC) || defined(CONFIG_SND_SOC_MODULE) |
243 | ||
244 | static struct platform_device omap_pcm = { | |
245 | .name = "omap-pcm-audio", | |
246 | .id = -1, | |
247 | }; | |
248 | ||
249 | /* | |
250 | * OMAP2420 has 2 McBSP ports | |
251 | * OMAP2430 has 5 McBSP ports | |
252 | * OMAP3 has 5 McBSP ports | |
253 | * OMAP4 has 4 McBSP ports | |
254 | */ | |
255 | OMAP_MCBSP_PLATFORM_DEVICE(1); | |
256 | OMAP_MCBSP_PLATFORM_DEVICE(2); | |
257 | OMAP_MCBSP_PLATFORM_DEVICE(3); | |
258 | OMAP_MCBSP_PLATFORM_DEVICE(4); | |
259 | OMAP_MCBSP_PLATFORM_DEVICE(5); | |
260 | ||
261 | static void omap_init_audio(void) | |
262 | { | |
263 | platform_device_register(&omap_mcbsp1); | |
264 | platform_device_register(&omap_mcbsp2); | |
265 | if (cpu_is_omap243x() || cpu_is_omap34xx() || cpu_is_omap44xx()) { | |
266 | platform_device_register(&omap_mcbsp3); | |
267 | platform_device_register(&omap_mcbsp4); | |
268 | } | |
269 | if (cpu_is_omap243x() || cpu_is_omap34xx()) | |
270 | platform_device_register(&omap_mcbsp5); | |
271 | ||
272 | platform_device_register(&omap_pcm); | |
273 | } | |
274 | ||
275 | #else | |
276 | static inline void omap_init_audio(void) {} | |
277 | #endif | |
278 | ||
646e3ed1 | 279 | #if defined(CONFIG_SPI_OMAP24XX) || defined(CONFIG_SPI_OMAP24XX_MODULE) |
ed7eb9d9 | 280 | |
ce491cf8 | 281 | #include <plat/mcspi.h> |
ed7eb9d9 JY |
282 | |
283 | #define OMAP2_MCSPI1_BASE 0x48098000 | |
284 | #define OMAP2_MCSPI2_BASE 0x4809a000 | |
646e3ed1 TL |
285 | #define OMAP2_MCSPI3_BASE 0x480b8000 |
286 | #define OMAP2_MCSPI4_BASE 0x480ba000 | |
ed7eb9d9 | 287 | |
7869c0b9 SR |
288 | #define OMAP4_MCSPI1_BASE 0x48098100 |
289 | #define OMAP4_MCSPI2_BASE 0x4809a100 | |
290 | #define OMAP4_MCSPI3_BASE 0x480b8100 | |
291 | #define OMAP4_MCSPI4_BASE 0x480ba100 | |
292 | ||
ed7eb9d9 | 293 | static struct omap2_mcspi_platform_config omap2_mcspi1_config = { |
ed7eb9d9 JY |
294 | .num_cs = 4, |
295 | }; | |
296 | ||
c40fae95 TL |
297 | static struct resource omap2_mcspi1_resources[] = { |
298 | { | |
299 | .start = OMAP2_MCSPI1_BASE, | |
300 | .end = OMAP2_MCSPI1_BASE + 0xff, | |
301 | .flags = IORESOURCE_MEM, | |
302 | }, | |
303 | }; | |
304 | ||
646e3ed1 | 305 | static struct platform_device omap2_mcspi1 = { |
ed7eb9d9 JY |
306 | .name = "omap2_mcspi", |
307 | .id = 1, | |
c40fae95 TL |
308 | .num_resources = ARRAY_SIZE(omap2_mcspi1_resources), |
309 | .resource = omap2_mcspi1_resources, | |
ed7eb9d9 JY |
310 | .dev = { |
311 | .platform_data = &omap2_mcspi1_config, | |
312 | }, | |
313 | }; | |
314 | ||
315 | static struct omap2_mcspi_platform_config omap2_mcspi2_config = { | |
ed7eb9d9 JY |
316 | .num_cs = 2, |
317 | }; | |
318 | ||
c40fae95 TL |
319 | static struct resource omap2_mcspi2_resources[] = { |
320 | { | |
321 | .start = OMAP2_MCSPI2_BASE, | |
322 | .end = OMAP2_MCSPI2_BASE + 0xff, | |
323 | .flags = IORESOURCE_MEM, | |
324 | }, | |
325 | }; | |
326 | ||
646e3ed1 | 327 | static struct platform_device omap2_mcspi2 = { |
ed7eb9d9 JY |
328 | .name = "omap2_mcspi", |
329 | .id = 2, | |
c40fae95 TL |
330 | .num_resources = ARRAY_SIZE(omap2_mcspi2_resources), |
331 | .resource = omap2_mcspi2_resources, | |
ed7eb9d9 JY |
332 | .dev = { |
333 | .platform_data = &omap2_mcspi2_config, | |
334 | }, | |
335 | }; | |
336 | ||
7869c0b9 SR |
337 | #if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3) || \ |
338 | defined(CONFIG_ARCH_OMAP4) | |
646e3ed1 TL |
339 | static struct omap2_mcspi_platform_config omap2_mcspi3_config = { |
340 | .num_cs = 2, | |
341 | }; | |
342 | ||
343 | static struct resource omap2_mcspi3_resources[] = { | |
344 | { | |
345 | .start = OMAP2_MCSPI3_BASE, | |
346 | .end = OMAP2_MCSPI3_BASE + 0xff, | |
347 | .flags = IORESOURCE_MEM, | |
348 | }, | |
349 | }; | |
350 | ||
351 | static struct platform_device omap2_mcspi3 = { | |
352 | .name = "omap2_mcspi", | |
353 | .id = 3, | |
354 | .num_resources = ARRAY_SIZE(omap2_mcspi3_resources), | |
355 | .resource = omap2_mcspi3_resources, | |
356 | .dev = { | |
357 | .platform_data = &omap2_mcspi3_config, | |
358 | }, | |
359 | }; | |
360 | #endif | |
361 | ||
7869c0b9 | 362 | #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4) |
646e3ed1 TL |
363 | static struct omap2_mcspi_platform_config omap2_mcspi4_config = { |
364 | .num_cs = 1, | |
365 | }; | |
366 | ||
367 | static struct resource omap2_mcspi4_resources[] = { | |
368 | { | |
369 | .start = OMAP2_MCSPI4_BASE, | |
370 | .end = OMAP2_MCSPI4_BASE + 0xff, | |
371 | .flags = IORESOURCE_MEM, | |
372 | }, | |
373 | }; | |
374 | ||
375 | static struct platform_device omap2_mcspi4 = { | |
376 | .name = "omap2_mcspi", | |
377 | .id = 4, | |
378 | .num_resources = ARRAY_SIZE(omap2_mcspi4_resources), | |
379 | .resource = omap2_mcspi4_resources, | |
380 | .dev = { | |
381 | .platform_data = &omap2_mcspi4_config, | |
382 | }, | |
383 | }; | |
384 | #endif | |
385 | ||
af41a12f TL |
386 | #ifdef CONFIG_ARCH_OMAP4 |
387 | static inline void omap4_mcspi_fixup(void) | |
ed7eb9d9 | 388 | { |
af41a12f TL |
389 | omap2_mcspi1_resources[0].start = OMAP4_MCSPI1_BASE; |
390 | omap2_mcspi1_resources[0].end = OMAP4_MCSPI1_BASE + 0xff; | |
391 | omap2_mcspi2_resources[0].start = OMAP4_MCSPI2_BASE; | |
392 | omap2_mcspi2_resources[0].end = OMAP4_MCSPI2_BASE + 0xff; | |
393 | omap2_mcspi3_resources[0].start = OMAP4_MCSPI3_BASE; | |
394 | omap2_mcspi3_resources[0].end = OMAP4_MCSPI3_BASE + 0xff; | |
395 | omap2_mcspi4_resources[0].start = OMAP4_MCSPI4_BASE; | |
396 | omap2_mcspi4_resources[0].end = OMAP4_MCSPI4_BASE + 0xff; | |
397 | } | |
398 | #else | |
399 | static inline void omap4_mcspi_fixup(void) | |
400 | { | |
401 | } | |
402 | #endif | |
403 | ||
7869c0b9 SR |
404 | #if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3) || \ |
405 | defined(CONFIG_ARCH_OMAP4) | |
af41a12f TL |
406 | static inline void omap2_mcspi3_init(void) |
407 | { | |
408 | platform_device_register(&omap2_mcspi3); | |
409 | } | |
410 | #else | |
411 | static inline void omap2_mcspi3_init(void) | |
412 | { | |
413 | } | |
646e3ed1 | 414 | #endif |
af41a12f | 415 | |
7869c0b9 | 416 | #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4) |
af41a12f TL |
417 | static inline void omap2_mcspi4_init(void) |
418 | { | |
419 | platform_device_register(&omap2_mcspi4); | |
420 | } | |
421 | #else | |
422 | static inline void omap2_mcspi4_init(void) | |
423 | { | |
424 | } | |
646e3ed1 | 425 | #endif |
af41a12f TL |
426 | |
427 | static void omap_init_mcspi(void) | |
428 | { | |
429 | if (cpu_is_omap44xx()) | |
430 | omap4_mcspi_fixup(); | |
431 | ||
432 | platform_device_register(&omap2_mcspi1); | |
433 | platform_device_register(&omap2_mcspi2); | |
434 | ||
435 | if (cpu_is_omap2430() || cpu_is_omap343x() || cpu_is_omap44xx()) | |
436 | omap2_mcspi3_init(); | |
437 | ||
438 | if (cpu_is_omap343x() || cpu_is_omap44xx()) | |
439 | omap2_mcspi4_init(); | |
ed7eb9d9 JY |
440 | } |
441 | ||
442 | #else | |
443 | static inline void omap_init_mcspi(void) {} | |
444 | #endif | |
445 | ||
88341334 WD |
446 | static struct resource omap2_pmu_resource = { |
447 | .start = 3, | |
448 | .end = 3, | |
449 | .flags = IORESOURCE_IRQ, | |
450 | }; | |
451 | ||
452 | static struct resource omap3_pmu_resource = { | |
453 | .start = INT_34XX_BENCH_MPU_EMUL, | |
454 | .end = INT_34XX_BENCH_MPU_EMUL, | |
455 | .flags = IORESOURCE_IRQ, | |
456 | }; | |
457 | ||
458 | static struct platform_device omap_pmu_device = { | |
459 | .name = "arm-pmu", | |
460 | .id = ARM_PMU_DEVICE_CPU, | |
461 | .num_resources = 1, | |
462 | }; | |
463 | ||
464 | static void omap_init_pmu(void) | |
465 | { | |
466 | if (cpu_is_omap24xx()) | |
467 | omap_pmu_device.resource = &omap2_pmu_resource; | |
468 | else if (cpu_is_omap34xx()) | |
469 | omap_pmu_device.resource = &omap3_pmu_resource; | |
470 | else | |
471 | return; | |
472 | ||
473 | platform_device_register(&omap_pmu_device); | |
474 | } | |
475 | ||
476 | ||
ee5500c4 DK |
477 | #if defined(CONFIG_CRYPTO_DEV_OMAP_SHAM) || defined(CONFIG_CRYPTO_DEV_OMAP_SHAM_MODULE) |
478 | ||
edc774ed | 479 | #ifdef CONFIG_ARCH_OMAP2 |
ee5500c4 | 480 | static struct resource omap2_sham_resources[] = { |
646e3ed1 TL |
481 | { |
482 | .start = OMAP24XX_SEC_SHA1MD5_BASE, | |
483 | .end = OMAP24XX_SEC_SHA1MD5_BASE + 0x64, | |
484 | .flags = IORESOURCE_MEM, | |
485 | }, | |
486 | { | |
487 | .start = INT_24XX_SHA1MD5, | |
488 | .flags = IORESOURCE_IRQ, | |
489 | } | |
490 | }; | |
ee5500c4 DK |
491 | static int omap2_sham_resources_sz = ARRAY_SIZE(omap2_sham_resources); |
492 | #else | |
493 | #define omap2_sham_resources NULL | |
494 | #define omap2_sham_resources_sz 0 | |
495 | #endif | |
646e3ed1 | 496 | |
edc774ed | 497 | #ifdef CONFIG_ARCH_OMAP3 |
ee5500c4 DK |
498 | static struct resource omap3_sham_resources[] = { |
499 | { | |
500 | .start = OMAP34XX_SEC_SHA1MD5_BASE, | |
501 | .end = OMAP34XX_SEC_SHA1MD5_BASE + 0x64, | |
502 | .flags = IORESOURCE_MEM, | |
503 | }, | |
504 | { | |
505 | .start = INT_34XX_SHA1MD52_IRQ, | |
506 | .flags = IORESOURCE_IRQ, | |
507 | }, | |
508 | { | |
509 | .start = OMAP34XX_DMA_SHA1MD5_RX, | |
510 | .flags = IORESOURCE_DMA, | |
511 | } | |
512 | }; | |
513 | static int omap3_sham_resources_sz = ARRAY_SIZE(omap3_sham_resources); | |
514 | #else | |
515 | #define omap3_sham_resources NULL | |
516 | #define omap3_sham_resources_sz 0 | |
517 | #endif | |
518 | ||
519 | static struct platform_device sham_device = { | |
520 | .name = "omap-sham", | |
646e3ed1 | 521 | .id = -1, |
646e3ed1 TL |
522 | }; |
523 | ||
ee5500c4 | 524 | static void omap_init_sham(void) |
646e3ed1 | 525 | { |
ee5500c4 DK |
526 | if (cpu_is_omap24xx()) { |
527 | sham_device.resource = omap2_sham_resources; | |
528 | sham_device.num_resources = omap2_sham_resources_sz; | |
529 | } else if (cpu_is_omap34xx()) { | |
530 | sham_device.resource = omap3_sham_resources; | |
531 | sham_device.num_resources = omap3_sham_resources_sz; | |
532 | } else { | |
533 | pr_err("%s: platform not supported\n", __func__); | |
534 | return; | |
535 | } | |
536 | platform_device_register(&sham_device); | |
646e3ed1 TL |
537 | } |
538 | #else | |
ee5500c4 | 539 | static inline void omap_init_sham(void) { } |
646e3ed1 TL |
540 | #endif |
541 | ||
b744c679 DK |
542 | #if defined(CONFIG_CRYPTO_DEV_OMAP_AES) || defined(CONFIG_CRYPTO_DEV_OMAP_AES_MODULE) |
543 | ||
82a0c149 | 544 | #ifdef CONFIG_ARCH_OMAP2 |
b744c679 DK |
545 | static struct resource omap2_aes_resources[] = { |
546 | { | |
547 | .start = OMAP24XX_SEC_AES_BASE, | |
548 | .end = OMAP24XX_SEC_AES_BASE + 0x4C, | |
549 | .flags = IORESOURCE_MEM, | |
550 | }, | |
551 | { | |
552 | .start = OMAP24XX_DMA_AES_TX, | |
553 | .flags = IORESOURCE_DMA, | |
554 | }, | |
555 | { | |
556 | .start = OMAP24XX_DMA_AES_RX, | |
557 | .flags = IORESOURCE_DMA, | |
558 | } | |
559 | }; | |
560 | static int omap2_aes_resources_sz = ARRAY_SIZE(omap2_aes_resources); | |
561 | #else | |
562 | #define omap2_aes_resources NULL | |
563 | #define omap2_aes_resources_sz 0 | |
564 | #endif | |
565 | ||
82a0c149 | 566 | #ifdef CONFIG_ARCH_OMAP3 |
b744c679 DK |
567 | static struct resource omap3_aes_resources[] = { |
568 | { | |
569 | .start = OMAP34XX_SEC_AES_BASE, | |
570 | .end = OMAP34XX_SEC_AES_BASE + 0x4C, | |
571 | .flags = IORESOURCE_MEM, | |
572 | }, | |
573 | { | |
574 | .start = OMAP34XX_DMA_AES2_TX, | |
575 | .flags = IORESOURCE_DMA, | |
576 | }, | |
577 | { | |
578 | .start = OMAP34XX_DMA_AES2_RX, | |
579 | .flags = IORESOURCE_DMA, | |
580 | } | |
581 | }; | |
582 | static int omap3_aes_resources_sz = ARRAY_SIZE(omap3_aes_resources); | |
583 | #else | |
584 | #define omap3_aes_resources NULL | |
585 | #define omap3_aes_resources_sz 0 | |
586 | #endif | |
587 | ||
588 | static struct platform_device aes_device = { | |
589 | .name = "omap-aes", | |
590 | .id = -1, | |
591 | }; | |
592 | ||
593 | static void omap_init_aes(void) | |
594 | { | |
595 | if (cpu_is_omap24xx()) { | |
596 | aes_device.resource = omap2_aes_resources; | |
597 | aes_device.num_resources = omap2_aes_resources_sz; | |
598 | } else if (cpu_is_omap34xx()) { | |
599 | aes_device.resource = omap3_aes_resources; | |
600 | aes_device.num_resources = omap3_aes_resources_sz; | |
601 | } else { | |
602 | pr_err("%s: platform not supported\n", __func__); | |
603 | return; | |
604 | } | |
605 | platform_device_register(&aes_device); | |
606 | } | |
607 | ||
608 | #else | |
609 | static inline void omap_init_aes(void) { } | |
610 | #endif | |
611 | ||
d8874665 TL |
612 | /*-------------------------------------------------------------------------*/ |
613 | ||
82cf818d | 614 | #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4) |
917fa280 KH |
615 | |
616 | #define MMCHS_SYSCONFIG 0x0010 | |
617 | #define MMCHS_SYSCONFIG_SWRESET (1 << 1) | |
618 | #define MMCHS_SYSSTATUS 0x0014 | |
619 | #define MMCHS_SYSSTATUS_RESETDONE (1 << 0) | |
620 | ||
621 | static struct platform_device dummy_pdev = { | |
622 | .dev = { | |
623 | .bus = &platform_bus_type, | |
624 | }, | |
625 | }; | |
626 | ||
627 | /** | |
628 | * omap_hsmmc_reset() - Full reset of each HS-MMC controller | |
629 | * | |
630 | * Ensure that each MMC controller is fully reset. Controllers | |
631 | * left in an unknown state (by bootloader) may prevent retention | |
632 | * or OFF-mode. This is especially important in cases where the | |
633 | * MMC driver is not enabled, _or_ built as a module. | |
634 | * | |
635 | * In order for reset to work, interface, functional and debounce | |
636 | * clocks must be enabled. The debounce clock comes from func_32k_clk | |
637 | * and is not under SW control, so we only enable i- and f-clocks. | |
638 | **/ | |
639 | static void __init omap_hsmmc_reset(void) | |
640 | { | |
4323e9f7 | 641 | u32 i, nr_controllers; |
434c23a7 | 642 | struct clk *iclk, *fclk; |
4323e9f7 TL |
643 | |
644 | if (cpu_is_omap242x()) | |
645 | return; | |
646 | ||
647 | nr_controllers = cpu_is_omap44xx() ? OMAP44XX_NR_MMC : | |
82cf818d | 648 | (cpu_is_omap34xx() ? OMAP34XX_NR_MMC : OMAP24XX_NR_MMC); |
917fa280 KH |
649 | |
650 | for (i = 0; i < nr_controllers; i++) { | |
651 | u32 v, base = 0; | |
917fa280 KH |
652 | struct device *dev = &dummy_pdev.dev; |
653 | ||
654 | switch (i) { | |
655 | case 0: | |
656 | base = OMAP2_MMC1_BASE; | |
657 | break; | |
658 | case 1: | |
659 | base = OMAP2_MMC2_BASE; | |
660 | break; | |
661 | case 2: | |
662 | base = OMAP3_MMC3_BASE; | |
663 | break; | |
82cf818d | 664 | case 3: |
665 | if (!cpu_is_omap44xx()) | |
666 | return; | |
667 | base = OMAP4_MMC4_BASE; | |
668 | break; | |
669 | case 4: | |
670 | if (!cpu_is_omap44xx()) | |
671 | return; | |
672 | base = OMAP4_MMC5_BASE; | |
673 | break; | |
917fa280 KH |
674 | } |
675 | ||
82cf818d | 676 | if (cpu_is_omap44xx()) |
677 | base += OMAP4_MMC_REG_OFFSET; | |
678 | ||
917fa280 | 679 | dummy_pdev.id = i; |
1e98ffa8 | 680 | dev_set_name(&dummy_pdev.dev, "mmci-omap-hs.%d", i); |
6f7607cc | 681 | iclk = clk_get(dev, "ick"); |
434c23a7 AK |
682 | if (IS_ERR(iclk)) |
683 | goto err1; | |
684 | if (clk_enable(iclk)) | |
685 | goto err2; | |
917fa280 | 686 | |
6f7607cc | 687 | fclk = clk_get(dev, "fck"); |
434c23a7 AK |
688 | if (IS_ERR(fclk)) |
689 | goto err3; | |
690 | if (clk_enable(fclk)) | |
691 | goto err4; | |
917fa280 KH |
692 | |
693 | omap_writel(MMCHS_SYSCONFIG_SWRESET, base + MMCHS_SYSCONFIG); | |
694 | v = omap_readl(base + MMCHS_SYSSTATUS); | |
695 | while (!(omap_readl(base + MMCHS_SYSSTATUS) & | |
696 | MMCHS_SYSSTATUS_RESETDONE)) | |
697 | cpu_relax(); | |
698 | ||
434c23a7 AK |
699 | clk_disable(fclk); |
700 | clk_put(fclk); | |
701 | clk_disable(iclk); | |
702 | clk_put(iclk); | |
917fa280 | 703 | } |
434c23a7 AK |
704 | return; |
705 | ||
706 | err4: | |
707 | clk_put(fclk); | |
708 | err3: | |
709 | clk_disable(iclk); | |
710 | err2: | |
711 | clk_put(iclk); | |
712 | err1: | |
713 | printk(KERN_WARNING "%s: Unable to enable clocks for MMC%d, " | |
714 | "cannot reset.\n", __func__, i); | |
917fa280 KH |
715 | } |
716 | #else | |
717 | static inline void omap_hsmmc_reset(void) {} | |
718 | #endif | |
719 | ||
d8874665 TL |
720 | #if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE) || \ |
721 | defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE) | |
722 | ||
723 | static inline void omap2_mmc_mux(struct omap_mmc_platform_data *mmc_controller, | |
724 | int controller_nr) | |
725 | { | |
ed8303fc | 726 | if ((mmc_controller->slots[0].switch_pin > 0) && \ |
727 | (mmc_controller->slots[0].switch_pin < OMAP_MAX_GPIO_LINES)) | |
728 | omap_mux_init_gpio(mmc_controller->slots[0].switch_pin, | |
729 | OMAP_PIN_INPUT_PULLUP); | |
730 | if ((mmc_controller->slots[0].gpio_wp > 0) && \ | |
731 | (mmc_controller->slots[0].gpio_wp < OMAP_MAX_GPIO_LINES)) | |
732 | omap_mux_init_gpio(mmc_controller->slots[0].gpio_wp, | |
733 | OMAP_PIN_INPUT_PULLUP); | |
734 | ||
d8874665 | 735 | if (cpu_is_omap2420() && controller_nr == 0) { |
f99bf16d TL |
736 | omap_mux_init_signal("sdmmc_cmd", 0); |
737 | omap_mux_init_signal("sdmmc_clki", 0); | |
738 | omap_mux_init_signal("sdmmc_clko", 0); | |
739 | omap_mux_init_signal("sdmmc_dat0", 0); | |
740 | omap_mux_init_signal("sdmmc_dat_dir0", 0); | |
741 | omap_mux_init_signal("sdmmc_cmd_dir", 0); | |
3a63833e | 742 | if (mmc_controller->slots[0].caps & MMC_CAP_4_BIT_DATA) { |
f99bf16d TL |
743 | omap_mux_init_signal("sdmmc_dat1", 0); |
744 | omap_mux_init_signal("sdmmc_dat2", 0); | |
745 | omap_mux_init_signal("sdmmc_dat3", 0); | |
746 | omap_mux_init_signal("sdmmc_dat_dir1", 0); | |
747 | omap_mux_init_signal("sdmmc_dat_dir2", 0); | |
748 | omap_mux_init_signal("sdmmc_dat_dir3", 0); | |
d8874665 TL |
749 | } |
750 | ||
751 | /* | |
752 | * Use internal loop-back in MMC/SDIO Module Input Clock | |
753 | * selection | |
754 | */ | |
755 | if (mmc_controller->slots[0].internal_clock) { | |
756 | u32 v = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0); | |
757 | v |= (1 << 24); | |
758 | omap_ctrl_writel(v, OMAP2_CONTROL_DEVCONF0); | |
759 | } | |
760 | } | |
57b9daa0 | 761 | |
4596d14a | 762 | if (cpu_is_omap34xx()) { |
57b9daa0 | 763 | if (controller_nr == 0) { |
4896e394 TL |
764 | omap_mux_init_signal("sdmmc1_clk", |
765 | OMAP_PIN_INPUT_PULLUP); | |
766 | omap_mux_init_signal("sdmmc1_cmd", | |
767 | OMAP_PIN_INPUT_PULLUP); | |
768 | omap_mux_init_signal("sdmmc1_dat0", | |
769 | OMAP_PIN_INPUT_PULLUP); | |
3a63833e SG |
770 | if (mmc_controller->slots[0].caps & |
771 | (MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA)) { | |
4896e394 TL |
772 | omap_mux_init_signal("sdmmc1_dat1", |
773 | OMAP_PIN_INPUT_PULLUP); | |
774 | omap_mux_init_signal("sdmmc1_dat2", | |
775 | OMAP_PIN_INPUT_PULLUP); | |
776 | omap_mux_init_signal("sdmmc1_dat3", | |
777 | OMAP_PIN_INPUT_PULLUP); | |
57b9daa0 | 778 | } |
3a63833e SG |
779 | if (mmc_controller->slots[0].caps & |
780 | MMC_CAP_8_BIT_DATA) { | |
4896e394 TL |
781 | omap_mux_init_signal("sdmmc1_dat4", |
782 | OMAP_PIN_INPUT_PULLUP); | |
783 | omap_mux_init_signal("sdmmc1_dat5", | |
784 | OMAP_PIN_INPUT_PULLUP); | |
785 | omap_mux_init_signal("sdmmc1_dat6", | |
786 | OMAP_PIN_INPUT_PULLUP); | |
787 | omap_mux_init_signal("sdmmc1_dat7", | |
788 | OMAP_PIN_INPUT_PULLUP); | |
57b9daa0 VP |
789 | } |
790 | } | |
791 | if (controller_nr == 1) { | |
792 | /* MMC2 */ | |
4896e394 TL |
793 | omap_mux_init_signal("sdmmc2_clk", |
794 | OMAP_PIN_INPUT_PULLUP); | |
795 | omap_mux_init_signal("sdmmc2_cmd", | |
796 | OMAP_PIN_INPUT_PULLUP); | |
797 | omap_mux_init_signal("sdmmc2_dat0", | |
798 | OMAP_PIN_INPUT_PULLUP); | |
57b9daa0 VP |
799 | |
800 | /* | |
801 | * For 8 wire configurations, Lines DAT4, 5, 6 and 7 need to be muxed | |
802 | * in the board-*.c files | |
803 | */ | |
3a63833e SG |
804 | if (mmc_controller->slots[0].caps & |
805 | (MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA)) { | |
4896e394 TL |
806 | omap_mux_init_signal("sdmmc2_dat1", |
807 | OMAP_PIN_INPUT_PULLUP); | |
808 | omap_mux_init_signal("sdmmc2_dat2", | |
809 | OMAP_PIN_INPUT_PULLUP); | |
810 | omap_mux_init_signal("sdmmc2_dat3", | |
811 | OMAP_PIN_INPUT_PULLUP); | |
57b9daa0 | 812 | } |
3a63833e SG |
813 | if (mmc_controller->slots[0].caps & |
814 | MMC_CAP_8_BIT_DATA) { | |
4896e394 TL |
815 | omap_mux_init_signal("sdmmc2_dat4.sdmmc2_dat4", |
816 | OMAP_PIN_INPUT_PULLUP); | |
817 | omap_mux_init_signal("sdmmc2_dat5.sdmmc2_dat5", | |
818 | OMAP_PIN_INPUT_PULLUP); | |
819 | omap_mux_init_signal("sdmmc2_dat6.sdmmc2_dat6", | |
820 | OMAP_PIN_INPUT_PULLUP); | |
821 | omap_mux_init_signal("sdmmc2_dat7.sdmmc2_dat7", | |
822 | OMAP_PIN_INPUT_PULLUP); | |
4679232d | 823 | } |
57b9daa0 VP |
824 | } |
825 | ||
826 | /* | |
827 | * For MMC3 the pins need to be muxed in the board-*.c files | |
828 | */ | |
829 | } | |
d8874665 TL |
830 | } |
831 | ||
832 | void __init omap2_init_mmc(struct omap_mmc_platform_data **mmc_data, | |
833 | int nr_controllers) | |
834 | { | |
835 | int i; | |
0dffb5c5 | 836 | char *name; |
d8874665 TL |
837 | |
838 | for (i = 0; i < nr_controllers; i++) { | |
839 | unsigned long base, size; | |
840 | unsigned int irq = 0; | |
841 | ||
842 | if (!mmc_data[i]) | |
843 | continue; | |
844 | ||
845 | omap2_mmc_mux(mmc_data[i], i); | |
846 | ||
847 | switch (i) { | |
848 | case 0: | |
849 | base = OMAP2_MMC1_BASE; | |
850 | irq = INT_24XX_MMC_IRQ; | |
851 | break; | |
852 | case 1: | |
853 | base = OMAP2_MMC2_BASE; | |
854 | irq = INT_24XX_MMC2_IRQ; | |
855 | break; | |
856 | case 2: | |
82cf818d | 857 | if (!cpu_is_omap44xx() && !cpu_is_omap34xx()) |
d8874665 TL |
858 | return; |
859 | base = OMAP3_MMC3_BASE; | |
860 | irq = INT_34XX_MMC3_IRQ; | |
861 | break; | |
82cf818d | 862 | case 3: |
863 | if (!cpu_is_omap44xx()) | |
864 | return; | |
91a0b089 | 865 | base = OMAP4_MMC4_BASE; |
5772ca7d | 866 | irq = OMAP44XX_IRQ_MMC4; |
82cf818d | 867 | break; |
868 | case 4: | |
869 | if (!cpu_is_omap44xx()) | |
870 | return; | |
91a0b089 | 871 | base = OMAP4_MMC5_BASE; |
9df76b7f | 872 | irq = OMAP44XX_IRQ_MMC5; |
82cf818d | 873 | break; |
d8874665 TL |
874 | default: |
875 | continue; | |
876 | } | |
877 | ||
0dffb5c5 | 878 | if (cpu_is_omap2420()) { |
d8874665 | 879 | size = OMAP2420_MMC_SIZE; |
0dffb5c5 | 880 | name = "mmci-omap"; |
82cf818d | 881 | } else if (cpu_is_omap44xx()) { |
91a0b089 | 882 | if (i < 3) |
5772ca7d | 883 | irq += OMAP44XX_IRQ_GIC_START; |
82cf818d | 884 | size = OMAP4_HSMMC_SIZE; |
885 | name = "mmci-omap-hs"; | |
0dffb5c5 | 886 | } else { |
82cf818d | 887 | size = OMAP3_HSMMC_SIZE; |
0dffb5c5 TL |
888 | name = "mmci-omap-hs"; |
889 | } | |
890 | omap_mmc_add(name, i, base, size, irq, mmc_data[i]); | |
d8874665 TL |
891 | }; |
892 | } | |
893 | ||
894 | #endif | |
895 | ||
896 | /*-------------------------------------------------------------------------*/ | |
897 | ||
646e3ed1 TL |
898 | #if defined(CONFIG_HDQ_MASTER_OMAP) || defined(CONFIG_HDQ_MASTER_OMAP_MODULE) |
899 | #if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3430) | |
900 | #define OMAP_HDQ_BASE 0x480B2000 | |
901 | #endif | |
902 | static struct resource omap_hdq_resources[] = { | |
903 | { | |
904 | .start = OMAP_HDQ_BASE, | |
905 | .end = OMAP_HDQ_BASE + 0x1C, | |
906 | .flags = IORESOURCE_MEM, | |
907 | }, | |
908 | { | |
909 | .start = INT_24XX_HDQ_IRQ, | |
910 | .flags = IORESOURCE_IRQ, | |
911 | }, | |
912 | }; | |
913 | static struct platform_device omap_hdq_dev = { | |
914 | .name = "omap_hdq", | |
915 | .id = 0, | |
916 | .dev = { | |
917 | .platform_data = NULL, | |
918 | }, | |
919 | .num_resources = ARRAY_SIZE(omap_hdq_resources), | |
920 | .resource = omap_hdq_resources, | |
921 | }; | |
922 | static inline void omap_hdq_init(void) | |
923 | { | |
924 | (void) platform_device_register(&omap_hdq_dev); | |
925 | } | |
926 | #else | |
927 | static inline void omap_hdq_init(void) {} | |
928 | #endif | |
929 | ||
b227358d VH |
930 | /*---------------------------------------------------------------------------*/ |
931 | ||
932 | #if defined(CONFIG_VIDEO_OMAP2_VOUT) || \ | |
933 | defined(CONFIG_VIDEO_OMAP2_VOUT_MODULE) | |
934 | #if defined(CONFIG_FB_OMAP2) || defined(CONFIG_FB_OMAP2_MODULE) | |
935 | static struct resource omap_vout_resource[3 - CONFIG_FB_OMAP2_NUM_FBS] = { | |
936 | }; | |
937 | #else | |
938 | static struct resource omap_vout_resource[2] = { | |
939 | }; | |
940 | #endif | |
941 | ||
942 | static struct platform_device omap_vout_device = { | |
943 | .name = "omap_vout", | |
944 | .num_resources = ARRAY_SIZE(omap_vout_resource), | |
945 | .resource = &omap_vout_resource[0], | |
946 | .id = -1, | |
947 | }; | |
948 | static void omap_init_vout(void) | |
949 | { | |
950 | if (platform_device_register(&omap_vout_device) < 0) | |
951 | printk(KERN_ERR "Unable to register OMAP-VOUT device\n"); | |
952 | } | |
953 | #else | |
954 | static inline void omap_init_vout(void) {} | |
955 | #endif | |
956 | ||
1dbae815 TL |
957 | /*-------------------------------------------------------------------------*/ |
958 | ||
20252d46 C |
959 | static int omap2_disable_wdt(struct omap_hwmod *oh, void *unused) |
960 | { | |
81fbc5ef | 961 | return omap2_wd_timer_disable(oh); |
20252d46 C |
962 | } |
963 | ||
964 | static void __init omap_disable_wdt(void) | |
965 | { | |
966 | if (cpu_class_is_omap2()) | |
967 | omap_hwmod_for_each_by_class("wd_timer", | |
81fbc5ef | 968 | omap2_disable_wdt, NULL); |
20252d46 C |
969 | return; |
970 | } | |
971 | ||
1dbae815 TL |
972 | static int __init omap2_init_devices(void) |
973 | { | |
81fbc5ef PW |
974 | /* |
975 | * please keep these calls, and their implementations above, | |
1dbae815 TL |
976 | * in alphabetical order so they're easier to sort through. |
977 | */ | |
20252d46 | 978 | omap_disable_wdt(); |
917fa280 | 979 | omap_hsmmc_reset(); |
f0fba2ad | 980 | omap_init_audio(); |
828c707e | 981 | omap_init_camera(); |
c40fae95 | 982 | omap_init_mbox(); |
ed7eb9d9 | 983 | omap_init_mcspi(); |
88341334 | 984 | omap_init_pmu(); |
646e3ed1 | 985 | omap_hdq_init(); |
9b6553cd | 986 | omap_init_sti(); |
ee5500c4 | 987 | omap_init_sham(); |
b744c679 | 988 | omap_init_aes(); |
b227358d | 989 | omap_init_vout(); |
1dbae815 TL |
990 | |
991 | return 0; | |
992 | } | |
993 | arch_initcall(omap2_init_devices); | |
f2ce6231 VC |
994 | |
995 | #if defined(CONFIG_OMAP_WATCHDOG) || defined(CONFIG_OMAP_WATCHDOG_MODULE) | |
996 | struct omap_device_pm_latency omap_wdt_latency[] = { | |
997 | [0] = { | |
998 | .deactivate_func = omap_device_idle_hwmods, | |
999 | .activate_func = omap_device_enable_hwmods, | |
1000 | .flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST, | |
1001 | }, | |
1002 | }; | |
1003 | ||
1004 | static int __init omap_init_wdt(void) | |
1005 | { | |
1006 | int id = -1; | |
1007 | struct omap_device *od; | |
1008 | struct omap_hwmod *oh; | |
1009 | char *oh_name = "wd_timer2"; | |
1010 | char *dev_name = "omap_wdt"; | |
1011 | ||
1012 | if (!cpu_class_is_omap2()) | |
1013 | return 0; | |
1014 | ||
1015 | oh = omap_hwmod_lookup(oh_name); | |
1016 | if (!oh) { | |
1017 | pr_err("Could not look up wd_timer%d hwmod\n", id); | |
1018 | return -EINVAL; | |
1019 | } | |
1020 | ||
1021 | od = omap_device_build(dev_name, id, oh, NULL, 0, | |
1022 | omap_wdt_latency, | |
1023 | ARRAY_SIZE(omap_wdt_latency), 0); | |
1024 | WARN(IS_ERR(od), "Cant build omap_device for %s:%s.\n", | |
1025 | dev_name, oh->name); | |
1026 | return 0; | |
1027 | } | |
1028 | subsys_initcall(omap_init_wdt); | |
1029 | #endif |