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[media] omap3: Remove unusued ISP CBUFF resource
[deliverable/linux.git] / arch / arm / mach-omap2 / devices.c
CommitLineData
1dbae815
TL		 1/*
2 * linux/arch/arm/mach-omap2/devices.c
3 *
4 * OMAP2 platform device setup/initialization
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 */
11
1dbae815
TL		 12#include <linux/kernel.h>
13#include <linux/init.h>
14#include <linux/platform_device.h>
fced80c7 15#include <linux/io.h>
917fa280 16#include <linux/clk.h>
f2ce6231 17#include <linux/err.h>
1dbae815 18
a09e64fb 19#include <mach/hardware.h>
88341334 20#include <mach/irqs.h>
1dbae815
TL		 21#include <asm/mach-types.h>
22#include <asm/mach/map.h>
88341334 23#include <asm/pmu.h>
1dbae815 24
ce491cf8
TL		 25#include <plat/tc.h>
26#include <plat/board.h>
a09f73fa 27#include <plat/mcbsp.h>
a09e64fb 28#include <mach/gpio.h>
ce491cf8 29#include <plat/mmc.h>
ee5500c4 30#include <plat/dma.h>
f2ce6231
VC		 31#include <plat/omap_hwmod.h>
32#include <plat/omap_device.h>
1dbae815 33
4896e394 34#include "mux.h"
4814ced5 35#include "control.h"
4896e394 36
828c707e 37#if defined(CONFIG_VIDEO_OMAP2) || defined(CONFIG_VIDEO_OMAP2_MODULE)
c40fae95 38
828c707e 39static struct resource cam_resources[] = {
c40fae95 40 {
828c707e
TL		 41 .start = OMAP24XX_CAMERA_BASE,
42 .end = OMAP24XX_CAMERA_BASE + 0xfff,
43 .flags = IORESOURCE_MEM,
44 },
45 {
46 .start = INT_24XX_CAM_IRQ,
47 .flags = IORESOURCE_IRQ,
48 }
49};
50
51static struct platform_device omap_cam_device = {
52 .name = "omap24xxcam",
53 .id = -1,
54 .num_resources = ARRAY_SIZE(cam_resources),
55 .resource = cam_resources,
56};
57
58static inline void omap_init_camera(void)
59{
60 platform_device_register(&omap_cam_device);
61}
62
63#elif defined(CONFIG_VIDEO_OMAP3) || defined(CONFIG_VIDEO_OMAP3_MODULE)
64
65static struct resource omap3isp_resources[] = {
66 {
67 .start = OMAP3430_ISP_BASE,
68 .end = OMAP3430_ISP_END,
69 .flags = IORESOURCE_MEM,
70 },
828c707e
TL		 71 {
72 .start = OMAP3430_ISP_CCP2_BASE,
73 .end = OMAP3430_ISP_CCP2_END,
74 .flags = IORESOURCE_MEM,
75 },
76 {
77 .start = OMAP3430_ISP_CCDC_BASE,
78 .end = OMAP3430_ISP_CCDC_END,
79 .flags = IORESOURCE_MEM,
80 },
81 {
82 .start = OMAP3430_ISP_HIST_BASE,
83 .end = OMAP3430_ISP_HIST_END,
84 .flags = IORESOURCE_MEM,
85 },
86 {
87 .start = OMAP3430_ISP_H3A_BASE,
88 .end = OMAP3430_ISP_H3A_END,
89 .flags = IORESOURCE_MEM,
90 },
91 {
92 .start = OMAP3430_ISP_PREV_BASE,
93 .end = OMAP3430_ISP_PREV_END,
94 .flags = IORESOURCE_MEM,
95 },
96 {
97 .start = OMAP3430_ISP_RESZ_BASE,
98 .end = OMAP3430_ISP_RESZ_END,
99 .flags = IORESOURCE_MEM,
100 },
101 {
102 .start = OMAP3430_ISP_SBL_BASE,
103 .end = OMAP3430_ISP_SBL_END,
104 .flags = IORESOURCE_MEM,
105 },
106 {
6817a69a
TT		 107 .start = OMAP3430_ISP_CSI2A_REGS1_BASE,
108 .end = OMAP3430_ISP_CSI2A_REGS1_END,
828c707e
TL		 109 .flags = IORESOURCE_MEM,
110 },
111 {
6817a69a
TT		 112 .start = OMAP3430_ISP_CSIPHY2_BASE,
113 .end = OMAP3430_ISP_CSIPHY2_END,
114 .flags = IORESOURCE_MEM,
115 },
116 {
117 .start = OMAP3630_ISP_CSI2A_REGS2_BASE,
118 .end = OMAP3630_ISP_CSI2A_REGS2_END,
119 .flags = IORESOURCE_MEM,
120 },
121 {
122 .start = OMAP3630_ISP_CSI2C_REGS1_BASE,
123 .end = OMAP3630_ISP_CSI2C_REGS1_END,
124 .flags = IORESOURCE_MEM,
125 },
126 {
127 .start = OMAP3630_ISP_CSIPHY1_BASE,
128 .end = OMAP3630_ISP_CSIPHY1_END,
129 .flags = IORESOURCE_MEM,
130 },
131 {
132 .start = OMAP3630_ISP_CSI2C_REGS2_BASE,
133 .end = OMAP3630_ISP_CSI2C_REGS2_END,
828c707e
TL		 134 .flags = IORESOURCE_MEM,
135 },
136 {
137 .start = INT_34XX_CAM_IRQ,
138 .flags = IORESOURCE_IRQ,
139 }
140};
141
142static struct platform_device omap3isp_device = {
143 .name = "omap3isp",
144 .id = -1,
145 .num_resources = ARRAY_SIZE(omap3isp_resources),
146 .resource = omap3isp_resources,
147};
148
149static inline void omap_init_camera(void)
150{
151 platform_device_register(&omap3isp_device);
152}
153#else
154static inline void omap_init_camera(void)
155{
156}
157#endif
158
6c20a683 159#if defined(CONFIG_OMAP_MBOX_FWK) || defined(CONFIG_OMAP_MBOX_FWK_MODULE)
c40fae95 160
454bf340 161#define MBOX_REG_SIZE 0x120
6c20a683 162
454bf340 163#ifdef CONFIG_ARCH_OMAP2
d10f2b6e 164static struct resource omap2_mbox_resources[] = {
c40fae95 165 {
6c20a683
HD		 166 .start = OMAP24XX_MAILBOX_BASE,
167 .end = OMAP24XX_MAILBOX_BASE + MBOX_REG_SIZE - 1,
c40fae95
TL		 168 .flags = IORESOURCE_MEM,
169 },
170 {
171 .start = INT_24XX_MAIL_U0_MPU,
172 .flags = IORESOURCE_IRQ,
1f2c4dfd 173 .name = "dsp",
c40fae95
TL		 174 },
175 {
176 .start = INT_24XX_MAIL_U3_MPU,
177 .flags = IORESOURCE_IRQ,
1f2c4dfd 178 .name = "iva",
c40fae95
TL		 179 },
180};
d10f2b6e
TL		 181static int omap2_mbox_resources_sz = ARRAY_SIZE(omap2_mbox_resources);
182#else
183#define omap2_mbox_resources NULL
184#define omap2_mbox_resources_sz 0
454bf340 185#endif
c40fae95 186
454bf340 187#ifdef CONFIG_ARCH_OMAP3
d10f2b6e 188static struct resource omap3_mbox_resources[] = {
6c20a683
HD		 189 {
190 .start = OMAP34XX_MAILBOX_BASE,
191 .end = OMAP34XX_MAILBOX_BASE + MBOX_REG_SIZE - 1,
192 .flags = IORESOURCE_MEM,
193 },
194 {
195 .start = INT_24XX_MAIL_U0_MPU,
196 .flags = IORESOURCE_IRQ,
1f2c4dfd 197 .name = "dsp",
6c20a683
HD		 198 },
199};
d10f2b6e
TL		 200static int omap3_mbox_resources_sz = ARRAY_SIZE(omap3_mbox_resources);
201#else
202#define omap3_mbox_resources NULL
203#define omap3_mbox_resources_sz 0
454bf340
S		 204#endif
205
206#ifdef CONFIG_ARCH_OMAP4
207
208#define OMAP4_MBOX_REG_SIZE 0x130
d10f2b6e 209static struct resource omap4_mbox_resources[] = {
454bf340
S		 210 {
211 .start = OMAP44XX_MAILBOX_BASE,
212 .end = OMAP44XX_MAILBOX_BASE +
213 OMAP4_MBOX_REG_SIZE - 1,
214 .flags = IORESOURCE_MEM,
215 },
216 {
5772ca7d 217 .start = OMAP44XX_IRQ_MAIL_U0,
454bf340 218 .flags = IORESOURCE_IRQ,
1f2c4dfd 219 .name = "mbox",
454bf340
S		 220 },
221};
d10f2b6e
TL		 222static int omap4_mbox_resources_sz = ARRAY_SIZE(omap4_mbox_resources);
223#else
224#define omap4_mbox_resources NULL
225#define omap4_mbox_resources_sz 0
454bf340 226#endif
6c20a683 227
c40fae95 228static struct platform_device mbox_device = {
d742709e 229 .name = "omap-mailbox",
c40fae95 230 .id = -1,
c40fae95
TL		 231};
232
233static inline void omap_init_mbox(void)
234{
d10f2b6e
TL		 235 if (cpu_is_omap24xx()) {
236 mbox_device.resource = omap2_mbox_resources;
237 mbox_device.num_resources = omap2_mbox_resources_sz;
238 } else if (cpu_is_omap34xx()) {
239 mbox_device.resource = omap3_mbox_resources;
240 mbox_device.num_resources = omap3_mbox_resources_sz;
241 } else if (cpu_is_omap44xx()) {
242 mbox_device.resource = omap4_mbox_resources;
243 mbox_device.num_resources = omap4_mbox_resources_sz;
6c20a683
HD		 244 } else {
245 pr_err("%s: platform not supported\n", __func__);
246 return;
247 }
c40fae95
TL		 248 platform_device_register(&mbox_device);
249}
250#else
251static inline void omap_init_mbox(void) { }
6c20a683 252#endif /* CONFIG_OMAP_MBOX_FWK */
c40fae95 253
9b6553cd 254static inline void omap_init_sti(void) {}
9b6553cd 255
f0fba2ad
LG		 256#if defined(CONFIG_SND_SOC) || defined(CONFIG_SND_SOC_MODULE)
257
258static struct platform_device omap_pcm = {
259 .name = "omap-pcm-audio",
260 .id = -1,
261};
262
263/*
264 * OMAP2420 has 2 McBSP ports
265 * OMAP2430 has 5 McBSP ports
266 * OMAP3 has 5 McBSP ports
267 * OMAP4 has 4 McBSP ports
268 */
269OMAP_MCBSP_PLATFORM_DEVICE(1);
270OMAP_MCBSP_PLATFORM_DEVICE(2);
271OMAP_MCBSP_PLATFORM_DEVICE(3);
272OMAP_MCBSP_PLATFORM_DEVICE(4);
273OMAP_MCBSP_PLATFORM_DEVICE(5);
274
275static void omap_init_audio(void)
276{
277 platform_device_register(&omap_mcbsp1);
278 platform_device_register(&omap_mcbsp2);
279 if (cpu_is_omap243x() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
280 platform_device_register(&omap_mcbsp3);
281 platform_device_register(&omap_mcbsp4);
282 }
283 if (cpu_is_omap243x() || cpu_is_omap34xx())
284 platform_device_register(&omap_mcbsp5);
285
286 platform_device_register(&omap_pcm);
287}
288
289#else
290static inline void omap_init_audio(void) {}
291#endif
292
646e3ed1 293#if defined(CONFIG_SPI_OMAP24XX) || defined(CONFIG_SPI_OMAP24XX_MODULE)
ed7eb9d9 294
ce491cf8 295#include <plat/mcspi.h>
ed7eb9d9
JY		 296
297#define OMAP2_MCSPI1_BASE 0x48098000
298#define OMAP2_MCSPI2_BASE 0x4809a000
646e3ed1
TL		 299#define OMAP2_MCSPI3_BASE 0x480b8000
300#define OMAP2_MCSPI4_BASE 0x480ba000
ed7eb9d9 301
7869c0b9
SR		 302#define OMAP4_MCSPI1_BASE 0x48098100
303#define OMAP4_MCSPI2_BASE 0x4809a100
304#define OMAP4_MCSPI3_BASE 0x480b8100
305#define OMAP4_MCSPI4_BASE 0x480ba100
306
ed7eb9d9 307static struct omap2_mcspi_platform_config omap2_mcspi1_config = {
ed7eb9d9
JY		 308 .num_cs = 4,
309};
310
c40fae95
TL		 311static struct resource omap2_mcspi1_resources[] = {
312 {
313 .start = OMAP2_MCSPI1_BASE,
314 .end = OMAP2_MCSPI1_BASE + 0xff,
315 .flags = IORESOURCE_MEM,
316 },
317};
318
646e3ed1 319static struct platform_device omap2_mcspi1 = {
ed7eb9d9
JY		 320 .name = "omap2_mcspi",
321 .id = 1,
c40fae95
TL		 322 .num_resources = ARRAY_SIZE(omap2_mcspi1_resources),
323 .resource = omap2_mcspi1_resources,
ed7eb9d9
JY		 324 .dev = {
325 .platform_data = &omap2_mcspi1_config,
326 },
327};
328
329static struct omap2_mcspi_platform_config omap2_mcspi2_config = {
ed7eb9d9
JY		 330 .num_cs = 2,
331};
332
c40fae95
TL		 333static struct resource omap2_mcspi2_resources[] = {
334 {
335 .start = OMAP2_MCSPI2_BASE,
336 .end = OMAP2_MCSPI2_BASE + 0xff,
337 .flags = IORESOURCE_MEM,
338 },
339};
340
646e3ed1 341static struct platform_device omap2_mcspi2 = {
ed7eb9d9
JY		 342 .name = "omap2_mcspi",
343 .id = 2,
c40fae95
TL		 344 .num_resources = ARRAY_SIZE(omap2_mcspi2_resources),
345 .resource = omap2_mcspi2_resources,
ed7eb9d9
JY		 346 .dev = {
347 .platform_data = &omap2_mcspi2_config,
348 },
349};
350
7869c0b9
SR		 351#if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3) || \
352 defined(CONFIG_ARCH_OMAP4)
646e3ed1
TL		 353static struct omap2_mcspi_platform_config omap2_mcspi3_config = {
354 .num_cs = 2,
355};
356
357static struct resource omap2_mcspi3_resources[] = {
358 {
359 .start = OMAP2_MCSPI3_BASE,
360 .end = OMAP2_MCSPI3_BASE + 0xff,
361 .flags = IORESOURCE_MEM,
362 },
363};
364
365static struct platform_device omap2_mcspi3 = {
366 .name = "omap2_mcspi",
367 .id = 3,
368 .num_resources = ARRAY_SIZE(omap2_mcspi3_resources),
369 .resource = omap2_mcspi3_resources,
370 .dev = {
371 .platform_data = &omap2_mcspi3_config,
372 },
373};
374#endif
375
7869c0b9 376#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
646e3ed1
TL		 377static struct omap2_mcspi_platform_config omap2_mcspi4_config = {
378 .num_cs = 1,
379};
380
381static struct resource omap2_mcspi4_resources[] = {
382 {
383 .start = OMAP2_MCSPI4_BASE,
384 .end = OMAP2_MCSPI4_BASE + 0xff,
385 .flags = IORESOURCE_MEM,
386 },
387};
388
389static struct platform_device omap2_mcspi4 = {
390 .name = "omap2_mcspi",
391 .id = 4,
392 .num_resources = ARRAY_SIZE(omap2_mcspi4_resources),
393 .resource = omap2_mcspi4_resources,
394 .dev = {
395 .platform_data = &omap2_mcspi4_config,
396 },
397};
398#endif
399
af41a12f
TL		 400#ifdef CONFIG_ARCH_OMAP4
401static inline void omap4_mcspi_fixup(void)
ed7eb9d9 402{
af41a12f
TL		 403 omap2_mcspi1_resources[0].start = OMAP4_MCSPI1_BASE;
404 omap2_mcspi1_resources[0].end = OMAP4_MCSPI1_BASE + 0xff;
405 omap2_mcspi2_resources[0].start = OMAP4_MCSPI2_BASE;
406 omap2_mcspi2_resources[0].end = OMAP4_MCSPI2_BASE + 0xff;
407 omap2_mcspi3_resources[0].start = OMAP4_MCSPI3_BASE;
408 omap2_mcspi3_resources[0].end = OMAP4_MCSPI3_BASE + 0xff;
409 omap2_mcspi4_resources[0].start = OMAP4_MCSPI4_BASE;
410 omap2_mcspi4_resources[0].end = OMAP4_MCSPI4_BASE + 0xff;
411}
412#else
413static inline void omap4_mcspi_fixup(void)
414{
415}
416#endif
417
7869c0b9
SR		 418#if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3) || \
419 defined(CONFIG_ARCH_OMAP4)
af41a12f
TL		 420static inline void omap2_mcspi3_init(void)
421{
422 platform_device_register(&omap2_mcspi3);
423}
424#else
425static inline void omap2_mcspi3_init(void)
426{
427}
646e3ed1 428#endif
af41a12f 429
7869c0b9 430#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
af41a12f
TL		 431static inline void omap2_mcspi4_init(void)
432{
433 platform_device_register(&omap2_mcspi4);
434}
435#else
436static inline void omap2_mcspi4_init(void)
437{
438}
646e3ed1 439#endif
af41a12f
TL		 440
441static void omap_init_mcspi(void)
442{
443 if (cpu_is_omap44xx())
444 omap4_mcspi_fixup();
445
446 platform_device_register(&omap2_mcspi1);
447 platform_device_register(&omap2_mcspi2);
448
449 if (cpu_is_omap2430() || cpu_is_omap343x() || cpu_is_omap44xx())
450 omap2_mcspi3_init();
451
452 if (cpu_is_omap343x() || cpu_is_omap44xx())
453 omap2_mcspi4_init();
ed7eb9d9
JY		 454}
455
456#else
457static inline void omap_init_mcspi(void) {}
458#endif
459
88341334
WD		 460static struct resource omap2_pmu_resource = {
461 .start = 3,
462 .end = 3,
463 .flags = IORESOURCE_IRQ,
464};
465
466static struct resource omap3_pmu_resource = {
467 .start = INT_34XX_BENCH_MPU_EMUL,
468 .end = INT_34XX_BENCH_MPU_EMUL,
469 .flags = IORESOURCE_IRQ,
470};
471
472static struct platform_device omap_pmu_device = {
473 .name = "arm-pmu",
474 .id = ARM_PMU_DEVICE_CPU,
475 .num_resources = 1,
476};
477
478static void omap_init_pmu(void)
479{
480 if (cpu_is_omap24xx())
481 omap_pmu_device.resource = &omap2_pmu_resource;
482 else if (cpu_is_omap34xx())
483 omap_pmu_device.resource = &omap3_pmu_resource;
484 else
485 return;
486
487 platform_device_register(&omap_pmu_device);
488}
489
490
ee5500c4
DK		 491#if defined(CONFIG_CRYPTO_DEV_OMAP_SHAM) || defined(CONFIG_CRYPTO_DEV_OMAP_SHAM_MODULE)
492
edc774ed 493#ifdef CONFIG_ARCH_OMAP2
ee5500c4 494static struct resource omap2_sham_resources[] = {
646e3ed1
TL		 495 {
496 .start = OMAP24XX_SEC_SHA1MD5_BASE,
497 .end = OMAP24XX_SEC_SHA1MD5_BASE + 0x64,
498 .flags = IORESOURCE_MEM,
499 },
500 {
501 .start = INT_24XX_SHA1MD5,
502 .flags = IORESOURCE_IRQ,
503 }
504};
ee5500c4
DK		 505static int omap2_sham_resources_sz = ARRAY_SIZE(omap2_sham_resources);
506#else
507#define omap2_sham_resources NULL
508#define omap2_sham_resources_sz 0
509#endif
646e3ed1 510
edc774ed 511#ifdef CONFIG_ARCH_OMAP3
ee5500c4
DK		 512static struct resource omap3_sham_resources[] = {
513 {
514 .start = OMAP34XX_SEC_SHA1MD5_BASE,
515 .end = OMAP34XX_SEC_SHA1MD5_BASE + 0x64,
516 .flags = IORESOURCE_MEM,
517 },
518 {
519 .start = INT_34XX_SHA1MD52_IRQ,
520 .flags = IORESOURCE_IRQ,
521 },
522 {
523 .start = OMAP34XX_DMA_SHA1MD5_RX,
524 .flags = IORESOURCE_DMA,
525 }
526};
527static int omap3_sham_resources_sz = ARRAY_SIZE(omap3_sham_resources);
528#else
529#define omap3_sham_resources NULL
530#define omap3_sham_resources_sz 0
531#endif
532
533static struct platform_device sham_device = {
534 .name = "omap-sham",
646e3ed1 535 .id = -1,
646e3ed1
TL		 536};
537
ee5500c4 538static void omap_init_sham(void)
646e3ed1 539{
ee5500c4
DK		 540 if (cpu_is_omap24xx()) {
541 sham_device.resource = omap2_sham_resources;
542 sham_device.num_resources = omap2_sham_resources_sz;
543 } else if (cpu_is_omap34xx()) {
544 sham_device.resource = omap3_sham_resources;
545 sham_device.num_resources = omap3_sham_resources_sz;
546 } else {
547 pr_err("%s: platform not supported\n", __func__);
548 return;
549 }
550 platform_device_register(&sham_device);
646e3ed1
TL		 551}
552#else
ee5500c4 553static inline void omap_init_sham(void) { }
646e3ed1
TL		 554#endif
555
b744c679
DK		 556#if defined(CONFIG_CRYPTO_DEV_OMAP_AES) || defined(CONFIG_CRYPTO_DEV_OMAP_AES_MODULE)
557
82a0c149 558#ifdef CONFIG_ARCH_OMAP2
b744c679
DK		 559static struct resource omap2_aes_resources[] = {
560 {
561 .start = OMAP24XX_SEC_AES_BASE,
562 .end = OMAP24XX_SEC_AES_BASE + 0x4C,
563 .flags = IORESOURCE_MEM,
564 },
565 {
566 .start = OMAP24XX_DMA_AES_TX,
567 .flags = IORESOURCE_DMA,
568 },
569 {
570 .start = OMAP24XX_DMA_AES_RX,
571 .flags = IORESOURCE_DMA,
572 }
573};
574static int omap2_aes_resources_sz = ARRAY_SIZE(omap2_aes_resources);
575#else
576#define omap2_aes_resources NULL
577#define omap2_aes_resources_sz 0
578#endif
579
82a0c149 580#ifdef CONFIG_ARCH_OMAP3
b744c679
DK		 581static struct resource omap3_aes_resources[] = {
582 {
583 .start = OMAP34XX_SEC_AES_BASE,
584 .end = OMAP34XX_SEC_AES_BASE + 0x4C,
585 .flags = IORESOURCE_MEM,
586 },
587 {
588 .start = OMAP34XX_DMA_AES2_TX,
589 .flags = IORESOURCE_DMA,
590 },
591 {
592 .start = OMAP34XX_DMA_AES2_RX,
593 .flags = IORESOURCE_DMA,
594 }
595};
596static int omap3_aes_resources_sz = ARRAY_SIZE(omap3_aes_resources);
597#else
598#define omap3_aes_resources NULL
599#define omap3_aes_resources_sz 0
600#endif
601
602static struct platform_device aes_device = {
603 .name = "omap-aes",
604 .id = -1,
605};
606
607static void omap_init_aes(void)
608{
609 if (cpu_is_omap24xx()) {
610 aes_device.resource = omap2_aes_resources;
611 aes_device.num_resources = omap2_aes_resources_sz;
612 } else if (cpu_is_omap34xx()) {
613 aes_device.resource = omap3_aes_resources;
614 aes_device.num_resources = omap3_aes_resources_sz;
615 } else {
616 pr_err("%s: platform not supported\n", __func__);
617 return;
618 }
619 platform_device_register(&aes_device);
620}
621
622#else
623static inline void omap_init_aes(void) { }
624#endif
625
d8874665
TL		 626/*-------------------------------------------------------------------------*/
627
82cf818d 628#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
917fa280
KH		 629
630#define MMCHS_SYSCONFIG 0x0010
631#define MMCHS_SYSCONFIG_SWRESET (1 << 1)
632#define MMCHS_SYSSTATUS 0x0014
633#define MMCHS_SYSSTATUS_RESETDONE (1 << 0)
634
635static struct platform_device dummy_pdev = {
636 .dev = {
637 .bus = &platform_bus_type,
638 },
639};
640
641/**
642 * omap_hsmmc_reset() - Full reset of each HS-MMC controller
643 *
644 * Ensure that each MMC controller is fully reset. Controllers
645 * left in an unknown state (by bootloader) may prevent retention
646 * or OFF-mode. This is especially important in cases where the
647 * MMC driver is not enabled, _or_ built as a module.
648 *
649 * In order for reset to work, interface, functional and debounce
650 * clocks must be enabled. The debounce clock comes from func_32k_clk
651 * and is not under SW control, so we only enable i- and f-clocks.
652 **/
653static void __init omap_hsmmc_reset(void)
654{
4323e9f7 655 u32 i, nr_controllers;
434c23a7 656 struct clk *iclk, *fclk;
4323e9f7
TL		 657
658 if (cpu_is_omap242x())
659 return;
660
661 nr_controllers = cpu_is_omap44xx() ? OMAP44XX_NR_MMC :
82cf818d 662 (cpu_is_omap34xx() ? OMAP34XX_NR_MMC : OMAP24XX_NR_MMC);
917fa280
KH		 663
664 for (i = 0; i < nr_controllers; i++) {
665 u32 v, base = 0;
917fa280
KH		 666 struct device *dev = &dummy_pdev.dev;
667
668 switch (i) {
669 case 0:
670 base = OMAP2_MMC1_BASE;
671 break;
672 case 1:
673 base = OMAP2_MMC2_BASE;
674 break;
675 case 2:
676 base = OMAP3_MMC3_BASE;
677 break;
82cf818d 678 case 3:
679 if (!cpu_is_omap44xx())
680 return;
681 base = OMAP4_MMC4_BASE;
682 break;
683 case 4:
684 if (!cpu_is_omap44xx())
685 return;
686 base = OMAP4_MMC5_BASE;
687 break;
917fa280
KH		 688 }
689
82cf818d 690 if (cpu_is_omap44xx())
691 base += OMAP4_MMC_REG_OFFSET;
692
917fa280 693 dummy_pdev.id = i;
1e98ffa8 694 dev_set_name(&dummy_pdev.dev, "mmci-omap-hs.%d", i);
6f7607cc 695 iclk = clk_get(dev, "ick");
434c23a7
AK		 696 if (IS_ERR(iclk))
697 goto err1;
698 if (clk_enable(iclk))
699 goto err2;
917fa280 700
6f7607cc 701 fclk = clk_get(dev, "fck");
434c23a7
AK		 702 if (IS_ERR(fclk))
703 goto err3;
704 if (clk_enable(fclk))
705 goto err4;
917fa280
KH		 706
707 omap_writel(MMCHS_SYSCONFIG_SWRESET, base + MMCHS_SYSCONFIG);
708 v = omap_readl(base + MMCHS_SYSSTATUS);
709 while (!(omap_readl(base + MMCHS_SYSSTATUS) &
710 MMCHS_SYSSTATUS_RESETDONE))
711 cpu_relax();
712
434c23a7
AK		 713 clk_disable(fclk);
714 clk_put(fclk);
715 clk_disable(iclk);
716 clk_put(iclk);
917fa280 717 }
434c23a7
AK		 718 return;
719
720err4:
721 clk_put(fclk);
722err3:
723 clk_disable(iclk);
724err2:
725 clk_put(iclk);
726err1:
727 printk(KERN_WARNING "%s: Unable to enable clocks for MMC%d, "
728 "cannot reset.\n", __func__, i);
917fa280
KH		 729}
730#else
731static inline void omap_hsmmc_reset(void) {}
732#endif
733
d8874665
TL		 734#if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE) || \
735 defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE)
736
737static inline void omap2_mmc_mux(struct omap_mmc_platform_data *mmc_controller,
738 int controller_nr)
739{
ed8303fc 740 if ((mmc_controller->slots[0].switch_pin > 0) && \
741 (mmc_controller->slots[0].switch_pin < OMAP_MAX_GPIO_LINES))
742 omap_mux_init_gpio(mmc_controller->slots[0].switch_pin,
743 OMAP_PIN_INPUT_PULLUP);
744 if ((mmc_controller->slots[0].gpio_wp > 0) && \
745 (mmc_controller->slots[0].gpio_wp < OMAP_MAX_GPIO_LINES))
746 omap_mux_init_gpio(mmc_controller->slots[0].gpio_wp,
747 OMAP_PIN_INPUT_PULLUP);
748
d8874665 749 if (cpu_is_omap2420() && controller_nr == 0) {
f99bf16d
TL		 750 omap_mux_init_signal("sdmmc_cmd", 0);
751 omap_mux_init_signal("sdmmc_clki", 0);
752 omap_mux_init_signal("sdmmc_clko", 0);
753 omap_mux_init_signal("sdmmc_dat0", 0);
754 omap_mux_init_signal("sdmmc_dat_dir0", 0);
755 omap_mux_init_signal("sdmmc_cmd_dir", 0);
3a63833e 756 if (mmc_controller->slots[0].caps & MMC_CAP_4_BIT_DATA) {
f99bf16d
TL		 757 omap_mux_init_signal("sdmmc_dat1", 0);
758 omap_mux_init_signal("sdmmc_dat2", 0);
759 omap_mux_init_signal("sdmmc_dat3", 0);
760 omap_mux_init_signal("sdmmc_dat_dir1", 0);
761 omap_mux_init_signal("sdmmc_dat_dir2", 0);
762 omap_mux_init_signal("sdmmc_dat_dir3", 0);
d8874665
TL		 763 }
764
765 /*
766 * Use internal loop-back in MMC/SDIO Module Input Clock
767 * selection
768 */
769 if (mmc_controller->slots[0].internal_clock) {
770 u32 v = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
771 v |= (1 << 24);
772 omap_ctrl_writel(v, OMAP2_CONTROL_DEVCONF0);
773 }
774 }
57b9daa0 775
4596d14a 776 if (cpu_is_omap34xx()) {
57b9daa0 777 if (controller_nr == 0) {
4896e394
TL		 778 omap_mux_init_signal("sdmmc1_clk",
779 OMAP_PIN_INPUT_PULLUP);
780 omap_mux_init_signal("sdmmc1_cmd",
781 OMAP_PIN_INPUT_PULLUP);
782 omap_mux_init_signal("sdmmc1_dat0",
783 OMAP_PIN_INPUT_PULLUP);
3a63833e
SG		 784 if (mmc_controller->slots[0].caps &
785 (MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA)) {
4896e394
TL		 786 omap_mux_init_signal("sdmmc1_dat1",
787 OMAP_PIN_INPUT_PULLUP);
788 omap_mux_init_signal("sdmmc1_dat2",
789 OMAP_PIN_INPUT_PULLUP);
790 omap_mux_init_signal("sdmmc1_dat3",
791 OMAP_PIN_INPUT_PULLUP);
57b9daa0 792 }
3a63833e
SG		 793 if (mmc_controller->slots[0].caps &
794 MMC_CAP_8_BIT_DATA) {
4896e394
TL		 795 omap_mux_init_signal("sdmmc1_dat4",
796 OMAP_PIN_INPUT_PULLUP);
797 omap_mux_init_signal("sdmmc1_dat5",
798 OMAP_PIN_INPUT_PULLUP);
799 omap_mux_init_signal("sdmmc1_dat6",
800 OMAP_PIN_INPUT_PULLUP);
801 omap_mux_init_signal("sdmmc1_dat7",
802 OMAP_PIN_INPUT_PULLUP);
57b9daa0
VP		 803 }
804 }
805 if (controller_nr == 1) {
806 /* MMC2 */
4896e394
TL		 807 omap_mux_init_signal("sdmmc2_clk",
808 OMAP_PIN_INPUT_PULLUP);
809 omap_mux_init_signal("sdmmc2_cmd",
810 OMAP_PIN_INPUT_PULLUP);
811 omap_mux_init_signal("sdmmc2_dat0",
812 OMAP_PIN_INPUT_PULLUP);
57b9daa0
VP		 813
814 /*
815 * For 8 wire configurations, Lines DAT4, 5, 6 and 7 need to be muxed
816 * in the board-*.c files
817 */
3a63833e
SG		 818 if (mmc_controller->slots[0].caps &
819 (MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA)) {
4896e394
TL		 820 omap_mux_init_signal("sdmmc2_dat1",
821 OMAP_PIN_INPUT_PULLUP);
822 omap_mux_init_signal("sdmmc2_dat2",
823 OMAP_PIN_INPUT_PULLUP);
824 omap_mux_init_signal("sdmmc2_dat3",
825 OMAP_PIN_INPUT_PULLUP);
57b9daa0 826 }
3a63833e
SG		 827 if (mmc_controller->slots[0].caps &
828 MMC_CAP_8_BIT_DATA) {
4896e394
TL		 829 omap_mux_init_signal("sdmmc2_dat4.sdmmc2_dat4",
830 OMAP_PIN_INPUT_PULLUP);
831 omap_mux_init_signal("sdmmc2_dat5.sdmmc2_dat5",
832 OMAP_PIN_INPUT_PULLUP);
833 omap_mux_init_signal("sdmmc2_dat6.sdmmc2_dat6",
834 OMAP_PIN_INPUT_PULLUP);
835 omap_mux_init_signal("sdmmc2_dat7.sdmmc2_dat7",
836 OMAP_PIN_INPUT_PULLUP);
4679232d 837 }
57b9daa0
VP		 838 }
839
840 /*
841 * For MMC3 the pins need to be muxed in the board-*.c files
842 */
843 }
d8874665
TL		 844}
845
846void __init omap2_init_mmc(struct omap_mmc_platform_data **mmc_data,
847 int nr_controllers)
848{
849 int i;
0dffb5c5 850 char *name;
d8874665
TL		 851
852 for (i = 0; i < nr_controllers; i++) {
853 unsigned long base, size;
854 unsigned int irq = 0;
855
856 if (!mmc_data[i])
857 continue;
858
859 omap2_mmc_mux(mmc_data[i], i);
860
861 switch (i) {
862 case 0:
863 base = OMAP2_MMC1_BASE;
864 irq = INT_24XX_MMC_IRQ;
865 break;
866 case 1:
867 base = OMAP2_MMC2_BASE;
868 irq = INT_24XX_MMC2_IRQ;
869 break;
870 case 2:
82cf818d 871 if (!cpu_is_omap44xx() && !cpu_is_omap34xx())
d8874665
TL		 872 return;
873 base = OMAP3_MMC3_BASE;
874 irq = INT_34XX_MMC3_IRQ;
875 break;
82cf818d 876 case 3:
877 if (!cpu_is_omap44xx())
878 return;
91a0b089 879 base = OMAP4_MMC4_BASE;
5772ca7d 880 irq = OMAP44XX_IRQ_MMC4;
82cf818d 881 break;
882 case 4:
883 if (!cpu_is_omap44xx())
884 return;
91a0b089 885 base = OMAP4_MMC5_BASE;
9df76b7f 886 irq = OMAP44XX_IRQ_MMC5;
82cf818d 887 break;
d8874665
TL		 888 default:
889 continue;
890 }
891
0dffb5c5 892 if (cpu_is_omap2420()) {
d8874665 893 size = OMAP2420_MMC_SIZE;
0dffb5c5 894 name = "mmci-omap";
82cf818d 895 } else if (cpu_is_omap44xx()) {
91a0b089 896 if (i < 3)
5772ca7d 897 irq += OMAP44XX_IRQ_GIC_START;
82cf818d 898 size = OMAP4_HSMMC_SIZE;
899 name = "mmci-omap-hs";
0dffb5c5 900 } else {
82cf818d 901 size = OMAP3_HSMMC_SIZE;
0dffb5c5
TL		 902 name = "mmci-omap-hs";
903 }
904 omap_mmc_add(name, i, base, size, irq, mmc_data[i]);
d8874665
TL		 905 };
906}
907
908#endif
909
910/*-------------------------------------------------------------------------*/
911
646e3ed1
TL		 912#if defined(CONFIG_HDQ_MASTER_OMAP) || defined(CONFIG_HDQ_MASTER_OMAP_MODULE)
913#if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3430)
914#define OMAP_HDQ_BASE 0x480B2000
915#endif
916static struct resource omap_hdq_resources[] = {
917 {
918 .start = OMAP_HDQ_BASE,
919 .end = OMAP_HDQ_BASE + 0x1C,
920 .flags = IORESOURCE_MEM,
921 },
922 {
923 .start = INT_24XX_HDQ_IRQ,
924 .flags = IORESOURCE_IRQ,
925 },
926};
927static struct platform_device omap_hdq_dev = {
928 .name = "omap_hdq",
929 .id = 0,
930 .dev = {
931 .platform_data = NULL,
932 },
933 .num_resources = ARRAY_SIZE(omap_hdq_resources),
934 .resource = omap_hdq_resources,
935};
936static inline void omap_hdq_init(void)
937{
938 (void) platform_device_register(&omap_hdq_dev);
939}
940#else
941static inline void omap_hdq_init(void) {}
942#endif
943
b227358d
VH		 944/*---------------------------------------------------------------------------*/
945
946#if defined(CONFIG_VIDEO_OMAP2_VOUT) || \
947 defined(CONFIG_VIDEO_OMAP2_VOUT_MODULE)
948#if defined(CONFIG_FB_OMAP2) || defined(CONFIG_FB_OMAP2_MODULE)
949static struct resource omap_vout_resource[3 - CONFIG_FB_OMAP2_NUM_FBS] = {
950};
951#else
952static struct resource omap_vout_resource[2] = {
953};
954#endif
955
956static struct platform_device omap_vout_device = {
957 .name = "omap_vout",
958 .num_resources = ARRAY_SIZE(omap_vout_resource),
959 .resource = &omap_vout_resource[0],
960 .id = -1,
961};
962static void omap_init_vout(void)
963{
964 if (platform_device_register(&omap_vout_device) < 0)
965 printk(KERN_ERR "Unable to register OMAP-VOUT device\n");
966}
967#else
968static inline void omap_init_vout(void) {}
969#endif
970
1dbae815
TL		 971/*-------------------------------------------------------------------------*/
972
973static int __init omap2_init_devices(void)
974{
81fbc5ef
PW		 975 /*
976 * please keep these calls, and their implementations above,
1dbae815
TL		 977 * in alphabetical order so they're easier to sort through.
978 */
917fa280 979 omap_hsmmc_reset();
f0fba2ad 980 omap_init_audio();
828c707e 981 omap_init_camera();
c40fae95 982 omap_init_mbox();
ed7eb9d9 983 omap_init_mcspi();
88341334 984 omap_init_pmu();
646e3ed1 985 omap_hdq_init();
9b6553cd 986 omap_init_sti();
ee5500c4 987 omap_init_sham();
b744c679 988 omap_init_aes();
b227358d 989 omap_init_vout();
1dbae815
TL		 990
991 return 0;
992}
993arch_initcall(omap2_init_devices);
f2ce6231
VC		 994
995#if defined(CONFIG_OMAP_WATCHDOG) || defined(CONFIG_OMAP_WATCHDOG_MODULE)
a9b365bd 996static struct omap_device_pm_latency omap_wdt_latency[] = {
f2ce6231
VC		 997 [0] = {
998 .deactivate_func = omap_device_idle_hwmods,
999 .activate_func = omap_device_enable_hwmods,
1000 .flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST,
1001 },
1002};
1003
1004static int __init omap_init_wdt(void)
1005{
1006 int id = -1;
1007 struct omap_device *od;
1008 struct omap_hwmod *oh;
1009 char *oh_name = "wd_timer2";
1010 char *dev_name = "omap_wdt";
1011
1012 if (!cpu_class_is_omap2())
1013 return 0;
1014
1015 oh = omap_hwmod_lookup(oh_name);
1016 if (!oh) {
1017 pr_err("Could not look up wd_timer%d hwmod\n", id);
1018 return -EINVAL;
1019 }
1020
1021 od = omap_device_build(dev_name, id, oh, NULL, 0,
1022 omap_wdt_latency,
1023 ARRAY_SIZE(omap_wdt_latency), 0);
1024 WARN(IS_ERR(od), "Cant build omap_device for %s:%s.\n",
1025 dev_name, oh->name);
1026 return 0;
1027}
1028subsys_initcall(omap_init_wdt);
1029#endif
Linux kernel - Deliverables
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