[deliverable/linux.git] / arch / arm / mach-omap2 / devices.c

/*
 * linux/arch/arm/mach-omap2/devices.c
 *
 * OMAP2 platform device setup/initialization
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 */

#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/io.h>
#include <linux/clk.h>

#include <mach/hardware.h>
#include <asm/mach-types.h>
#include <asm/mach/map.h>

#include <plat/control.h>
#include <plat/tc.h>
#include <plat/board.h>
#include <plat/mux.h>
#include <mach/gpio.h>
#include <plat/mmc.h>

#if defined(CONFIG_VIDEO_OMAP2) || defined(CONFIG_VIDEO_OMAP2_MODULE)

static struct resource cam_resources[] = {
	{
		.start		= OMAP24XX_CAMERA_BASE,
		.end		= OMAP24XX_CAMERA_BASE + 0xfff,
		.flags		= IORESOURCE_MEM,
	},
	{
		.start		= INT_24XX_CAM_IRQ,
		.flags		= IORESOURCE_IRQ,
	}
};

static struct platform_device omap_cam_device = {
	.name		= "omap24xxcam",
	.id		= -1,
	.num_resources	= ARRAY_SIZE(cam_resources),
	.resource	= cam_resources,
};

static inline void omap_init_camera(void)
{
	platform_device_register(&omap_cam_device);
}

#elif defined(CONFIG_VIDEO_OMAP3) || defined(CONFIG_VIDEO_OMAP3_MODULE)

static struct resource omap3isp_resources[] = {
	{
		.start		= OMAP3430_ISP_BASE,
		.end		= OMAP3430_ISP_END,
		.flags		= IORESOURCE_MEM,
	},
	{
		.start		= OMAP3430_ISP_CBUFF_BASE,
		.end		= OMAP3430_ISP_CBUFF_END,
		.flags		= IORESOURCE_MEM,
	},
	{
		.start		= OMAP3430_ISP_CCP2_BASE,
		.end		= OMAP3430_ISP_CCP2_END,
		.flags		= IORESOURCE_MEM,
	},
	{
		.start		= OMAP3430_ISP_CCDC_BASE,
		.end		= OMAP3430_ISP_CCDC_END,
		.flags		= IORESOURCE_MEM,
	},
	{
		.start		= OMAP3430_ISP_HIST_BASE,
		.end		= OMAP3430_ISP_HIST_END,
		.flags		= IORESOURCE_MEM,
	},
	{
		.start		= OMAP3430_ISP_H3A_BASE,
		.end		= OMAP3430_ISP_H3A_END,
		.flags		= IORESOURCE_MEM,
	},
	{
		.start		= OMAP3430_ISP_PREV_BASE,
		.end		= OMAP3430_ISP_PREV_END,
		.flags		= IORESOURCE_MEM,
	},
	{
		.start		= OMAP3430_ISP_RESZ_BASE,
		.end		= OMAP3430_ISP_RESZ_END,
		.flags		= IORESOURCE_MEM,
	},
	{
		.start		= OMAP3430_ISP_SBL_BASE,
		.end		= OMAP3430_ISP_SBL_END,
		.flags		= IORESOURCE_MEM,
	},
	{
		.start		= OMAP3430_ISP_CSI2A_BASE,
		.end		= OMAP3430_ISP_CSI2A_END,
		.flags		= IORESOURCE_MEM,
	},
	{
		.start		= OMAP3430_ISP_CSI2PHY_BASE,
		.end		= OMAP3430_ISP_CSI2PHY_END,
		.flags		= IORESOURCE_MEM,
	},
	{
		.start		= INT_34XX_CAM_IRQ,
		.flags		= IORESOURCE_IRQ,
	}
};

static struct platform_device omap3isp_device = {
	.name		= "omap3isp",
	.id		= -1,
	.num_resources	= ARRAY_SIZE(omap3isp_resources),
	.resource	= omap3isp_resources,
};

static inline void omap_init_camera(void)
{
	platform_device_register(&omap3isp_device);
}
#else
static inline void omap_init_camera(void)
{
}
#endif

#if defined(CONFIG_OMAP_MBOX_FWK) || defined(CONFIG_OMAP_MBOX_FWK_MODULE)

#define MBOX_REG_SIZE   0x120

#ifdef CONFIG_ARCH_OMAP2
static struct resource omap_mbox_resources[] = {
	{
		.start		= OMAP24XX_MAILBOX_BASE,
		.end		= OMAP24XX_MAILBOX_BASE + MBOX_REG_SIZE - 1,
		.flags		= IORESOURCE_MEM,
	},
	{
		.start		= INT_24XX_MAIL_U0_MPU,
		.flags		= IORESOURCE_IRQ,
	},
	{
		.start		= INT_24XX_MAIL_U3_MPU,
		.flags		= IORESOURCE_IRQ,
	},
};
#endif

#ifdef CONFIG_ARCH_OMAP3
static struct resource omap_mbox_resources[] = {
	{
		.start		= OMAP34XX_MAILBOX_BASE,
		.end		= OMAP34XX_MAILBOX_BASE + MBOX_REG_SIZE - 1,
		.flags		= IORESOURCE_MEM,
	},
	{
		.start		= INT_24XX_MAIL_U0_MPU,
		.flags		= IORESOURCE_IRQ,
	},
};
#endif

#ifdef CONFIG_ARCH_OMAP4

#define OMAP4_MBOX_REG_SIZE	0x130
static struct resource omap_mbox_resources[] = {
	{
		.start          = OMAP44XX_MAILBOX_BASE,
		.end            = OMAP44XX_MAILBOX_BASE +
					OMAP4_MBOX_REG_SIZE - 1,
		.flags          = IORESOURCE_MEM,
	},
	{
		.start          = INT_44XX_MAIL_U0_MPU,
		.flags          = IORESOURCE_IRQ,
	},
};
#endif

static struct platform_device mbox_device = {
	.name		= "omap2-mailbox",
	.id		= -1,
};

static inline void omap_init_mbox(void)
{
	if (cpu_is_omap2420() || cpu_is_omap3430() || cpu_is_omap44xx()) {
		mbox_device.num_resources = ARRAY_SIZE(omap_mbox_resources);
		mbox_device.resource = omap_mbox_resources;
	} else {
		pr_err("%s: platform not supported\n", __func__);
		return;
	}
	platform_device_register(&mbox_device);
}
#else
static inline void omap_init_mbox(void) { }
#endif /* CONFIG_OMAP_MBOX_FWK */

#if defined(CONFIG_OMAP_STI)

#if defined(CONFIG_ARCH_OMAP2)

#define OMAP2_STI_BASE		0x48068000
#define OMAP2_STI_CHANNEL_BASE	0x54000000
#define OMAP2_STI_IRQ		4

static struct resource sti_resources[] = {
	{
		.start		= OMAP2_STI_BASE,
		.end		= OMAP2_STI_BASE + 0x7ff,
		.flags		= IORESOURCE_MEM,
	},
	{
		.start		= OMAP2_STI_CHANNEL_BASE,
		.end		= OMAP2_STI_CHANNEL_BASE + SZ_64K - 1,
		.flags		= IORESOURCE_MEM,
	},
	{
		.start		= OMAP2_STI_IRQ,
		.flags		= IORESOURCE_IRQ,
	}
};
#elif defined(CONFIG_ARCH_OMAP3)

#define OMAP3_SDTI_BASE		0x54500000
#define OMAP3_SDTI_CHANNEL_BASE	0x54600000

static struct resource sti_resources[] = {
	{
		.start		= OMAP3_SDTI_BASE,
		.end		= OMAP3_SDTI_BASE + 0xFFF,
		.flags		= IORESOURCE_MEM,
	},
	{
		.start		= OMAP3_SDTI_CHANNEL_BASE,
		.end		= OMAP3_SDTI_CHANNEL_BASE + SZ_1M - 1,
		.flags		= IORESOURCE_MEM,
	}
};

#endif

static struct platform_device sti_device = {
	.name		= "sti",
	.id		= -1,
	.num_resources	= ARRAY_SIZE(sti_resources),
	.resource	= sti_resources,
};

static inline void omap_init_sti(void)
{
	platform_device_register(&sti_device);
}
#else
static inline void omap_init_sti(void) {}
#endif

#if defined(CONFIG_SPI_OMAP24XX) || defined(CONFIG_SPI_OMAP24XX_MODULE)

#include <plat/mcspi.h>

#define OMAP2_MCSPI1_BASE		0x48098000
#define OMAP2_MCSPI2_BASE		0x4809a000
#define OMAP2_MCSPI3_BASE		0x480b8000
#define OMAP2_MCSPI4_BASE		0x480ba000

#define OMAP4_MCSPI1_BASE		0x48098100
#define OMAP4_MCSPI2_BASE		0x4809a100
#define OMAP4_MCSPI3_BASE		0x480b8100
#define OMAP4_MCSPI4_BASE		0x480ba100

static struct omap2_mcspi_platform_config omap2_mcspi1_config = {
	.num_cs		= 4,
};

static struct resource omap2_mcspi1_resources[] = {
	{
		.start		= OMAP2_MCSPI1_BASE,
		.end		= OMAP2_MCSPI1_BASE + 0xff,
		.flags		= IORESOURCE_MEM,
	},
};

static struct platform_device omap2_mcspi1 = {
	.name		= "omap2_mcspi",
	.id		= 1,
	.num_resources	= ARRAY_SIZE(omap2_mcspi1_resources),
	.resource	= omap2_mcspi1_resources,
	.dev		= {
		.platform_data = &omap2_mcspi1_config,
	},
};

static struct omap2_mcspi_platform_config omap2_mcspi2_config = {
	.num_cs		= 2,
};

static struct resource omap2_mcspi2_resources[] = {
	{
		.start		= OMAP2_MCSPI2_BASE,
		.end		= OMAP2_MCSPI2_BASE + 0xff,
		.flags		= IORESOURCE_MEM,
	},
};

static struct platform_device omap2_mcspi2 = {
	.name		= "omap2_mcspi",
	.id		= 2,
	.num_resources	= ARRAY_SIZE(omap2_mcspi2_resources),
	.resource	= omap2_mcspi2_resources,
	.dev		= {
		.platform_data = &omap2_mcspi2_config,
	},
};

#if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3) || \
	defined(CONFIG_ARCH_OMAP4)
static struct omap2_mcspi_platform_config omap2_mcspi3_config = {
	.num_cs		= 2,
};

static struct resource omap2_mcspi3_resources[] = {
	{
	.start		= OMAP2_MCSPI3_BASE,
	.end		= OMAP2_MCSPI3_BASE + 0xff,
	.flags		= IORESOURCE_MEM,
	},
};

static struct platform_device omap2_mcspi3 = {
	.name		= "omap2_mcspi",
	.id		= 3,
	.num_resources	= ARRAY_SIZE(omap2_mcspi3_resources),
	.resource	= omap2_mcspi3_resources,
	.dev		= {
		.platform_data = &omap2_mcspi3_config,
	},
};
#endif

#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
static struct omap2_mcspi_platform_config omap2_mcspi4_config = {
	.num_cs		= 1,
};

static struct resource omap2_mcspi4_resources[] = {
	{
		.start		= OMAP2_MCSPI4_BASE,
		.end		= OMAP2_MCSPI4_BASE + 0xff,
		.flags		= IORESOURCE_MEM,
	},
};

static struct platform_device omap2_mcspi4 = {
	.name		= "omap2_mcspi",
	.id		= 4,
	.num_resources	= ARRAY_SIZE(omap2_mcspi4_resources),
	.resource	= omap2_mcspi4_resources,
	.dev		= {
		.platform_data = &omap2_mcspi4_config,
	},
};
#endif

#ifdef CONFIG_ARCH_OMAP4
static inline void omap4_mcspi_fixup(void)
{
	omap2_mcspi1_resources[0].start	= OMAP4_MCSPI1_BASE;
	omap2_mcspi1_resources[0].end	= OMAP4_MCSPI1_BASE + 0xff;
	omap2_mcspi2_resources[0].start	= OMAP4_MCSPI2_BASE;
	omap2_mcspi2_resources[0].end	= OMAP4_MCSPI2_BASE + 0xff;
	omap2_mcspi3_resources[0].start	= OMAP4_MCSPI3_BASE;
	omap2_mcspi3_resources[0].end	= OMAP4_MCSPI3_BASE + 0xff;
	omap2_mcspi4_resources[0].start	= OMAP4_MCSPI4_BASE;
	omap2_mcspi4_resources[0].end	= OMAP4_MCSPI4_BASE + 0xff;
}
#else
static inline void omap4_mcspi_fixup(void)
{
}
#endif

#if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3) || \
	defined(CONFIG_ARCH_OMAP4)
static inline void omap2_mcspi3_init(void)
{
	platform_device_register(&omap2_mcspi3);
}
#else
static inline void omap2_mcspi3_init(void)
{
}
#endif

#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
static inline void omap2_mcspi4_init(void)
{
	platform_device_register(&omap2_mcspi4);
}
#else
static inline void omap2_mcspi4_init(void)
{
}
#endif

static void omap_init_mcspi(void)
{
	if (cpu_is_omap44xx())
		omap4_mcspi_fixup();

	platform_device_register(&omap2_mcspi1);
	platform_device_register(&omap2_mcspi2);

	if (cpu_is_omap2430() || cpu_is_omap343x() || cpu_is_omap44xx())
		omap2_mcspi3_init();

	if (cpu_is_omap343x() || cpu_is_omap44xx())
		omap2_mcspi4_init();
}

#else
static inline void omap_init_mcspi(void) {}
#endif

#ifdef CONFIG_OMAP_SHA1_MD5
static struct resource sha1_md5_resources[] = {
	{
		.start	= OMAP24XX_SEC_SHA1MD5_BASE,
		.end	= OMAP24XX_SEC_SHA1MD5_BASE + 0x64,
		.flags	= IORESOURCE_MEM,
	},
	{
		.start	= INT_24XX_SHA1MD5,
		.flags	= IORESOURCE_IRQ,
	}
};

static struct platform_device sha1_md5_device = {
	.name		= "OMAP SHA1/MD5",
	.id		= -1,
	.num_resources	= ARRAY_SIZE(sha1_md5_resources),
	.resource	= sha1_md5_resources,
};

static void omap_init_sha1_md5(void)
{
	platform_device_register(&sha1_md5_device);
}
#else
static inline void omap_init_sha1_md5(void) { }
#endif

/*-------------------------------------------------------------------------*/

#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)

#define MMCHS_SYSCONFIG			0x0010
#define MMCHS_SYSCONFIG_SWRESET		(1 << 1)
#define MMCHS_SYSSTATUS			0x0014
#define MMCHS_SYSSTATUS_RESETDONE	(1 << 0)

static struct platform_device dummy_pdev = {
	.dev = {
		.bus = &platform_bus_type,
	},
};

/**
 * omap_hsmmc_reset() - Full reset of each HS-MMC controller
 *
 * Ensure that each MMC controller is fully reset.  Controllers
 * left in an unknown state (by bootloader) may prevent retention
 * or OFF-mode.  This is especially important in cases where the
 * MMC driver is not enabled, _or_ built as a module.
 *
 * In order for reset to work, interface, functional and debounce
 * clocks must be enabled.  The debounce clock comes from func_32k_clk
 * and is not under SW control, so we only enable i- and f-clocks.
 **/
static void __init omap_hsmmc_reset(void)
{
	u32 i, nr_controllers = cpu_is_omap44xx() ? OMAP44XX_NR_MMC :
		(cpu_is_omap34xx() ? OMAP34XX_NR_MMC : OMAP24XX_NR_MMC);

	for (i = 0; i < nr_controllers; i++) {
		u32 v, base = 0;
		struct clk *iclk, *fclk;
		struct device *dev = &dummy_pdev.dev;

		switch (i) {
		case 0:
			base = OMAP2_MMC1_BASE;
			break;
		case 1:
			base = OMAP2_MMC2_BASE;
			break;
		case 2:
			base = OMAP3_MMC3_BASE;
			break;
		case 3:
			if (!cpu_is_omap44xx())
				return;
			base = OMAP4_MMC4_BASE;
			break;
		case 4:
			if (!cpu_is_omap44xx())
				return;
			base = OMAP4_MMC5_BASE;
			break;
		}

		if (cpu_is_omap44xx())
			base += OMAP4_MMC_REG_OFFSET;

		dummy_pdev.id = i;
		dev_set_name(&dummy_pdev.dev, "mmci-omap-hs.%d", i);
		iclk = clk_get(dev, "ick");
		if (iclk && clk_enable(iclk))
			iclk = NULL;

		fclk = clk_get(dev, "fck");
		if (fclk && clk_enable(fclk))
			fclk = NULL;

		if (!iclk || !fclk) {
			printk(KERN_WARNING
			       "%s: Unable to enable clocks for MMC%d, "
			       "cannot reset.\n",  __func__, i);
			break;
		}

		omap_writel(MMCHS_SYSCONFIG_SWRESET, base + MMCHS_SYSCONFIG);
		v = omap_readl(base + MMCHS_SYSSTATUS);
		while (!(omap_readl(base + MMCHS_SYSSTATUS) &
			 MMCHS_SYSSTATUS_RESETDONE))
			cpu_relax();

		if (fclk) {
			clk_disable(fclk);
			clk_put(fclk);
		}
		if (iclk) {
			clk_disable(iclk);
			clk_put(iclk);
		}
	}
}
#else
static inline void omap_hsmmc_reset(void) {}
#endif

#if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE) || \
	defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE)

static inline void omap2_mmc_mux(struct omap_mmc_platform_data *mmc_controller,
			int controller_nr)
{
	if (cpu_is_omap2420() && controller_nr == 0) {
		omap_cfg_reg(H18_24XX_MMC_CMD);
		omap_cfg_reg(H15_24XX_MMC_CLKI);
		omap_cfg_reg(G19_24XX_MMC_CLKO);
		omap_cfg_reg(F20_24XX_MMC_DAT0);
		omap_cfg_reg(F19_24XX_MMC_DAT_DIR0);
		omap_cfg_reg(G18_24XX_MMC_CMD_DIR);
		if (mmc_controller->slots[0].wires == 4) {
			omap_cfg_reg(H14_24XX_MMC_DAT1);
			omap_cfg_reg(E19_24XX_MMC_DAT2);
			omap_cfg_reg(D19_24XX_MMC_DAT3);
			omap_cfg_reg(E20_24XX_MMC_DAT_DIR1);
			omap_cfg_reg(F18_24XX_MMC_DAT_DIR2);
			omap_cfg_reg(E18_24XX_MMC_DAT_DIR3);
		}

		/*
		 * Use internal loop-back in MMC/SDIO Module Input Clock
		 * selection
		 */
		if (mmc_controller->slots[0].internal_clock) {
			u32 v = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
			v |= (1 << 24);
			omap_ctrl_writel(v, OMAP2_CONTROL_DEVCONF0);
		}
	}

	if (cpu_is_omap34xx()) {
		if (controller_nr == 0) {
			omap_cfg_reg(N28_3430_MMC1_CLK);
			omap_cfg_reg(M27_3430_MMC1_CMD);
			omap_cfg_reg(N27_3430_MMC1_DAT0);
			if (mmc_controller->slots[0].wires == 4 ||
				mmc_controller->slots[0].wires == 8) {
				omap_cfg_reg(N26_3430_MMC1_DAT1);
				omap_cfg_reg(N25_3430_MMC1_DAT2);
				omap_cfg_reg(P28_3430_MMC1_DAT3);
			}
			if (mmc_controller->slots[0].wires == 8) {
				omap_cfg_reg(P27_3430_MMC1_DAT4);
				omap_cfg_reg(P26_3430_MMC1_DAT5);
				omap_cfg_reg(R27_3430_MMC1_DAT6);
				omap_cfg_reg(R25_3430_MMC1_DAT7);
			}
		}
		if (controller_nr == 1) {
			/* MMC2 */
			omap_cfg_reg(AE2_3430_MMC2_CLK);
			omap_cfg_reg(AG5_3430_MMC2_CMD);
			omap_cfg_reg(AH5_3430_MMC2_DAT0);

			/*
			 * For 8 wire configurations, Lines DAT4, 5, 6 and 7 need to be muxed
			 * in the board-*.c files
			 */
			if (mmc_controller->slots[0].wires == 4 ||
				mmc_controller->slots[0].wires == 8) {
				omap_cfg_reg(AH4_3430_MMC2_DAT1);
				omap_cfg_reg(AG4_3430_MMC2_DAT2);
				omap_cfg_reg(AF4_3430_MMC2_DAT3);
			}
			if (mmc_controller->slots[0].wires == 8) {
				omap_cfg_reg(AE4_3430_MMC2_DAT4);
				omap_cfg_reg(AH3_3430_MMC2_DAT5);
				omap_cfg_reg(AF3_3430_MMC2_DAT6);
				omap_cfg_reg(AE3_3430_MMC2_DAT7);
			}
		}

		/*
		 * For MMC3 the pins need to be muxed in the board-*.c files
		 */
	}
}

void __init omap2_init_mmc(struct omap_mmc_platform_data **mmc_data,
			int nr_controllers)
{
	int i;
	char *name;

	for (i = 0; i < nr_controllers; i++) {
		unsigned long base, size;
		unsigned int irq = 0;

		if (!mmc_data[i])
			continue;

		omap2_mmc_mux(mmc_data[i], i);

		switch (i) {
		case 0:
			base = OMAP2_MMC1_BASE;
			irq = INT_24XX_MMC_IRQ;
			break;
		case 1:
			base = OMAP2_MMC2_BASE;
			irq = INT_24XX_MMC2_IRQ;
			break;
		case 2:
			if (!cpu_is_omap44xx() && !cpu_is_omap34xx())
				return;
			base = OMAP3_MMC3_BASE;
			irq = INT_34XX_MMC3_IRQ;
			break;
		case 3:
			if (!cpu_is_omap44xx())
				return;
			base = OMAP4_MMC4_BASE + OMAP4_MMC_REG_OFFSET;
			irq = INT_44XX_MMC4_IRQ;
			break;
		case 4:
			if (!cpu_is_omap44xx())
				return;
			base = OMAP4_MMC5_BASE + OMAP4_MMC_REG_OFFSET;
			irq = INT_44XX_MMC5_IRQ;
			break;
		default:
			continue;
		}

		if (cpu_is_omap2420()) {
			size = OMAP2420_MMC_SIZE;
			name = "mmci-omap";
		} else if (cpu_is_omap44xx()) {
			if (i < 3) {
				base += OMAP4_MMC_REG_OFFSET;
				irq += IRQ_GIC_START;
			}
			size = OMAP4_HSMMC_SIZE;
			name = "mmci-omap-hs";
		} else {
			size = OMAP3_HSMMC_SIZE;
			name = "mmci-omap-hs";
		}
		omap_mmc_add(name, i, base, size, irq, mmc_data[i]);
	};
}

#endif

/*-------------------------------------------------------------------------*/

#if defined(CONFIG_HDQ_MASTER_OMAP) || defined(CONFIG_HDQ_MASTER_OMAP_MODULE)
#if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3430)
#define OMAP_HDQ_BASE	0x480B2000
#endif
static struct resource omap_hdq_resources[] = {
	{
		.start		= OMAP_HDQ_BASE,
		.end		= OMAP_HDQ_BASE + 0x1C,
		.flags		= IORESOURCE_MEM,
	},
	{
		.start		= INT_24XX_HDQ_IRQ,
		.flags		= IORESOURCE_IRQ,
	},
};
static struct platform_device omap_hdq_dev = {
	.name = "omap_hdq",
	.id = 0,
	.dev = {
		.platform_data = NULL,
	},
	.num_resources	= ARRAY_SIZE(omap_hdq_resources),
	.resource	= omap_hdq_resources,
};
static inline void omap_hdq_init(void)
{
	(void) platform_device_register(&omap_hdq_dev);
}
#else
static inline void omap_hdq_init(void) {}
#endif

/*-------------------------------------------------------------------------*/

static int __init omap2_init_devices(void)
{
	/* please keep these calls, and their implementations above,
	 * in alphabetical order so they're easier to sort through.
	 */
	omap_hsmmc_reset();
	omap_init_camera();
	omap_init_mbox();
	omap_init_mcspi();
	omap_hdq_init();
	omap_init_sti();
	omap_init_sha1_md5();

	return 0;
}
arch_initcall(omap2_init_devices);
Commit	Line	Data
1dbae815 TL	1	/*
	2	* linux/arch/arm/mach-omap2/devices.c
	3	*
	4	* OMAP2 platform device setup/initialization
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License as published by
	8	* the Free Software Foundation; either version 2 of the License, or
	9	* (at your option) any later version.
	10	*/
	11
1dbae815 TL	12	#include <linux/module.h>
	13	#include <linux/kernel.h>
	14	#include <linux/init.h>
	15	#include <linux/platform_device.h>
fced80c7	16	#include <linux/io.h>
917fa280	17	#include <linux/clk.h>
1dbae815	18
a09e64fb	19	#include <mach/hardware.h>
1dbae815 TL	20	#include <asm/mach-types.h>
	21	#include <asm/mach/map.h>
	22
ce491cf8 TL	23	#include <plat/control.h>
	24	#include <plat/tc.h>
	25	#include <plat/board.h>
	26	#include <plat/mux.h>
a09e64fb	27	#include <mach/gpio.h>
ce491cf8	28	#include <plat/mmc.h>
1dbae815	29
828c707e	30	#if defined(CONFIG_VIDEO_OMAP2) \|\| defined(CONFIG_VIDEO_OMAP2_MODULE)
c40fae95	31
828c707e	32	static struct resource cam_resources[] = {
c40fae95	33	{
828c707e TL	34	.start = OMAP24XX_CAMERA_BASE,
	35	.end = OMAP24XX_CAMERA_BASE + 0xfff,
	36	.flags = IORESOURCE_MEM,
	37	},
	38	{
	39	.start = INT_24XX_CAM_IRQ,
	40	.flags = IORESOURCE_IRQ,
	41	}
	42	};
	43
	44	static struct platform_device omap_cam_device = {
	45	.name = "omap24xxcam",
	46	.id = -1,
	47	.num_resources = ARRAY_SIZE(cam_resources),
	48	.resource = cam_resources,
	49	};
	50
	51	static inline void omap_init_camera(void)
	52	{
	53	platform_device_register(&omap_cam_device);
	54	}
	55
	56	#elif defined(CONFIG_VIDEO_OMAP3) \|\| defined(CONFIG_VIDEO_OMAP3_MODULE)
	57
	58	static struct resource omap3isp_resources[] = {
	59	{
	60	.start = OMAP3430_ISP_BASE,
	61	.end = OMAP3430_ISP_END,
	62	.flags = IORESOURCE_MEM,
	63	},
	64	{
	65	.start = OMAP3430_ISP_CBUFF_BASE,
	66	.end = OMAP3430_ISP_CBUFF_END,
	67	.flags = IORESOURCE_MEM,
	68	},
	69	{
	70	.start = OMAP3430_ISP_CCP2_BASE,
	71	.end = OMAP3430_ISP_CCP2_END,
	72	.flags = IORESOURCE_MEM,
	73	},
	74	{
	75	.start = OMAP3430_ISP_CCDC_BASE,
	76	.end = OMAP3430_ISP_CCDC_END,
	77	.flags = IORESOURCE_MEM,
	78	},
	79	{
	80	.start = OMAP3430_ISP_HIST_BASE,
	81	.end = OMAP3430_ISP_HIST_END,
	82	.flags = IORESOURCE_MEM,
	83	},
	84	{
	85	.start = OMAP3430_ISP_H3A_BASE,
	86	.end = OMAP3430_ISP_H3A_END,
	87	.flags = IORESOURCE_MEM,
	88	},
	89	{
	90	.start = OMAP3430_ISP_PREV_BASE,
	91	.end = OMAP3430_ISP_PREV_END,
	92	.flags = IORESOURCE_MEM,
	93	},
	94	{
	95	.start = OMAP3430_ISP_RESZ_BASE,
	96	.end = OMAP3430_ISP_RESZ_END,
	97	.flags = IORESOURCE_MEM,
98	},
99	{
100	.start = OMAP3430_ISP_SBL_BASE,
101	.end = OMAP3430_ISP_SBL_END,
102	.flags = IORESOURCE_MEM,
103	},
104	{
105	.start = OMAP3430_ISP_CSI2A_BASE,
106	.end = OMAP3430_ISP_CSI2A_END,
107	.flags = IORESOURCE_MEM,
108	},
109	{
110	.start = OMAP3430_ISP_CSI2PHY_BASE,
111	.end = OMAP3430_ISP_CSI2PHY_END,
112	.flags = IORESOURCE_MEM,
113	},
114	{
115	.start = INT_34XX_CAM_IRQ,
116	.flags = IORESOURCE_IRQ,
117	}
118	};
119
120	static struct platform_device omap3isp_device = {
121	.name = "omap3isp",
122	.id = -1,
123	.num_resources = ARRAY_SIZE(omap3isp_resources),
124	.resource = omap3isp_resources,
125	};
126
127	static inline void omap_init_camera(void)
128	{
129	platform_device_register(&omap3isp_device);
130	}
131	#else
132	static inline void omap_init_camera(void)
133	{
134	}
135	#endif
136
6c20a683	137	#if defined(CONFIG_OMAP_MBOX_FWK) \|\| defined(CONFIG_OMAP_MBOX_FWK_MODULE)
c40fae95	138
454bf340	139	#define MBOX_REG_SIZE 0x120
6c20a683	140
454bf340 S	141	#ifdef CONFIG_ARCH_OMAP2
454bf340 S	142	static struct resource omap_mbox_resources[] = {
c40fae95	143	{
6c20a683 HD	144	.start = OMAP24XX_MAILBOX_BASE,
6c20a683 HD	145	.end = OMAP24XX_MAILBOX_BASE + MBOX_REG_SIZE - 1,
c40fae95 TL	146	.flags = IORESOURCE_MEM,
	147	},
	148	{
	149	.start = INT_24XX_MAIL_U0_MPU,
	150	.flags = IORESOURCE_IRQ,
	151	},
	152	{
	153	.start = INT_24XX_MAIL_U3_MPU,
	154	.flags = IORESOURCE_IRQ,
	155	},
	156	};
454bf340	157	#endif
c40fae95	158
454bf340 S	159	#ifdef CONFIG_ARCH_OMAP3
454bf340 S	160	static struct resource omap_mbox_resources[] = {
6c20a683 HD	161	{
	162	.start = OMAP34XX_MAILBOX_BASE,
	163	.end = OMAP34XX_MAILBOX_BASE + MBOX_REG_SIZE - 1,
	164	.flags = IORESOURCE_MEM,
	165	},
	166	{
	167	.start = INT_24XX_MAIL_U0_MPU,
	168	.flags = IORESOURCE_IRQ,
	169	},
	170	};
454bf340 S	171	#endif
	172
	173	#ifdef CONFIG_ARCH_OMAP4
	174
	175	#define OMAP4_MBOX_REG_SIZE 0x130
	176	static struct resource omap_mbox_resources[] = {
	177	{
	178	.start = OMAP44XX_MAILBOX_BASE,
	179	.end = OMAP44XX_MAILBOX_BASE +
	180	OMAP4_MBOX_REG_SIZE - 1,
	181	.flags = IORESOURCE_MEM,
	182	},
	183	{
	184	.start = INT_44XX_MAIL_U0_MPU,
	185	.flags = IORESOURCE_IRQ,
	186	},
	187	};
	188	#endif
6c20a683	189
c40fae95	190	static struct platform_device mbox_device = {
da8cfe03	191	.name = "omap2-mailbox",
c40fae95	192	.id = -1,
c40fae95 TL	193	};
	194
	195	static inline void omap_init_mbox(void)
	196	{
454bf340 S	197	if (cpu_is_omap2420() \|\| cpu_is_omap3430() \|\| cpu_is_omap44xx()) {
	198	mbox_device.num_resources = ARRAY_SIZE(omap_mbox_resources);
	199	mbox_device.resource = omap_mbox_resources;
6c20a683 HD	200	} else {
	201	pr_err("%s: platform not supported\n", __func__);
	202	return;
	203	}
c40fae95 TL	204	platform_device_register(&mbox_device);
	205	}
	206	#else
	207	static inline void omap_init_mbox(void) { }
6c20a683	208	#endif /* CONFIG_OMAP_MBOX_FWK */
c40fae95	209
9b6553cd TL	210	#if defined(CONFIG_OMAP_STI)
9b6553cd TL	211
646e3ed1 TL	212	#if defined(CONFIG_ARCH_OMAP2)
	213
	214	#define OMAP2_STI_BASE 0x48068000
9b6553cd TL	215	#define OMAP2_STI_CHANNEL_BASE 0x54000000
	216	#define OMAP2_STI_IRQ 4
	217
	218	static struct resource sti_resources[] = {
	219	{
	220	.start = OMAP2_STI_BASE,
	221	.end = OMAP2_STI_BASE + 0x7ff,
	222	.flags = IORESOURCE_MEM,
	223	},
	224	{
	225	.start = OMAP2_STI_CHANNEL_BASE,
	226	.end = OMAP2_STI_CHANNEL_BASE + SZ_64K - 1,
	227	.flags = IORESOURCE_MEM,
	228	},
	229	{
	230	.start = OMAP2_STI_IRQ,
	231	.flags = IORESOURCE_IRQ,
	232	}
	233	};
646e3ed1 TL	234	#elif defined(CONFIG_ARCH_OMAP3)
	235
	236	#define OMAP3_SDTI_BASE 0x54500000
	237	#define OMAP3_SDTI_CHANNEL_BASE 0x54600000
	238
	239	static struct resource sti_resources[] = {
	240	{
	241	.start = OMAP3_SDTI_BASE,
	242	.end = OMAP3_SDTI_BASE + 0xFFF,
	243	.flags = IORESOURCE_MEM,
	244	},
	245	{
	246	.start = OMAP3_SDTI_CHANNEL_BASE,
	247	.end = OMAP3_SDTI_CHANNEL_BASE + SZ_1M - 1,
	248	.flags = IORESOURCE_MEM,
	249	}
	250	};
	251
	252	#endif
9b6553cd TL	253
	254	static struct platform_device sti_device = {
	255	.name = "sti",
	256	.id = -1,
9b6553cd TL	257	.num_resources = ARRAY_SIZE(sti_resources),
	258	.resource = sti_resources,
	259	};
	260
	261	static inline void omap_init_sti(void)
	262	{
	263	platform_device_register(&sti_device);
	264	}
	265	#else
	266	static inline void omap_init_sti(void) {}
	267	#endif
	268
646e3ed1	269	#if defined(CONFIG_SPI_OMAP24XX) \|\| defined(CONFIG_SPI_OMAP24XX_MODULE)
ed7eb9d9	270
ce491cf8	271	#include <plat/mcspi.h>
ed7eb9d9 JY	272
	273	#define OMAP2_MCSPI1_BASE 0x48098000
	274	#define OMAP2_MCSPI2_BASE 0x4809a000
646e3ed1 TL	275	#define OMAP2_MCSPI3_BASE 0x480b8000
646e3ed1 TL	276	#define OMAP2_MCSPI4_BASE 0x480ba000
ed7eb9d9	277
7869c0b9 SR	278	#define OMAP4_MCSPI1_BASE 0x48098100
	279	#define OMAP4_MCSPI2_BASE 0x4809a100
	280	#define OMAP4_MCSPI3_BASE 0x480b8100
	281	#define OMAP4_MCSPI4_BASE 0x480ba100
	282
ed7eb9d9	283	static struct omap2_mcspi_platform_config omap2_mcspi1_config = {
ed7eb9d9 JY	284	.num_cs = 4,
	285	};
	286
c40fae95 TL	287	static struct resource omap2_mcspi1_resources[] = {
	288	{
	289	.start = OMAP2_MCSPI1_BASE,
	290	.end = OMAP2_MCSPI1_BASE + 0xff,
	291	.flags = IORESOURCE_MEM,
	292	},
	293	};
	294
646e3ed1	295	static struct platform_device omap2_mcspi1 = {
ed7eb9d9 JY	296	.name = "omap2_mcspi",
ed7eb9d9 JY	297	.id = 1,
c40fae95 TL	298	.num_resources = ARRAY_SIZE(omap2_mcspi1_resources),
c40fae95 TL	299	.resource = omap2_mcspi1_resources,
ed7eb9d9 JY	300	.dev = {
	301	.platform_data = &omap2_mcspi1_config,
	302	},
	303	};
	304
	305	static struct omap2_mcspi_platform_config omap2_mcspi2_config = {
ed7eb9d9 JY	306	.num_cs = 2,
	307	};
	308
c40fae95 TL	309	static struct resource omap2_mcspi2_resources[] = {
	310	{
	311	.start = OMAP2_MCSPI2_BASE,
	312	.end = OMAP2_MCSPI2_BASE + 0xff,
	313	.flags = IORESOURCE_MEM,
	314	},
	315	};
	316
646e3ed1	317	static struct platform_device omap2_mcspi2 = {
ed7eb9d9 JY	318	.name = "omap2_mcspi",
ed7eb9d9 JY	319	.id = 2,
c40fae95 TL	320	.num_resources = ARRAY_SIZE(omap2_mcspi2_resources),
c40fae95 TL	321	.resource = omap2_mcspi2_resources,
ed7eb9d9 JY	322	.dev = {
	323	.platform_data = &omap2_mcspi2_config,
	324	},
	325	};
	326
7869c0b9 SR	327	#if defined(CONFIG_ARCH_OMAP2430) \|\| defined(CONFIG_ARCH_OMAP3) \|\| \
7869c0b9 SR	328	defined(CONFIG_ARCH_OMAP4)
646e3ed1 TL	329	static struct omap2_mcspi_platform_config omap2_mcspi3_config = {
	330	.num_cs = 2,
	331	};
	332
	333	static struct resource omap2_mcspi3_resources[] = {
	334	{
	335	.start = OMAP2_MCSPI3_BASE,
	336	.end = OMAP2_MCSPI3_BASE + 0xff,
	337	.flags = IORESOURCE_MEM,
	338	},
	339	};
	340
	341	static struct platform_device omap2_mcspi3 = {
	342	.name = "omap2_mcspi",
	343	.id = 3,
	344	.num_resources = ARRAY_SIZE(omap2_mcspi3_resources),
	345	.resource = omap2_mcspi3_resources,
	346	.dev = {
	347	.platform_data = &omap2_mcspi3_config,
	348	},
	349	};
	350	#endif
	351
7869c0b9	352	#if defined(CONFIG_ARCH_OMAP3) \|\| defined(CONFIG_ARCH_OMAP4)
646e3ed1 TL	353	static struct omap2_mcspi_platform_config omap2_mcspi4_config = {
	354	.num_cs = 1,
	355	};
	356
	357	static struct resource omap2_mcspi4_resources[] = {
	358	{
	359	.start = OMAP2_MCSPI4_BASE,
	360	.end = OMAP2_MCSPI4_BASE + 0xff,
	361	.flags = IORESOURCE_MEM,
	362	},
	363	};
	364
	365	static struct platform_device omap2_mcspi4 = {
	366	.name = "omap2_mcspi",
	367	.id = 4,
	368	.num_resources = ARRAY_SIZE(omap2_mcspi4_resources),
	369	.resource = omap2_mcspi4_resources,
	370	.dev = {
	371	.platform_data = &omap2_mcspi4_config,
	372	},
	373	};
	374	#endif
	375
af41a12f TL	376	#ifdef CONFIG_ARCH_OMAP4
af41a12f TL	377	static inline void omap4_mcspi_fixup(void)
ed7eb9d9	378	{
af41a12f TL	379	omap2_mcspi1_resources[0].start = OMAP4_MCSPI1_BASE;
	380	omap2_mcspi1_resources[0].end = OMAP4_MCSPI1_BASE + 0xff;
	381	omap2_mcspi2_resources[0].start = OMAP4_MCSPI2_BASE;
	382	omap2_mcspi2_resources[0].end = OMAP4_MCSPI2_BASE + 0xff;
	383	omap2_mcspi3_resources[0].start = OMAP4_MCSPI3_BASE;
	384	omap2_mcspi3_resources[0].end = OMAP4_MCSPI3_BASE + 0xff;
	385	omap2_mcspi4_resources[0].start = OMAP4_MCSPI4_BASE;
	386	omap2_mcspi4_resources[0].end = OMAP4_MCSPI4_BASE + 0xff;
	387	}
	388	#else
	389	static inline void omap4_mcspi_fixup(void)
	390	{
	391	}
	392	#endif
	393
7869c0b9 SR	394	#if defined(CONFIG_ARCH_OMAP2430) \|\| defined(CONFIG_ARCH_OMAP3) \|\| \
7869c0b9 SR	395	defined(CONFIG_ARCH_OMAP4)
af41a12f TL	396	static inline void omap2_mcspi3_init(void)
	397	{
	398	platform_device_register(&omap2_mcspi3);
	399	}
	400	#else
	401	static inline void omap2_mcspi3_init(void)
	402	{
	403	}
646e3ed1	404	#endif
af41a12f	405
7869c0b9	406	#if defined(CONFIG_ARCH_OMAP3) \|\| defined(CONFIG_ARCH_OMAP4)
af41a12f TL	407	static inline void omap2_mcspi4_init(void)
	408	{
	409	platform_device_register(&omap2_mcspi4);
	410	}
	411	#else
	412	static inline void omap2_mcspi4_init(void)
	413	{
	414	}
646e3ed1	415	#endif
af41a12f TL	416
	417	static void omap_init_mcspi(void)
	418	{
	419	if (cpu_is_omap44xx())
	420	omap4_mcspi_fixup();
	421
	422	platform_device_register(&omap2_mcspi1);
	423	platform_device_register(&omap2_mcspi2);
	424
	425	if (cpu_is_omap2430() \|\| cpu_is_omap343x() \|\| cpu_is_omap44xx())
	426	omap2_mcspi3_init();
	427
	428	if (cpu_is_omap343x() \|\| cpu_is_omap44xx())
	429	omap2_mcspi4_init();
ed7eb9d9 JY	430	}
	431
	432	#else
	433	static inline void omap_init_mcspi(void) {}
	434	#endif
	435
646e3ed1 TL	436	#ifdef CONFIG_OMAP_SHA1_MD5
	437	static struct resource sha1_md5_resources[] = {
	438	{
	439	.start = OMAP24XX_SEC_SHA1MD5_BASE,
	440	.end = OMAP24XX_SEC_SHA1MD5_BASE + 0x64,
	441	.flags = IORESOURCE_MEM,
	442	},
	443	{
	444	.start = INT_24XX_SHA1MD5,
	445	.flags = IORESOURCE_IRQ,
	446	}
	447	};
	448
	449	static struct platform_device sha1_md5_device = {
	450	.name = "OMAP SHA1/MD5",
	451	.id = -1,
	452	.num_resources = ARRAY_SIZE(sha1_md5_resources),
	453	.resource = sha1_md5_resources,
	454	};
	455
	456	static void omap_init_sha1_md5(void)
	457	{
	458	platform_device_register(&sha1_md5_device);
	459	}
	460	#else
	461	static inline void omap_init_sha1_md5(void) { }
	462	#endif
	463
d8874665 TL	464	/-------------------------------------------------------------------------/
d8874665 TL	465
82cf818d	466	#if defined(CONFIG_ARCH_OMAP3) \|\| defined(CONFIG_ARCH_OMAP4)
917fa280 KH	467
	468	#define MMCHS_SYSCONFIG 0x0010
	469	#define MMCHS_SYSCONFIG_SWRESET (1 << 1)
	470	#define MMCHS_SYSSTATUS 0x0014
	471	#define MMCHS_SYSSTATUS_RESETDONE (1 << 0)
	472
	473	static struct platform_device dummy_pdev = {
	474	.dev = {
	475	.bus = &platform_bus_type,
	476	},
	477	};
	478
	479	/**
	480	* omap_hsmmc_reset() - Full reset of each HS-MMC controller
	481	*
	482	* Ensure that each MMC controller is fully reset. Controllers
	483	* left in an unknown state (by bootloader) may prevent retention
	484	* or OFF-mode. This is especially important in cases where the
	485	* MMC driver is not enabled, _or_ built as a module.
	486	*
	487	* In order for reset to work, interface, functional and debounce
	488	* clocks must be enabled. The debounce clock comes from func_32k_clk
	489	* and is not under SW control, so we only enable i- and f-clocks.
	490	**/
	491	static void __init omap_hsmmc_reset(void)
	492	{
82cf818d	493	u32 i, nr_controllers = cpu_is_omap44xx() ? OMAP44XX_NR_MMC :
82cf818d	494	(cpu_is_omap34xx() ? OMAP34XX_NR_MMC : OMAP24XX_NR_MMC);
917fa280 KH	495
	496	for (i = 0; i < nr_controllers; i++) {
	497	u32 v, base = 0;
	498	struct clk iclk, fclk;
	499	struct device *dev = &dummy_pdev.dev;
	500
	501	switch (i) {
	502	case 0:
	503	base = OMAP2_MMC1_BASE;
	504	break;
	505	case 1:
	506	base = OMAP2_MMC2_BASE;
	507	break;
	508	case 2:
	509	base = OMAP3_MMC3_BASE;
	510	break;
82cf818d	511	case 3:
	512	if (!cpu_is_omap44xx())
	513	return;
	514	base = OMAP4_MMC4_BASE;
	515	break;
	516	case 4:
	517	if (!cpu_is_omap44xx())
	518	return;
	519	base = OMAP4_MMC5_BASE;
	520	break;
917fa280 KH	521	}
917fa280 KH	522
82cf818d	523	if (cpu_is_omap44xx())
	524	base += OMAP4_MMC_REG_OFFSET;
	525
917fa280	526	dummy_pdev.id = i;
1e98ffa8	527	dev_set_name(&dummy_pdev.dev, "mmci-omap-hs.%d", i);
6f7607cc	528	iclk = clk_get(dev, "ick");
917fa280 KH	529	if (iclk && clk_enable(iclk))
	530	iclk = NULL;
	531
6f7607cc	532	fclk = clk_get(dev, "fck");
917fa280 KH	533	if (fclk && clk_enable(fclk))
	534	fclk = NULL;
	535
	536	if (!iclk \|\| !fclk) {
	537	printk(KERN_WARNING
	538	"%s: Unable to enable clocks for MMC%d, "
	539	"cannot reset.\n", __func__, i);
	540	break;
	541	}
	542
	543	omap_writel(MMCHS_SYSCONFIG_SWRESET, base + MMCHS_SYSCONFIG);
	544	v = omap_readl(base + MMCHS_SYSSTATUS);
	545	while (!(omap_readl(base + MMCHS_SYSSTATUS) &
	546	MMCHS_SYSSTATUS_RESETDONE))
	547	cpu_relax();
	548
	549	if (fclk) {
	550	clk_disable(fclk);
	551	clk_put(fclk);
	552	}
	553	if (iclk) {
	554	clk_disable(iclk);
	555	clk_put(iclk);
	556	}
	557	}
	558	}
	559	#else
	560	static inline void omap_hsmmc_reset(void) {}
	561	#endif
	562
d8874665 TL	563	#if defined(CONFIG_MMC_OMAP) \|\| defined(CONFIG_MMC_OMAP_MODULE) \|\| \
	564	defined(CONFIG_MMC_OMAP_HS) \|\| defined(CONFIG_MMC_OMAP_HS_MODULE)
	565
	566	static inline void omap2_mmc_mux(struct omap_mmc_platform_data *mmc_controller,
	567	int controller_nr)
	568	{
	569	if (cpu_is_omap2420() && controller_nr == 0) {
	570	omap_cfg_reg(H18_24XX_MMC_CMD);
	571	omap_cfg_reg(H15_24XX_MMC_CLKI);
	572	omap_cfg_reg(G19_24XX_MMC_CLKO);
	573	omap_cfg_reg(F20_24XX_MMC_DAT0);
	574	omap_cfg_reg(F19_24XX_MMC_DAT_DIR0);
	575	omap_cfg_reg(G18_24XX_MMC_CMD_DIR);
90c62bf0	576	if (mmc_controller->slots[0].wires == 4) {
d8874665 TL	577	omap_cfg_reg(H14_24XX_MMC_DAT1);
	578	omap_cfg_reg(E19_24XX_MMC_DAT2);
	579	omap_cfg_reg(D19_24XX_MMC_DAT3);
	580	omap_cfg_reg(E20_24XX_MMC_DAT_DIR1);
	581	omap_cfg_reg(F18_24XX_MMC_DAT_DIR2);
	582	omap_cfg_reg(E18_24XX_MMC_DAT_DIR3);
	583	}
	584
	585	/*
	586	* Use internal loop-back in MMC/SDIO Module Input Clock
	587	* selection
	588	*/
	589	if (mmc_controller->slots[0].internal_clock) {
	590	u32 v = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
	591	v \|= (1 << 24);
	592	omap_ctrl_writel(v, OMAP2_CONTROL_DEVCONF0);
	593	}
	594	}
57b9daa0	595
4596d14a	596	if (cpu_is_omap34xx()) {
57b9daa0 VP	597	if (controller_nr == 0) {
	598	omap_cfg_reg(N28_3430_MMC1_CLK);
	599	omap_cfg_reg(M27_3430_MMC1_CMD);
	600	omap_cfg_reg(N27_3430_MMC1_DAT0);
	601	if (mmc_controller->slots[0].wires == 4 \|\|
	602	mmc_controller->slots[0].wires == 8) {
	603	omap_cfg_reg(N26_3430_MMC1_DAT1);
	604	omap_cfg_reg(N25_3430_MMC1_DAT2);
	605	omap_cfg_reg(P28_3430_MMC1_DAT3);
	606	}
	607	if (mmc_controller->slots[0].wires == 8) {
	608	omap_cfg_reg(P27_3430_MMC1_DAT4);
	609	omap_cfg_reg(P26_3430_MMC1_DAT5);
	610	omap_cfg_reg(R27_3430_MMC1_DAT6);
	611	omap_cfg_reg(R25_3430_MMC1_DAT7);
	612	}
	613	}
	614	if (controller_nr == 1) {
	615	/* MMC2 */
	616	omap_cfg_reg(AE2_3430_MMC2_CLK);
	617	omap_cfg_reg(AG5_3430_MMC2_CMD);
	618	omap_cfg_reg(AH5_3430_MMC2_DAT0);
	619
	620	/*
	621	* For 8 wire configurations, Lines DAT4, 5, 6 and 7 need to be muxed
	622	* in the board-*.c files
	623	*/
	624	if (mmc_controller->slots[0].wires == 4 \|\|
	625	mmc_controller->slots[0].wires == 8) {
	626	omap_cfg_reg(AH4_3430_MMC2_DAT1);
	627	omap_cfg_reg(AG4_3430_MMC2_DAT2);
	628	omap_cfg_reg(AF4_3430_MMC2_DAT3);
	629	}
4679232d M	630	if (mmc_controller->slots[0].wires == 8) {
	631	omap_cfg_reg(AE4_3430_MMC2_DAT4);
	632	omap_cfg_reg(AH3_3430_MMC2_DAT5);
	633	omap_cfg_reg(AF3_3430_MMC2_DAT6);
	634	omap_cfg_reg(AE3_3430_MMC2_DAT7);
	635	}
57b9daa0 VP	636	}
	637
	638	/*
	639	* For MMC3 the pins need to be muxed in the board-*.c files
	640	*/
	641	}
d8874665 TL	642	}
	643
	644	void __init omap2_init_mmc(struct omap_mmc_platform_data **mmc_data,
	645	int nr_controllers)
	646	{
	647	int i;
0dffb5c5	648	char *name;
d8874665 TL	649
	650	for (i = 0; i < nr_controllers; i++) {
	651	unsigned long base, size;
	652	unsigned int irq = 0;
	653
	654	if (!mmc_data[i])
	655	continue;
	656
	657	omap2_mmc_mux(mmc_data[i], i);
	658
	659	switch (i) {
	660	case 0:
	661	base = OMAP2_MMC1_BASE;
	662	irq = INT_24XX_MMC_IRQ;
	663	break;
	664	case 1:
	665	base = OMAP2_MMC2_BASE;
	666	irq = INT_24XX_MMC2_IRQ;
	667	break;
	668	case 2:
82cf818d	669	if (!cpu_is_omap44xx() && !cpu_is_omap34xx())
d8874665 TL	670	return;
	671	base = OMAP3_MMC3_BASE;
	672	irq = INT_34XX_MMC3_IRQ;
	673	break;
82cf818d	674	case 3:
	675	if (!cpu_is_omap44xx())
	676	return;
	677	base = OMAP4_MMC4_BASE + OMAP4_MMC_REG_OFFSET;
	678	irq = INT_44XX_MMC4_IRQ;
	679	break;
	680	case 4:
	681	if (!cpu_is_omap44xx())
	682	return;
	683	base = OMAP4_MMC5_BASE + OMAP4_MMC_REG_OFFSET;
	684	irq = INT_44XX_MMC5_IRQ;
	685	break;
d8874665 TL	686	default:
	687	continue;
	688	}
	689
0dffb5c5	690	if (cpu_is_omap2420()) {
d8874665	691	size = OMAP2420_MMC_SIZE;
0dffb5c5	692	name = "mmci-omap";
82cf818d	693	} else if (cpu_is_omap44xx()) {
	694	if (i < 3) {
	695	base += OMAP4_MMC_REG_OFFSET;
	696	irq += IRQ_GIC_START;
	697	}
	698	size = OMAP4_HSMMC_SIZE;
	699	name = "mmci-omap-hs";
0dffb5c5	700	} else {
82cf818d	701	size = OMAP3_HSMMC_SIZE;
0dffb5c5 TL	702	name = "mmci-omap-hs";
	703	}
	704	omap_mmc_add(name, i, base, size, irq, mmc_data[i]);
d8874665 TL	705	};
	706	}
	707
	708	#endif
	709
	710	/-------------------------------------------------------------------------/
	711
646e3ed1 TL	712	#if defined(CONFIG_HDQ_MASTER_OMAP) \|\| defined(CONFIG_HDQ_MASTER_OMAP_MODULE)
	713	#if defined(CONFIG_ARCH_OMAP2430) \|\| defined(CONFIG_ARCH_OMAP3430)
	714	#define OMAP_HDQ_BASE 0x480B2000
	715	#endif
	716	static struct resource omap_hdq_resources[] = {
	717	{
	718	.start = OMAP_HDQ_BASE,
	719	.end = OMAP_HDQ_BASE + 0x1C,
	720	.flags = IORESOURCE_MEM,
	721	},
	722	{
	723	.start = INT_24XX_HDQ_IRQ,
	724	.flags = IORESOURCE_IRQ,
	725	},
	726	};
	727	static struct platform_device omap_hdq_dev = {
	728	.name = "omap_hdq",
	729	.id = 0,
	730	.dev = {
	731	.platform_data = NULL,
	732	},
	733	.num_resources = ARRAY_SIZE(omap_hdq_resources),
	734	.resource = omap_hdq_resources,
	735	};
	736	static inline void omap_hdq_init(void)
	737	{
	738	(void) platform_device_register(&omap_hdq_dev);
	739	}
	740	#else
	741	static inline void omap_hdq_init(void) {}
	742	#endif
	743
1dbae815 TL	744	/-------------------------------------------------------------------------/
	745
	746	static int __init omap2_init_devices(void)
	747	{
	748	/* please keep these calls, and their implementations above,
	749	* in alphabetical order so they're easier to sort through.
	750	*/
917fa280	751	omap_hsmmc_reset();
828c707e	752	omap_init_camera();
c40fae95	753	omap_init_mbox();
ed7eb9d9	754	omap_init_mcspi();
646e3ed1	755	omap_hdq_init();
9b6553cd	756	omap_init_sti();
646e3ed1	757	omap_init_sha1_md5();
1dbae815 TL	758
	759	return 0;
	760	}
	761	arch_initcall(omap2_init_devices);