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ARM: OMAP2+: Mark omap_hsmmc_init and omap_mux related functions as __init
[deliverable/linux.git] / arch / arm / mach-omap2 / devices.c
CommitLineData
1dbae815
TL		 1/*
2 * linux/arch/arm/mach-omap2/devices.c
3 *
4 * OMAP2 platform device setup/initialization
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 */
2f8163ba 11#include <linux/gpio.h>
1dbae815
TL		 12#include <linux/kernel.h>
13#include <linux/init.h>
14#include <linux/platform_device.h>
fced80c7 15#include <linux/io.h>
917fa280 16#include <linux/clk.h>
f2ce6231 17#include <linux/err.h>
1a5d8190 18#include <linux/slab.h>
ad8dfac6 19#include <linux/of.h>
1dbae815 20
a09e64fb 21#include <mach/hardware.h>
88341334 22#include <mach/irqs.h>
1dbae815
TL		 23#include <asm/mach-types.h>
24#include <asm/mach/map.h>
88341334 25#include <asm/pmu.h>
1dbae815 26
ce491cf8
TL		 27#include <plat/tc.h>
28#include <plat/board.h>
a09f73fa 29#include <plat/mcbsp.h>
ce491cf8 30#include <plat/mmc.h>
ee5500c4 31#include <plat/dma.h>
f2ce6231
VC		 32#include <plat/omap_hwmod.h>
33#include <plat/omap_device.h>
59556765 34#include <plat/omap4-keypad.h>
1dbae815 35
4896e394 36#include "mux.h"
4814ced5 37#include "control.h"
a11f6706 38#include "devices.h"
4896e394 39
0abcf618 40#define L3_MODULES_MAX_LEN 12
a4dc616a 41#define L3_MODULES 3
0abcf618 42
43static int __init omap3_l3_init(void)
44{
45 int l;
46 struct omap_hwmod *oh;
3528c58e 47 struct platform_device *pdev;
0abcf618 48 char oh_name[L3_MODULES_MAX_LEN];
49
50 /*
51 * To avoid code running on other OMAPs in
52 * multi-omap builds
53 */
54 if (!(cpu_is_omap34xx()))
55 return -ENODEV;
56
57 l = snprintf(oh_name, L3_MODULES_MAX_LEN, "l3_main");
58
59 oh = omap_hwmod_lookup(oh_name);
60
61 if (!oh)
62 pr_err("could not look up %s\n", oh_name);
63
3528c58e 64 pdev = omap_device_build("omap_l3_smx", 0, oh, NULL, 0,
0abcf618 65 NULL, 0, 0);
66
3528c58e 67 WARN(IS_ERR(pdev), "could not build omap_device for %s\n", oh_name);
0abcf618 68
3528c58e 69 return IS_ERR(pdev) ? PTR_ERR(pdev) : 0;
0abcf618 70}
71postcore_initcall(omap3_l3_init);
72
a4dc616a 73static int __init omap4_l3_init(void)
74{
75 int l, i;
76 struct omap_hwmod *oh[3];
3528c58e 77 struct platform_device *pdev;
a4dc616a 78 char oh_name[L3_MODULES_MAX_LEN];
79
ad8dfac6
BC		 80 /* If dtb is there, the devices will be created dynamically */
81 if (of_have_populated_dt())
82 return -ENODEV;
83
a4dc616a 84 /*
85 * To avoid code running on other OMAPs in
86 * multi-omap builds
87 */
88 if (!(cpu_is_omap44xx()))
89 return -ENODEV;
90
91 for (i = 0; i < L3_MODULES; i++) {
92 l = snprintf(oh_name, L3_MODULES_MAX_LEN, "l3_main_%d", i+1);
93
94 oh[i] = omap_hwmod_lookup(oh_name);
95 if (!(oh[i]))
96 pr_err("could not look up %s\n", oh_name);
97 }
98
3528c58e 99 pdev = omap_device_build_ss("omap_l3_noc", 0, oh, 3, NULL,
a4dc616a 100 0, NULL, 0, 0);
101
3528c58e 102 WARN(IS_ERR(pdev), "could not build omap_device for %s\n", oh_name);
a4dc616a 103
3528c58e 104 return IS_ERR(pdev) ? PTR_ERR(pdev) : 0;
a4dc616a 105}
106postcore_initcall(omap4_l3_init);
107
828c707e 108#if defined(CONFIG_VIDEO_OMAP2) || defined(CONFIG_VIDEO_OMAP2_MODULE)
c40fae95 109
cfe2cde6 110static struct resource omap2cam_resources[] = {
c40fae95 111 {
828c707e
TL		 112 .start = OMAP24XX_CAMERA_BASE,
113 .end = OMAP24XX_CAMERA_BASE + 0xfff,
114 .flags = IORESOURCE_MEM,
115 },
116 {
117 .start = INT_24XX_CAM_IRQ,
118 .flags = IORESOURCE_IRQ,
119 }
120};
121
cfe2cde6 122static struct platform_device omap2cam_device = {
828c707e
TL		 123 .name = "omap24xxcam",
124 .id = -1,
cfe2cde6
SA		 125 .num_resources = ARRAY_SIZE(omap2cam_resources),
126 .resource = omap2cam_resources,
828c707e 127};
a11f6706 128#endif
828c707e 129
1a51a0ce
OBC		 130#if defined(CONFIG_IOMMU_API)
131
132#include <plat/iommu.h>
133
828c707e
TL		 134static struct resource omap3isp_resources[] = {
135 {
136 .start = OMAP3430_ISP_BASE,
137 .end = OMAP3430_ISP_END,
138 .flags = IORESOURCE_MEM,
139 },
828c707e
TL		 140 {
141 .start = OMAP3430_ISP_CCP2_BASE,
142 .end = OMAP3430_ISP_CCP2_END,
143 .flags = IORESOURCE_MEM,
144 },
145 {
146 .start = OMAP3430_ISP_CCDC_BASE,
147 .end = OMAP3430_ISP_CCDC_END,
148 .flags = IORESOURCE_MEM,
149 },
150 {
151 .start = OMAP3430_ISP_HIST_BASE,
152 .end = OMAP3430_ISP_HIST_END,
153 .flags = IORESOURCE_MEM,
154 },
155 {
156 .start = OMAP3430_ISP_H3A_BASE,
157 .end = OMAP3430_ISP_H3A_END,
158 .flags = IORESOURCE_MEM,
159 },
160 {
161 .start = OMAP3430_ISP_PREV_BASE,
162 .end = OMAP3430_ISP_PREV_END,
163 .flags = IORESOURCE_MEM,
164 },
165 {
166 .start = OMAP3430_ISP_RESZ_BASE,
167 .end = OMAP3430_ISP_RESZ_END,
168 .flags = IORESOURCE_MEM,
169 },
170 {
171 .start = OMAP3430_ISP_SBL_BASE,
172 .end = OMAP3430_ISP_SBL_END,
173 .flags = IORESOURCE_MEM,
174 },
175 {
6817a69a
TT		 176 .start = OMAP3430_ISP_CSI2A_REGS1_BASE,
177 .end = OMAP3430_ISP_CSI2A_REGS1_END,
828c707e
TL		 178 .flags = IORESOURCE_MEM,
179 },
180 {
6817a69a
TT		 181 .start = OMAP3430_ISP_CSIPHY2_BASE,
182 .end = OMAP3430_ISP_CSIPHY2_END,
183 .flags = IORESOURCE_MEM,
184 },
185 {
186 .start = OMAP3630_ISP_CSI2A_REGS2_BASE,
187 .end = OMAP3630_ISP_CSI2A_REGS2_END,
828c707e
TL		 188 .flags = IORESOURCE_MEM,
189 },
190 {
6817a69a
TT		 191 .start = OMAP3630_ISP_CSI2C_REGS1_BASE,
192 .end = OMAP3630_ISP_CSI2C_REGS1_END,
193 .flags = IORESOURCE_MEM,
194 },
195 {
196 .start = OMAP3630_ISP_CSIPHY1_BASE,
197 .end = OMAP3630_ISP_CSIPHY1_END,
198 .flags = IORESOURCE_MEM,
199 },
200 {
201 .start = OMAP3630_ISP_CSI2C_REGS2_BASE,
202 .end = OMAP3630_ISP_CSI2C_REGS2_END,
828c707e
TL		 203 .flags = IORESOURCE_MEM,
204 },
205 {
206 .start = INT_34XX_CAM_IRQ,
207 .flags = IORESOURCE_IRQ,
208 }
209};
210
211static struct platform_device omap3isp_device = {
212 .name = "omap3isp",
213 .id = -1,
214 .num_resources = ARRAY_SIZE(omap3isp_resources),
215 .resource = omap3isp_resources,
216};
217
c8eaab3b
OBC		 218static struct omap_iommu_arch_data omap3_isp_iommu = {
219 .name = "isp",
220};
221
a11f6706 222int omap3_init_camera(struct isp_platform_data *pdata)
828c707e 223{
a11f6706 224 omap3isp_device.dev.platform_data = pdata;
c8eaab3b
OBC		 225 omap3isp_device.dev.archdata.iommu = &omap3_isp_iommu;
226
a11f6706 227 return platform_device_register(&omap3isp_device);
828c707e 228}
828c707e 229
1a51a0ce
OBC		 230#else /* !CONFIG_IOMMU_API */
231
232int omap3_init_camera(struct isp_platform_data *pdata)
233{
234 return 0;
235}
236
237#endif
238
828c707e
TL		 239static inline void omap_init_camera(void)
240{
cfe2cde6
SA		 241#if defined(CONFIG_VIDEO_OMAP2) || defined(CONFIG_VIDEO_OMAP2_MODULE)
242 if (cpu_is_omap24xx())
243 platform_device_register(&omap2cam_device);
828c707e 244#endif
cfe2cde6 245}
828c707e 246
59556765 247int __init omap4_keyboard_init(struct omap4_keypad_platform_data
f67df6c6 248 *sdp4430_keypad_data, struct omap_board_data *bdata)
59556765 249{
3528c58e 250 struct platform_device *pdev;
59556765
SR		 251 struct omap_hwmod *oh;
252 struct omap4_keypad_platform_data *keypad_data;
253 unsigned int id = -1;
254 char *oh_name = "kbd";
255 char *name = "omap4-keypad";
256
257 oh = omap_hwmod_lookup(oh_name);
258 if (!oh) {
259 pr_err("Could not look up %s\n", oh_name);
260 return -ENODEV;
261 }
262
263 keypad_data = sdp4430_keypad_data;
264
3528c58e 265 pdev = omap_device_build(name, id, oh, keypad_data,
f718e2c0 266 sizeof(struct omap4_keypad_platform_data), NULL, 0, 0);
59556765 267
3528c58e 268 if (IS_ERR(pdev)) {
25985edc 269 WARN(1, "Can't build omap_device for %s:%s.\n",
59556765 270 name, oh->name);
3528c58e 271 return PTR_ERR(pdev);
59556765 272 }
f67df6c6 273 oh->mux = omap_hwmod_mux_init(bdata->pads, bdata->pads_cnt);
59556765
SR		 274
275 return 0;
276}
277
6c20a683 278#if defined(CONFIG_OMAP_MBOX_FWK) || defined(CONFIG_OMAP_MBOX_FWK_MODULE)
c40fae95
TL		 279static inline void omap_init_mbox(void)
280{
69dbf857 281 struct omap_hwmod *oh;
3528c58e 282 struct platform_device *pdev;
69dbf857
FC		 283
284 oh = omap_hwmod_lookup("mailbox");
285 if (!oh) {
286 pr_err("%s: unable to find hwmod\n", __func__);
6c20a683
HD		 287 return;
288 }
69dbf857 289
f718e2c0 290 pdev = omap_device_build("omap-mailbox", -1, oh, NULL, 0, NULL, 0, 0);
3528c58e
KH		 291 WARN(IS_ERR(pdev), "%s: could not build device, err %ld\n",
292 __func__, PTR_ERR(pdev));
c40fae95
TL		 293}
294#else
295static inline void omap_init_mbox(void) { }
6c20a683 296#endif /* CONFIG_OMAP_MBOX_FWK */
c40fae95 297
9b6553cd 298static inline void omap_init_sti(void) {}
9b6553cd 299
f0fba2ad
LG		 300#if defined(CONFIG_SND_SOC) || defined(CONFIG_SND_SOC_MODULE)
301
302static struct platform_device omap_pcm = {
303 .name = "omap-pcm-audio",
304 .id = -1,
305};
306
307/*
308 * OMAP2420 has 2 McBSP ports
309 * OMAP2430 has 5 McBSP ports
310 * OMAP3 has 5 McBSP ports
311 * OMAP4 has 4 McBSP ports
312 */
313OMAP_MCBSP_PLATFORM_DEVICE(1);
314OMAP_MCBSP_PLATFORM_DEVICE(2);
315OMAP_MCBSP_PLATFORM_DEVICE(3);
316OMAP_MCBSP_PLATFORM_DEVICE(4);
317OMAP_MCBSP_PLATFORM_DEVICE(5);
318
319static void omap_init_audio(void)
320{
321 platform_device_register(&omap_mcbsp1);
322 platform_device_register(&omap_mcbsp2);
323 if (cpu_is_omap243x() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
324 platform_device_register(&omap_mcbsp3);
325 platform_device_register(&omap_mcbsp4);
326 }
327 if (cpu_is_omap243x() || cpu_is_omap34xx())
328 platform_device_register(&omap_mcbsp5);
329
330 platform_device_register(&omap_pcm);
331}
332
333#else
334static inline void omap_init_audio(void) {}
335#endif
336
d231f5cb
PU		 337#if defined(CONFIG_SND_OMAP_SOC_MCPDM) || \
338 defined(CONFIG_SND_OMAP_SOC_MCPDM_MODULE)
339
d231f5cb
PU		 340static void omap_init_mcpdm(void)
341{
342 struct omap_hwmod *oh;
927dbbb2 343 struct platform_device *pdev;
d231f5cb
PU		 344
345 oh = omap_hwmod_lookup("mcpdm");
346 if (!oh) {
347 printk(KERN_ERR "Could not look up mcpdm hw_mod\n");
348 return;
349 }
350
927dbbb2
PU		 351 pdev = omap_device_build("omap-mcpdm", -1, oh, NULL, 0, NULL, 0, 0);
352 WARN(IS_ERR(pdev), "Can't build omap_device for omap-mcpdm.\n");
d231f5cb
PU		 353}
354#else
355static inline void omap_init_mcpdm(void) {}
356#endif
357
de9eb097
PU		 358#if defined(CONFIG_SND_OMAP_SOC_DMIC) || \
359 defined(CONFIG_SND_OMAP_SOC_DMIC_MODULE)
360
361static void omap_init_dmic(void)
362{
363 struct omap_hwmod *oh;
364 struct platform_device *pdev;
365
366 oh = omap_hwmod_lookup("dmic");
367 if (!oh) {
368 printk(KERN_ERR "Could not look up mcpdm hw_mod\n");
369 return;
370 }
371
372 pdev = omap_device_build("omap-dmic", -1, oh, NULL, 0, NULL, 0, 0);
373 WARN(IS_ERR(pdev), "Can't build omap_device for omap-dmic.\n");
374}
375#else
376static inline void omap_init_dmic(void) {}
377#endif
378
646e3ed1 379#if defined(CONFIG_SPI_OMAP24XX) || defined(CONFIG_SPI_OMAP24XX_MODULE)
ed7eb9d9 380
ce491cf8 381#include <plat/mcspi.h>
ed7eb9d9 382
1a5d8190 383static int omap_mcspi_init(struct omap_hwmod *oh, void *unused)
af41a12f 384{
3528c58e 385 struct platform_device *pdev;
1a5d8190
C		 386 char *name = "omap2_mcspi";
387 struct omap2_mcspi_platform_config *pdata;
388 static int spi_num;
389 struct omap2_mcspi_dev_attr *mcspi_attrib = oh->dev_attr;
390
391 pdata = kzalloc(sizeof(*pdata), GFP_KERNEL);
392 if (!pdata) {
393 pr_err("Memory allocation for McSPI device failed\n");
394 return -ENOMEM;
395 }
af41a12f 396
1a5d8190
C		 397 pdata->num_cs = mcspi_attrib->num_chipselect;
398 switch (oh->class->rev) {
399 case OMAP2_MCSPI_REV:
400 case OMAP3_MCSPI_REV:
401 pdata->regs_offset = 0;
402 break;
403 case OMAP4_MCSPI_REV:
404 pdata->regs_offset = OMAP4_MCSPI_REG_OFFSET;
405 break;
406 default:
407 pr_err("Invalid McSPI Revision value\n");
e0feca89 408 kfree(pdata);
1a5d8190
C		 409 return -EINVAL;
410 }
af41a12f 411
1a5d8190 412 spi_num++;
3528c58e 413 pdev = omap_device_build(name, spi_num, oh, pdata,
f718e2c0 414 sizeof(*pdata), NULL, 0, 0);
3528c58e 415 WARN(IS_ERR(pdev), "Can't build omap_device for %s:%s\n",
1a5d8190
C		 416 name, oh->name);
417 kfree(pdata);
418 return 0;
af41a12f 419}
af41a12f
TL		 420
421static void omap_init_mcspi(void)
422{
1a5d8190 423 omap_hwmod_for_each_by_class("mcspi", omap_mcspi_init, NULL);
ed7eb9d9
JY		 424}
425
426#else
427static inline void omap_init_mcspi(void) {}
428#endif
429
88341334
WD		 430static struct resource omap2_pmu_resource = {
431 .start = 3,
432 .end = 3,
433 .flags = IORESOURCE_IRQ,
434};
435
436static struct resource omap3_pmu_resource = {
437 .start = INT_34XX_BENCH_MPU_EMUL,
438 .end = INT_34XX_BENCH_MPU_EMUL,
439 .flags = IORESOURCE_IRQ,
440};
441
442static struct platform_device omap_pmu_device = {
443 .name = "arm-pmu",
444 .id = ARM_PMU_DEVICE_CPU,
445 .num_resources = 1,
446};
447
448static void omap_init_pmu(void)
449{
450 if (cpu_is_omap24xx())
451 omap_pmu_device.resource = &omap2_pmu_resource;
452 else if (cpu_is_omap34xx())
453 omap_pmu_device.resource = &omap3_pmu_resource;
454 else
455 return;
456
457 platform_device_register(&omap_pmu_device);
458}
459
460
ee5500c4
DK		 461#if defined(CONFIG_CRYPTO_DEV_OMAP_SHAM) || defined(CONFIG_CRYPTO_DEV_OMAP_SHAM_MODULE)
462
edc774ed 463#ifdef CONFIG_ARCH_OMAP2
ee5500c4 464static struct resource omap2_sham_resources[] = {
646e3ed1
TL		 465 {
466 .start = OMAP24XX_SEC_SHA1MD5_BASE,
467 .end = OMAP24XX_SEC_SHA1MD5_BASE + 0x64,
468 .flags = IORESOURCE_MEM,
469 },
470 {
471 .start = INT_24XX_SHA1MD5,
472 .flags = IORESOURCE_IRQ,
473 }
474};
ee5500c4
DK		 475static int omap2_sham_resources_sz = ARRAY_SIZE(omap2_sham_resources);
476#else
477#define omap2_sham_resources NULL
478#define omap2_sham_resources_sz 0
479#endif
646e3ed1 480
edc774ed 481#ifdef CONFIG_ARCH_OMAP3
ee5500c4
DK		 482static struct resource omap3_sham_resources[] = {
483 {
484 .start = OMAP34XX_SEC_SHA1MD5_BASE,
485 .end = OMAP34XX_SEC_SHA1MD5_BASE + 0x64,
486 .flags = IORESOURCE_MEM,
487 },
488 {
489 .start = INT_34XX_SHA1MD52_IRQ,
490 .flags = IORESOURCE_IRQ,
491 },
492 {
493 .start = OMAP34XX_DMA_SHA1MD5_RX,
494 .flags = IORESOURCE_DMA,
495 }
496};
497static int omap3_sham_resources_sz = ARRAY_SIZE(omap3_sham_resources);
498#else
499#define omap3_sham_resources NULL
500#define omap3_sham_resources_sz 0
501#endif
502
503static struct platform_device sham_device = {
504 .name = "omap-sham",
646e3ed1 505 .id = -1,
646e3ed1
TL		 506};
507
ee5500c4 508static void omap_init_sham(void)
646e3ed1 509{
ee5500c4
DK		 510 if (cpu_is_omap24xx()) {
511 sham_device.resource = omap2_sham_resources;
512 sham_device.num_resources = omap2_sham_resources_sz;
513 } else if (cpu_is_omap34xx()) {
514 sham_device.resource = omap3_sham_resources;
515 sham_device.num_resources = omap3_sham_resources_sz;
516 } else {
517 pr_err("%s: platform not supported\n", __func__);
518 return;
519 }
520 platform_device_register(&sham_device);
646e3ed1
TL		 521}
522#else
ee5500c4 523static inline void omap_init_sham(void) { }
646e3ed1
TL		 524#endif
525
b744c679
DK		 526#if defined(CONFIG_CRYPTO_DEV_OMAP_AES) || defined(CONFIG_CRYPTO_DEV_OMAP_AES_MODULE)
527
82a0c149 528#ifdef CONFIG_ARCH_OMAP2
b744c679
DK		 529static struct resource omap2_aes_resources[] = {
530 {
531 .start = OMAP24XX_SEC_AES_BASE,
532 .end = OMAP24XX_SEC_AES_BASE + 0x4C,
533 .flags = IORESOURCE_MEM,
534 },
535 {
536 .start = OMAP24XX_DMA_AES_TX,
537 .flags = IORESOURCE_DMA,
538 },
539 {
540 .start = OMAP24XX_DMA_AES_RX,
541 .flags = IORESOURCE_DMA,
542 }
543};
544static int omap2_aes_resources_sz = ARRAY_SIZE(omap2_aes_resources);
545#else
546#define omap2_aes_resources NULL
547#define omap2_aes_resources_sz 0
548#endif
549
82a0c149 550#ifdef CONFIG_ARCH_OMAP3
b744c679
DK		 551static struct resource omap3_aes_resources[] = {
552 {
553 .start = OMAP34XX_SEC_AES_BASE,
554 .end = OMAP34XX_SEC_AES_BASE + 0x4C,
555 .flags = IORESOURCE_MEM,
556 },
557 {
558 .start = OMAP34XX_DMA_AES2_TX,
559 .flags = IORESOURCE_DMA,
560 },
561 {
562 .start = OMAP34XX_DMA_AES2_RX,
563 .flags = IORESOURCE_DMA,
564 }
565};
566static int omap3_aes_resources_sz = ARRAY_SIZE(omap3_aes_resources);
567#else
568#define omap3_aes_resources NULL
569#define omap3_aes_resources_sz 0
570#endif
571
572static struct platform_device aes_device = {
573 .name = "omap-aes",
574 .id = -1,
575};
576
577static void omap_init_aes(void)
578{
579 if (cpu_is_omap24xx()) {
580 aes_device.resource = omap2_aes_resources;
581 aes_device.num_resources = omap2_aes_resources_sz;
582 } else if (cpu_is_omap34xx()) {
583 aes_device.resource = omap3_aes_resources;
584 aes_device.num_resources = omap3_aes_resources_sz;
585 } else {
586 pr_err("%s: platform not supported\n", __func__);
587 return;
588 }
589 platform_device_register(&aes_device);
590}
591
592#else
593static inline void omap_init_aes(void) { }
594#endif
595
d8874665
TL		 596/*-------------------------------------------------------------------------*/
597
e08016d0 598#if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE)
917fa280 599
e08016d0
AG		 600static inline void omap242x_mmc_mux(struct omap_mmc_platform_data
601 *mmc_controller)
d8874665 602{
ed8303fc 603 if ((mmc_controller->slots[0].switch_pin > 0) && \
604 (mmc_controller->slots[0].switch_pin < OMAP_MAX_GPIO_LINES))
605 omap_mux_init_gpio(mmc_controller->slots[0].switch_pin,
606 OMAP_PIN_INPUT_PULLUP);
607 if ((mmc_controller->slots[0].gpio_wp > 0) && \
608 (mmc_controller->slots[0].gpio_wp < OMAP_MAX_GPIO_LINES))
609 omap_mux_init_gpio(mmc_controller->slots[0].gpio_wp,
610 OMAP_PIN_INPUT_PULLUP);
611
e08016d0
AG		 612 omap_mux_init_signal("sdmmc_cmd", 0);
613 omap_mux_init_signal("sdmmc_clki", 0);
614 omap_mux_init_signal("sdmmc_clko", 0);
615 omap_mux_init_signal("sdmmc_dat0", 0);
616 omap_mux_init_signal("sdmmc_dat_dir0", 0);
617 omap_mux_init_signal("sdmmc_cmd_dir", 0);
618 if (mmc_controller->slots[0].caps & MMC_CAP_4_BIT_DATA) {
619 omap_mux_init_signal("sdmmc_dat1", 0);
620 omap_mux_init_signal("sdmmc_dat2", 0);
621 omap_mux_init_signal("sdmmc_dat3", 0);
622 omap_mux_init_signal("sdmmc_dat_dir1", 0);
623 omap_mux_init_signal("sdmmc_dat_dir2", 0);
624 omap_mux_init_signal("sdmmc_dat_dir3", 0);
d8874665 625 }
57b9daa0 626
e08016d0
AG		 627 /*
628 * Use internal loop-back in MMC/SDIO Module Input Clock
629 * selection
630 */
631 if (mmc_controller->slots[0].internal_clock) {
632 u32 v = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
633 v |= (1 << 24);
634 omap_ctrl_writel(v, OMAP2_CONTROL_DEVCONF0);
57b9daa0 635 }
d8874665
TL		 636}
637
e08016d0 638void __init omap242x_init_mmc(struct omap_mmc_platform_data **mmc_data)
d8874665 639{
e08016d0 640 char *name = "mmci-omap";
d8874665 641
e08016d0
AG		 642 if (!mmc_data[0]) {
643 pr_err("%s fails: Incomplete platform data\n", __func__);
644 return;
645 }
d8874665 646
e08016d0
AG		 647 omap242x_mmc_mux(mmc_data[0]);
648 omap_mmc_add(name, 0, OMAP2_MMC1_BASE, OMAP2420_MMC_SIZE,
649 INT_24XX_MMC_IRQ, mmc_data[0]);
d8874665
TL		 650}
651
652#endif
653
654/*-------------------------------------------------------------------------*/
655
646e3ed1 656#if defined(CONFIG_HDQ_MASTER_OMAP) || defined(CONFIG_HDQ_MASTER_OMAP_MODULE)
59b479e0 657#if defined(CONFIG_SOC_OMAP2430) || defined(CONFIG_SOC_OMAP3430)
646e3ed1
TL		 658#define OMAP_HDQ_BASE 0x480B2000
659#endif
660static struct resource omap_hdq_resources[] = {
661 {
662 .start = OMAP_HDQ_BASE,
663 .end = OMAP_HDQ_BASE + 0x1C,
664 .flags = IORESOURCE_MEM,
665 },
666 {
667 .start = INT_24XX_HDQ_IRQ,
668 .flags = IORESOURCE_IRQ,
669 },
670};
671static struct platform_device omap_hdq_dev = {
672 .name = "omap_hdq",
673 .id = 0,
674 .dev = {
675 .platform_data = NULL,
676 },
677 .num_resources = ARRAY_SIZE(omap_hdq_resources),
678 .resource = omap_hdq_resources,
679};
680static inline void omap_hdq_init(void)
681{
682 (void) platform_device_register(&omap_hdq_dev);
683}
684#else
685static inline void omap_hdq_init(void) {}
686#endif
687
b227358d
VH		 688/*---------------------------------------------------------------------------*/
689
690#if defined(CONFIG_VIDEO_OMAP2_VOUT) || \
691 defined(CONFIG_VIDEO_OMAP2_VOUT_MODULE)
692#if defined(CONFIG_FB_OMAP2) || defined(CONFIG_FB_OMAP2_MODULE)
693static struct resource omap_vout_resource[3 - CONFIG_FB_OMAP2_NUM_FBS] = {
694};
695#else
696static struct resource omap_vout_resource[2] = {
697};
698#endif
699
700static struct platform_device omap_vout_device = {
701 .name = "omap_vout",
702 .num_resources = ARRAY_SIZE(omap_vout_resource),
703 .resource = &omap_vout_resource[0],
704 .id = -1,
705};
706static void omap_init_vout(void)
707{
708 if (platform_device_register(&omap_vout_device) < 0)
709 printk(KERN_ERR "Unable to register OMAP-VOUT device\n");
710}
711#else
712static inline void omap_init_vout(void) {}
713#endif
714
1dbae815
TL		 715/*-------------------------------------------------------------------------*/
716
717static int __init omap2_init_devices(void)
718{
81fbc5ef
PW		 719 /*
720 * please keep these calls, and their implementations above,
1dbae815
TL		 721 * in alphabetical order so they're easier to sort through.
722 */
f0fba2ad 723 omap_init_audio();
d231f5cb 724 omap_init_mcpdm();
de9eb097 725 omap_init_dmic();
828c707e 726 omap_init_camera();
c40fae95 727 omap_init_mbox();
ed7eb9d9 728 omap_init_mcspi();
88341334 729 omap_init_pmu();
646e3ed1 730 omap_hdq_init();
9b6553cd 731 omap_init_sti();
ee5500c4 732 omap_init_sham();
b744c679 733 omap_init_aes();
b227358d 734 omap_init_vout();
1dbae815
TL		 735
736 return 0;
737}
738arch_initcall(omap2_init_devices);
f2ce6231
VC		 739
740#if defined(CONFIG_OMAP_WATCHDOG) || defined(CONFIG_OMAP_WATCHDOG_MODULE)
f2ce6231
VC		 741static int __init omap_init_wdt(void)
742{
743 int id = -1;
3528c58e 744 struct platform_device *pdev;
f2ce6231
VC		 745 struct omap_hwmod *oh;
746 char *oh_name = "wd_timer2";
747 char *dev_name = "omap_wdt";
748
749 if (!cpu_class_is_omap2())
750 return 0;
751
752 oh = omap_hwmod_lookup(oh_name);
753 if (!oh) {
754 pr_err("Could not look up wd_timer%d hwmod\n", id);
755 return -EINVAL;
756 }
757
f718e2c0 758 pdev = omap_device_build(dev_name, id, oh, NULL, 0, NULL, 0, 0);
3528c58e 759 WARN(IS_ERR(pdev), "Can't build omap_device for %s:%s.\n",
f2ce6231
VC		 760 dev_name, oh->name);
761 return 0;
762}
763subsys_initcall(omap_init_wdt);
764#endif
Linux kernel - Deliverables
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