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OMAP: hsmmc: Move mux configuration to hsmmc.c
[deliverable/linux.git] / arch / arm / mach-omap2 / devices.c
CommitLineData
1dbae815
TL		 1/*
2 * linux/arch/arm/mach-omap2/devices.c
3 *
4 * OMAP2 platform device setup/initialization
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 */
11
1dbae815
TL		 12#include <linux/kernel.h>
13#include <linux/init.h>
14#include <linux/platform_device.h>
fced80c7 15#include <linux/io.h>
917fa280 16#include <linux/clk.h>
f2ce6231 17#include <linux/err.h>
1a5d8190 18#include <linux/slab.h>
1dbae815 19
a09e64fb 20#include <mach/hardware.h>
88341334 21#include <mach/irqs.h>
1dbae815
TL		 22#include <asm/mach-types.h>
23#include <asm/mach/map.h>
88341334 24#include <asm/pmu.h>
1dbae815 25
ce491cf8
TL		 26#include <plat/tc.h>
27#include <plat/board.h>
a09f73fa 28#include <plat/mcbsp.h>
a09e64fb 29#include <mach/gpio.h>
ce491cf8 30#include <plat/mmc.h>
ee5500c4 31#include <plat/dma.h>
f2ce6231
VC		 32#include <plat/omap_hwmod.h>
33#include <plat/omap_device.h>
59556765 34#include <plat/omap4-keypad.h>
1dbae815 35
4896e394 36#include "mux.h"
4814ced5 37#include "control.h"
4896e394 38
828c707e 39#if defined(CONFIG_VIDEO_OMAP2) || defined(CONFIG_VIDEO_OMAP2_MODULE)
c40fae95 40
828c707e 41static struct resource cam_resources[] = {
c40fae95 42 {
828c707e
TL		 43 .start = OMAP24XX_CAMERA_BASE,
44 .end = OMAP24XX_CAMERA_BASE + 0xfff,
45 .flags = IORESOURCE_MEM,
46 },
47 {
48 .start = INT_24XX_CAM_IRQ,
49 .flags = IORESOURCE_IRQ,
50 }
51};
52
53static struct platform_device omap_cam_device = {
54 .name = "omap24xxcam",
55 .id = -1,
56 .num_resources = ARRAY_SIZE(cam_resources),
57 .resource = cam_resources,
58};
59
60static inline void omap_init_camera(void)
61{
62 platform_device_register(&omap_cam_device);
63}
64
65#elif defined(CONFIG_VIDEO_OMAP3) || defined(CONFIG_VIDEO_OMAP3_MODULE)
66
67static struct resource omap3isp_resources[] = {
68 {
69 .start = OMAP3430_ISP_BASE,
70 .end = OMAP3430_ISP_END,
71 .flags = IORESOURCE_MEM,
72 },
73 {
74 .start = OMAP3430_ISP_CBUFF_BASE,
75 .end = OMAP3430_ISP_CBUFF_END,
76 .flags = IORESOURCE_MEM,
77 },
78 {
79 .start = OMAP3430_ISP_CCP2_BASE,
80 .end = OMAP3430_ISP_CCP2_END,
81 .flags = IORESOURCE_MEM,
82 },
83 {
84 .start = OMAP3430_ISP_CCDC_BASE,
85 .end = OMAP3430_ISP_CCDC_END,
86 .flags = IORESOURCE_MEM,
87 },
88 {
89 .start = OMAP3430_ISP_HIST_BASE,
90 .end = OMAP3430_ISP_HIST_END,
91 .flags = IORESOURCE_MEM,
92 },
93 {
94 .start = OMAP3430_ISP_H3A_BASE,
95 .end = OMAP3430_ISP_H3A_END,
96 .flags = IORESOURCE_MEM,
97 },
98 {
99 .start = OMAP3430_ISP_PREV_BASE,
100 .end = OMAP3430_ISP_PREV_END,
101 .flags = IORESOURCE_MEM,
102 },
103 {
104 .start = OMAP3430_ISP_RESZ_BASE,
105 .end = OMAP3430_ISP_RESZ_END,
106 .flags = IORESOURCE_MEM,
107 },
108 {
109 .start = OMAP3430_ISP_SBL_BASE,
110 .end = OMAP3430_ISP_SBL_END,
111 .flags = IORESOURCE_MEM,
112 },
113 {
114 .start = OMAP3430_ISP_CSI2A_BASE,
115 .end = OMAP3430_ISP_CSI2A_END,
116 .flags = IORESOURCE_MEM,
117 },
118 {
119 .start = OMAP3430_ISP_CSI2PHY_BASE,
120 .end = OMAP3430_ISP_CSI2PHY_END,
121 .flags = IORESOURCE_MEM,
122 },
123 {
124 .start = INT_34XX_CAM_IRQ,
125 .flags = IORESOURCE_IRQ,
126 }
127};
128
129static struct platform_device omap3isp_device = {
130 .name = "omap3isp",
131 .id = -1,
132 .num_resources = ARRAY_SIZE(omap3isp_resources),
133 .resource = omap3isp_resources,
134};
135
136static inline void omap_init_camera(void)
137{
138 platform_device_register(&omap3isp_device);
139}
140#else
141static inline void omap_init_camera(void)
142{
143}
144#endif
145
59556765
SR		 146struct omap_device_pm_latency omap_keyboard_latency[] = {
147 {
148 .deactivate_func = omap_device_idle_hwmods,
149 .activate_func = omap_device_enable_hwmods,
150 .flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST,
151 },
152};
153
154int __init omap4_keyboard_init(struct omap4_keypad_platform_data
155 *sdp4430_keypad_data)
156{
157 struct omap_device *od;
158 struct omap_hwmod *oh;
159 struct omap4_keypad_platform_data *keypad_data;
160 unsigned int id = -1;
161 char *oh_name = "kbd";
162 char *name = "omap4-keypad";
163
164 oh = omap_hwmod_lookup(oh_name);
165 if (!oh) {
166 pr_err("Could not look up %s\n", oh_name);
167 return -ENODEV;
168 }
169
170 keypad_data = sdp4430_keypad_data;
171
172 od = omap_device_build(name, id, oh, keypad_data,
173 sizeof(struct omap4_keypad_platform_data),
174 omap_keyboard_latency,
175 ARRAY_SIZE(omap_keyboard_latency), 0);
176
177 if (IS_ERR(od)) {
178 WARN(1, "Cant build omap_device for %s:%s.\n",
179 name, oh->name);
180 return PTR_ERR(od);
181 }
182
183 return 0;
184}
185
6c20a683 186#if defined(CONFIG_OMAP_MBOX_FWK) || defined(CONFIG_OMAP_MBOX_FWK_MODULE)
c40fae95 187
454bf340 188#define MBOX_REG_SIZE 0x120
6c20a683 189
454bf340 190#ifdef CONFIG_ARCH_OMAP2
d10f2b6e 191static struct resource omap2_mbox_resources[] = {
c40fae95 192 {
6c20a683
HD		 193 .start = OMAP24XX_MAILBOX_BASE,
194 .end = OMAP24XX_MAILBOX_BASE + MBOX_REG_SIZE - 1,
c40fae95
TL		 195 .flags = IORESOURCE_MEM,
196 },
197 {
198 .start = INT_24XX_MAIL_U0_MPU,
199 .flags = IORESOURCE_IRQ,
1f2c4dfd 200 .name = "dsp",
c40fae95
TL		 201 },
202 {
203 .start = INT_24XX_MAIL_U3_MPU,
204 .flags = IORESOURCE_IRQ,
1f2c4dfd 205 .name = "iva",
c40fae95
TL		 206 },
207};
d10f2b6e
TL		 208static int omap2_mbox_resources_sz = ARRAY_SIZE(omap2_mbox_resources);
209#else
210#define omap2_mbox_resources NULL
211#define omap2_mbox_resources_sz 0
454bf340 212#endif
c40fae95 213
454bf340 214#ifdef CONFIG_ARCH_OMAP3
d10f2b6e 215static struct resource omap3_mbox_resources[] = {
6c20a683
HD		 216 {
217 .start = OMAP34XX_MAILBOX_BASE,
218 .end = OMAP34XX_MAILBOX_BASE + MBOX_REG_SIZE - 1,
219 .flags = IORESOURCE_MEM,
220 },
221 {
222 .start = INT_24XX_MAIL_U0_MPU,
223 .flags = IORESOURCE_IRQ,
1f2c4dfd 224 .name = "dsp",
6c20a683
HD		 225 },
226};
d10f2b6e
TL		 227static int omap3_mbox_resources_sz = ARRAY_SIZE(omap3_mbox_resources);
228#else
229#define omap3_mbox_resources NULL
230#define omap3_mbox_resources_sz 0
454bf340
S		 231#endif
232
233#ifdef CONFIG_ARCH_OMAP4
234
235#define OMAP4_MBOX_REG_SIZE 0x130
d10f2b6e 236static struct resource omap4_mbox_resources[] = {
454bf340
S		 237 {
238 .start = OMAP44XX_MAILBOX_BASE,
239 .end = OMAP44XX_MAILBOX_BASE +
240 OMAP4_MBOX_REG_SIZE - 1,
241 .flags = IORESOURCE_MEM,
242 },
243 {
5772ca7d 244 .start = OMAP44XX_IRQ_MAIL_U0,
454bf340 245 .flags = IORESOURCE_IRQ,
1f2c4dfd 246 .name = "mbox",
454bf340
S		 247 },
248};
d10f2b6e
TL		 249static int omap4_mbox_resources_sz = ARRAY_SIZE(omap4_mbox_resources);
250#else
251#define omap4_mbox_resources NULL
252#define omap4_mbox_resources_sz 0
454bf340 253#endif
6c20a683 254
c40fae95 255static struct platform_device mbox_device = {
d742709e 256 .name = "omap-mailbox",
c40fae95 257 .id = -1,
c40fae95
TL		 258};
259
260static inline void omap_init_mbox(void)
261{
d10f2b6e
TL		 262 if (cpu_is_omap24xx()) {
263 mbox_device.resource = omap2_mbox_resources;
264 mbox_device.num_resources = omap2_mbox_resources_sz;
265 } else if (cpu_is_omap34xx()) {
266 mbox_device.resource = omap3_mbox_resources;
267 mbox_device.num_resources = omap3_mbox_resources_sz;
268 } else if (cpu_is_omap44xx()) {
269 mbox_device.resource = omap4_mbox_resources;
270 mbox_device.num_resources = omap4_mbox_resources_sz;
6c20a683
HD		 271 } else {
272 pr_err("%s: platform not supported\n", __func__);
273 return;
274 }
c40fae95
TL		 275 platform_device_register(&mbox_device);
276}
277#else
278static inline void omap_init_mbox(void) { }
6c20a683 279#endif /* CONFIG_OMAP_MBOX_FWK */
c40fae95 280
9b6553cd 281static inline void omap_init_sti(void) {}
9b6553cd 282
f0fba2ad
LG		 283#if defined(CONFIG_SND_SOC) || defined(CONFIG_SND_SOC_MODULE)
284
285static struct platform_device omap_pcm = {
286 .name = "omap-pcm-audio",
287 .id = -1,
288};
289
290/*
291 * OMAP2420 has 2 McBSP ports
292 * OMAP2430 has 5 McBSP ports
293 * OMAP3 has 5 McBSP ports
294 * OMAP4 has 4 McBSP ports
295 */
296OMAP_MCBSP_PLATFORM_DEVICE(1);
297OMAP_MCBSP_PLATFORM_DEVICE(2);
298OMAP_MCBSP_PLATFORM_DEVICE(3);
299OMAP_MCBSP_PLATFORM_DEVICE(4);
300OMAP_MCBSP_PLATFORM_DEVICE(5);
301
302static void omap_init_audio(void)
303{
304 platform_device_register(&omap_mcbsp1);
305 platform_device_register(&omap_mcbsp2);
306 if (cpu_is_omap243x() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
307 platform_device_register(&omap_mcbsp3);
308 platform_device_register(&omap_mcbsp4);
309 }
310 if (cpu_is_omap243x() || cpu_is_omap34xx())
311 platform_device_register(&omap_mcbsp5);
312
313 platform_device_register(&omap_pcm);
314}
315
316#else
317static inline void omap_init_audio(void) {}
318#endif
319
646e3ed1 320#if defined(CONFIG_SPI_OMAP24XX) || defined(CONFIG_SPI_OMAP24XX_MODULE)
ed7eb9d9 321
ce491cf8 322#include <plat/mcspi.h>
ed7eb9d9 323
1a5d8190
C		 324struct omap_device_pm_latency omap_mcspi_latency[] = {
325 [0] = {
326 .deactivate_func = omap_device_idle_hwmods,
327 .activate_func = omap_device_enable_hwmods,
328 .flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST,
646e3ed1
TL		 329 },
330};
646e3ed1 331
1a5d8190 332static int omap_mcspi_init(struct omap_hwmod *oh, void *unused)
af41a12f 333{
1a5d8190
C		 334 struct omap_device *od;
335 char *name = "omap2_mcspi";
336 struct omap2_mcspi_platform_config *pdata;
337 static int spi_num;
338 struct omap2_mcspi_dev_attr *mcspi_attrib = oh->dev_attr;
339
340 pdata = kzalloc(sizeof(*pdata), GFP_KERNEL);
341 if (!pdata) {
342 pr_err("Memory allocation for McSPI device failed\n");
343 return -ENOMEM;
344 }
af41a12f 345
1a5d8190
C		 346 pdata->num_cs = mcspi_attrib->num_chipselect;
347 switch (oh->class->rev) {
348 case OMAP2_MCSPI_REV:
349 case OMAP3_MCSPI_REV:
350 pdata->regs_offset = 0;
351 break;
352 case OMAP4_MCSPI_REV:
353 pdata->regs_offset = OMAP4_MCSPI_REG_OFFSET;
354 break;
355 default:
356 pr_err("Invalid McSPI Revision value\n");
357 return -EINVAL;
358 }
af41a12f 359
1a5d8190
C		 360 spi_num++;
361 od = omap_device_build(name, spi_num, oh, pdata,
362 sizeof(*pdata), omap_mcspi_latency,
363 ARRAY_SIZE(omap_mcspi_latency), 0);
364 WARN(IS_ERR(od), "Cant build omap_device for %s:%s\n",
365 name, oh->name);
366 kfree(pdata);
367 return 0;
af41a12f 368}
af41a12f
TL		 369
370static void omap_init_mcspi(void)
371{
1a5d8190 372 omap_hwmod_for_each_by_class("mcspi", omap_mcspi_init, NULL);
ed7eb9d9
JY		 373}
374
375#else
376static inline void omap_init_mcspi(void) {}
377#endif
378
88341334
WD		 379static struct resource omap2_pmu_resource = {
380 .start = 3,
381 .end = 3,
382 .flags = IORESOURCE_IRQ,
383};
384
385static struct resource omap3_pmu_resource = {
386 .start = INT_34XX_BENCH_MPU_EMUL,
387 .end = INT_34XX_BENCH_MPU_EMUL,
388 .flags = IORESOURCE_IRQ,
389};
390
391static struct platform_device omap_pmu_device = {
392 .name = "arm-pmu",
393 .id = ARM_PMU_DEVICE_CPU,
394 .num_resources = 1,
395};
396
397static void omap_init_pmu(void)
398{
399 if (cpu_is_omap24xx())
400 omap_pmu_device.resource = &omap2_pmu_resource;
401 else if (cpu_is_omap34xx())
402 omap_pmu_device.resource = &omap3_pmu_resource;
403 else
404 return;
405
406 platform_device_register(&omap_pmu_device);
407}
408
409
ee5500c4
DK		 410#if defined(CONFIG_CRYPTO_DEV_OMAP_SHAM) || defined(CONFIG_CRYPTO_DEV_OMAP_SHAM_MODULE)
411
edc774ed 412#ifdef CONFIG_ARCH_OMAP2
ee5500c4 413static struct resource omap2_sham_resources[] = {
646e3ed1
TL		 414 {
415 .start = OMAP24XX_SEC_SHA1MD5_BASE,
416 .end = OMAP24XX_SEC_SHA1MD5_BASE + 0x64,
417 .flags = IORESOURCE_MEM,
418 },
419 {
420 .start = INT_24XX_SHA1MD5,
421 .flags = IORESOURCE_IRQ,
422 }
423};
ee5500c4
DK		 424static int omap2_sham_resources_sz = ARRAY_SIZE(omap2_sham_resources);
425#else
426#define omap2_sham_resources NULL
427#define omap2_sham_resources_sz 0
428#endif
646e3ed1 429
edc774ed 430#ifdef CONFIG_ARCH_OMAP3
ee5500c4
DK		 431static struct resource omap3_sham_resources[] = {
432 {
433 .start = OMAP34XX_SEC_SHA1MD5_BASE,
434 .end = OMAP34XX_SEC_SHA1MD5_BASE + 0x64,
435 .flags = IORESOURCE_MEM,
436 },
437 {
438 .start = INT_34XX_SHA1MD52_IRQ,
439 .flags = IORESOURCE_IRQ,
440 },
441 {
442 .start = OMAP34XX_DMA_SHA1MD5_RX,
443 .flags = IORESOURCE_DMA,
444 }
445};
446static int omap3_sham_resources_sz = ARRAY_SIZE(omap3_sham_resources);
447#else
448#define omap3_sham_resources NULL
449#define omap3_sham_resources_sz 0
450#endif
451
452static struct platform_device sham_device = {
453 .name = "omap-sham",
646e3ed1 454 .id = -1,
646e3ed1
TL		 455};
456
ee5500c4 457static void omap_init_sham(void)
646e3ed1 458{
ee5500c4
DK		 459 if (cpu_is_omap24xx()) {
460 sham_device.resource = omap2_sham_resources;
461 sham_device.num_resources = omap2_sham_resources_sz;
462 } else if (cpu_is_omap34xx()) {
463 sham_device.resource = omap3_sham_resources;
464 sham_device.num_resources = omap3_sham_resources_sz;
465 } else {
466 pr_err("%s: platform not supported\n", __func__);
467 return;
468 }
469 platform_device_register(&sham_device);
646e3ed1
TL		 470}
471#else
ee5500c4 472static inline void omap_init_sham(void) { }
646e3ed1
TL		 473#endif
474
b744c679
DK		 475#if defined(CONFIG_CRYPTO_DEV_OMAP_AES) || defined(CONFIG_CRYPTO_DEV_OMAP_AES_MODULE)
476
82a0c149 477#ifdef CONFIG_ARCH_OMAP2
b744c679
DK		 478static struct resource omap2_aes_resources[] = {
479 {
480 .start = OMAP24XX_SEC_AES_BASE,
481 .end = OMAP24XX_SEC_AES_BASE + 0x4C,
482 .flags = IORESOURCE_MEM,
483 },
484 {
485 .start = OMAP24XX_DMA_AES_TX,
486 .flags = IORESOURCE_DMA,
487 },
488 {
489 .start = OMAP24XX_DMA_AES_RX,
490 .flags = IORESOURCE_DMA,
491 }
492};
493static int omap2_aes_resources_sz = ARRAY_SIZE(omap2_aes_resources);
494#else
495#define omap2_aes_resources NULL
496#define omap2_aes_resources_sz 0
497#endif
498
82a0c149 499#ifdef CONFIG_ARCH_OMAP3
b744c679
DK		 500static struct resource omap3_aes_resources[] = {
501 {
502 .start = OMAP34XX_SEC_AES_BASE,
503 .end = OMAP34XX_SEC_AES_BASE + 0x4C,
504 .flags = IORESOURCE_MEM,
505 },
506 {
507 .start = OMAP34XX_DMA_AES2_TX,
508 .flags = IORESOURCE_DMA,
509 },
510 {
511 .start = OMAP34XX_DMA_AES2_RX,
512 .flags = IORESOURCE_DMA,
513 }
514};
515static int omap3_aes_resources_sz = ARRAY_SIZE(omap3_aes_resources);
516#else
517#define omap3_aes_resources NULL
518#define omap3_aes_resources_sz 0
519#endif
520
521static struct platform_device aes_device = {
522 .name = "omap-aes",
523 .id = -1,
524};
525
526static void omap_init_aes(void)
527{
528 if (cpu_is_omap24xx()) {
529 aes_device.resource = omap2_aes_resources;
530 aes_device.num_resources = omap2_aes_resources_sz;
531 } else if (cpu_is_omap34xx()) {
532 aes_device.resource = omap3_aes_resources;
533 aes_device.num_resources = omap3_aes_resources_sz;
534 } else {
535 pr_err("%s: platform not supported\n", __func__);
536 return;
537 }
538 platform_device_register(&aes_device);
539}
540
541#else
542static inline void omap_init_aes(void) { }
543#endif
544
d8874665
TL		 545/*-------------------------------------------------------------------------*/
546
82cf818d 547#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
917fa280
KH		 548
549#define MMCHS_SYSCONFIG 0x0010
550#define MMCHS_SYSCONFIG_SWRESET (1 << 1)
551#define MMCHS_SYSSTATUS 0x0014
552#define MMCHS_SYSSTATUS_RESETDONE (1 << 0)
553
554static struct platform_device dummy_pdev = {
555 .dev = {
556 .bus = &platform_bus_type,
557 },
558};
559
560/**
561 * omap_hsmmc_reset() - Full reset of each HS-MMC controller
562 *
563 * Ensure that each MMC controller is fully reset. Controllers
564 * left in an unknown state (by bootloader) may prevent retention
565 * or OFF-mode. This is especially important in cases where the
566 * MMC driver is not enabled, _or_ built as a module.
567 *
568 * In order for reset to work, interface, functional and debounce
569 * clocks must be enabled. The debounce clock comes from func_32k_clk
570 * and is not under SW control, so we only enable i- and f-clocks.
571 **/
572static void __init omap_hsmmc_reset(void)
573{
4323e9f7 574 u32 i, nr_controllers;
434c23a7 575 struct clk *iclk, *fclk;
4323e9f7
TL		 576
577 if (cpu_is_omap242x())
578 return;
579
580 nr_controllers = cpu_is_omap44xx() ? OMAP44XX_NR_MMC :
82cf818d 581 (cpu_is_omap34xx() ? OMAP34XX_NR_MMC : OMAP24XX_NR_MMC);
917fa280
KH		 582
583 for (i = 0; i < nr_controllers; i++) {
584 u32 v, base = 0;
917fa280
KH		 585 struct device *dev = &dummy_pdev.dev;
586
587 switch (i) {
588 case 0:
589 base = OMAP2_MMC1_BASE;
590 break;
591 case 1:
592 base = OMAP2_MMC2_BASE;
593 break;
594 case 2:
595 base = OMAP3_MMC3_BASE;
596 break;
82cf818d 597 case 3:
598 if (!cpu_is_omap44xx())
599 return;
600 base = OMAP4_MMC4_BASE;
601 break;
602 case 4:
603 if (!cpu_is_omap44xx())
604 return;
605 base = OMAP4_MMC5_BASE;
606 break;
917fa280
KH		 607 }
608
82cf818d 609 if (cpu_is_omap44xx())
610 base += OMAP4_MMC_REG_OFFSET;
611
917fa280 612 dummy_pdev.id = i;
1e98ffa8 613 dev_set_name(&dummy_pdev.dev, "mmci-omap-hs.%d", i);
6f7607cc 614 iclk = clk_get(dev, "ick");
434c23a7
AK		 615 if (IS_ERR(iclk))
616 goto err1;
617 if (clk_enable(iclk))
618 goto err2;
917fa280 619
6f7607cc 620 fclk = clk_get(dev, "fck");
434c23a7
AK		 621 if (IS_ERR(fclk))
622 goto err3;
623 if (clk_enable(fclk))
624 goto err4;
917fa280
KH		 625
626 omap_writel(MMCHS_SYSCONFIG_SWRESET, base + MMCHS_SYSCONFIG);
627 v = omap_readl(base + MMCHS_SYSSTATUS);
628 while (!(omap_readl(base + MMCHS_SYSSTATUS) &
629 MMCHS_SYSSTATUS_RESETDONE))
630 cpu_relax();
631
434c23a7
AK		 632 clk_disable(fclk);
633 clk_put(fclk);
634 clk_disable(iclk);
635 clk_put(iclk);
917fa280 636 }
434c23a7
AK		 637 return;
638
639err4:
640 clk_put(fclk);
641err3:
642 clk_disable(iclk);
643err2:
644 clk_put(iclk);
645err1:
646 printk(KERN_WARNING "%s: Unable to enable clocks for MMC%d, "
647 "cannot reset.\n", __func__, i);
917fa280
KH		 648}
649#else
650static inline void omap_hsmmc_reset(void) {}
651#endif
652
e08016d0 653#if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE)
d8874665 654
e08016d0
AG		 655static inline void omap242x_mmc_mux(struct omap_mmc_platform_data
656 *mmc_controller)
d8874665 657{
ed8303fc 658 if ((mmc_controller->slots[0].switch_pin > 0) && \
659 (mmc_controller->slots[0].switch_pin < OMAP_MAX_GPIO_LINES))
660 omap_mux_init_gpio(mmc_controller->slots[0].switch_pin,
661 OMAP_PIN_INPUT_PULLUP);
662 if ((mmc_controller->slots[0].gpio_wp > 0) && \
663 (mmc_controller->slots[0].gpio_wp < OMAP_MAX_GPIO_LINES))
664 omap_mux_init_gpio(mmc_controller->slots[0].gpio_wp,
665 OMAP_PIN_INPUT_PULLUP);
666
e08016d0
AG		 667 omap_mux_init_signal("sdmmc_cmd", 0);
668 omap_mux_init_signal("sdmmc_clki", 0);
669 omap_mux_init_signal("sdmmc_clko", 0);
670 omap_mux_init_signal("sdmmc_dat0", 0);
671 omap_mux_init_signal("sdmmc_dat_dir0", 0);
672 omap_mux_init_signal("sdmmc_cmd_dir", 0);
673 if (mmc_controller->slots[0].caps & MMC_CAP_4_BIT_DATA) {
674 omap_mux_init_signal("sdmmc_dat1", 0);
675 omap_mux_init_signal("sdmmc_dat2", 0);
676 omap_mux_init_signal("sdmmc_dat3", 0);
677 omap_mux_init_signal("sdmmc_dat_dir1", 0);
678 omap_mux_init_signal("sdmmc_dat_dir2", 0);
679 omap_mux_init_signal("sdmmc_dat_dir3", 0);
680 }
d8874665 681
e08016d0
AG		 682 /*
683 * Use internal loop-back in MMC/SDIO Module Input Clock
684 * selection
685 */
686 if (mmc_controller->slots[0].internal_clock) {
687 u32 v = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
688 v |= (1 << 24);
689 omap_ctrl_writel(v, OMAP2_CONTROL_DEVCONF0);
d8874665 690 }
e08016d0
AG		 691}
692
693void __init omap242x_init_mmc(struct omap_mmc_platform_data **mmc_data)
694{
695 char *name = "mmci-omap";
696
697 if (!mmc_data[0]) {
698 pr_err("%s fails: Incomplete platform data\n", __func__);
699 return;
700 }
701
702 omap242x_mmc_mux(mmc_data[0]);
703 omap_mmc_add(name, 0, OMAP2_MMC1_BASE, OMAP2420_MMC_SIZE,
704 INT_24XX_MMC_IRQ, mmc_data[0]);
705}
57b9daa0 706
e08016d0
AG		 707#endif
708
709#if defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE)
710
d8874665
TL		 711void __init omap2_init_mmc(struct omap_mmc_platform_data **mmc_data,
712 int nr_controllers)
713{
714 int i;
0dffb5c5 715 char *name;
d8874665
TL		 716
717 for (i = 0; i < nr_controllers; i++) {
718 unsigned long base, size;
719 unsigned int irq = 0;
720
721 if (!mmc_data[i])
722 continue;
723
d8874665
TL		 724 switch (i) {
725 case 0:
726 base = OMAP2_MMC1_BASE;
727 irq = INT_24XX_MMC_IRQ;
728 break;
729 case 1:
730 base = OMAP2_MMC2_BASE;
731 irq = INT_24XX_MMC2_IRQ;
732 break;
733 case 2:
82cf818d 734 if (!cpu_is_omap44xx() && !cpu_is_omap34xx())
d8874665
TL		 735 return;
736 base = OMAP3_MMC3_BASE;
737 irq = INT_34XX_MMC3_IRQ;
738 break;
82cf818d 739 case 3:
740 if (!cpu_is_omap44xx())
741 return;
91a0b089 742 base = OMAP4_MMC4_BASE;
5772ca7d 743 irq = OMAP44XX_IRQ_MMC4;
82cf818d 744 break;
745 case 4:
746 if (!cpu_is_omap44xx())
747 return;
91a0b089 748 base = OMAP4_MMC5_BASE;
9df76b7f 749 irq = OMAP44XX_IRQ_MMC5;
82cf818d 750 break;
d8874665
TL		 751 default:
752 continue;
753 }
754
e08016d0 755 if (cpu_is_omap44xx()) {
91a0b089 756 if (i < 3)
5772ca7d 757 irq += OMAP44XX_IRQ_GIC_START;
82cf818d 758 size = OMAP4_HSMMC_SIZE;
759 name = "mmci-omap-hs";
0dffb5c5 760 } else {
82cf818d 761 size = OMAP3_HSMMC_SIZE;
0dffb5c5
TL		 762 name = "mmci-omap-hs";
763 }
764 omap_mmc_add(name, i, base, size, irq, mmc_data[i]);
d8874665
TL		 765 };
766}
767
768#endif
769
770/*-------------------------------------------------------------------------*/
771
646e3ed1 772#if defined(CONFIG_HDQ_MASTER_OMAP) || defined(CONFIG_HDQ_MASTER_OMAP_MODULE)
59b479e0 773#if defined(CONFIG_SOC_OMAP2430) || defined(CONFIG_SOC_OMAP3430)
646e3ed1
TL		 774#define OMAP_HDQ_BASE 0x480B2000
775#endif
776static struct resource omap_hdq_resources[] = {
777 {
778 .start = OMAP_HDQ_BASE,
779 .end = OMAP_HDQ_BASE + 0x1C,
780 .flags = IORESOURCE_MEM,
781 },
782 {
783 .start = INT_24XX_HDQ_IRQ,
784 .flags = IORESOURCE_IRQ,
785 },
786};
787static struct platform_device omap_hdq_dev = {
788 .name = "omap_hdq",
789 .id = 0,
790 .dev = {
791 .platform_data = NULL,
792 },
793 .num_resources = ARRAY_SIZE(omap_hdq_resources),
794 .resource = omap_hdq_resources,
795};
796static inline void omap_hdq_init(void)
797{
798 (void) platform_device_register(&omap_hdq_dev);
799}
800#else
801static inline void omap_hdq_init(void) {}
802#endif
803
b227358d
VH		 804/*---------------------------------------------------------------------------*/
805
806#if defined(CONFIG_VIDEO_OMAP2_VOUT) || \
807 defined(CONFIG_VIDEO_OMAP2_VOUT_MODULE)
808#if defined(CONFIG_FB_OMAP2) || defined(CONFIG_FB_OMAP2_MODULE)
809static struct resource omap_vout_resource[3 - CONFIG_FB_OMAP2_NUM_FBS] = {
810};
811#else
812static struct resource omap_vout_resource[2] = {
813};
814#endif
815
816static struct platform_device omap_vout_device = {
817 .name = "omap_vout",
818 .num_resources = ARRAY_SIZE(omap_vout_resource),
819 .resource = &omap_vout_resource[0],
820 .id = -1,
821};
822static void omap_init_vout(void)
823{
824 if (platform_device_register(&omap_vout_device) < 0)
825 printk(KERN_ERR "Unable to register OMAP-VOUT device\n");
826}
827#else
828static inline void omap_init_vout(void) {}
829#endif
830
1dbae815
TL		 831/*-------------------------------------------------------------------------*/
832
833static int __init omap2_init_devices(void)
834{
81fbc5ef
PW		 835 /*
836 * please keep these calls, and their implementations above,
1dbae815
TL		 837 * in alphabetical order so they're easier to sort through.
838 */
917fa280 839 omap_hsmmc_reset();
f0fba2ad 840 omap_init_audio();
828c707e 841 omap_init_camera();
c40fae95 842 omap_init_mbox();
ed7eb9d9 843 omap_init_mcspi();
88341334 844 omap_init_pmu();
646e3ed1 845 omap_hdq_init();
9b6553cd 846 omap_init_sti();
ee5500c4 847 omap_init_sham();
b744c679 848 omap_init_aes();
b227358d 849 omap_init_vout();
1dbae815
TL		 850
851 return 0;
852}
853arch_initcall(omap2_init_devices);
f2ce6231
VC		 854
855#if defined(CONFIG_OMAP_WATCHDOG) || defined(CONFIG_OMAP_WATCHDOG_MODULE)
a9b365bd 856static struct omap_device_pm_latency omap_wdt_latency[] = {
f2ce6231
VC		 857 [0] = {
858 .deactivate_func = omap_device_idle_hwmods,
859 .activate_func = omap_device_enable_hwmods,
860 .flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST,
861 },
862};
863
864static int __init omap_init_wdt(void)
865{
866 int id = -1;
867 struct omap_device *od;
868 struct omap_hwmod *oh;
869 char *oh_name = "wd_timer2";
870 char *dev_name = "omap_wdt";
871
872 if (!cpu_class_is_omap2())
873 return 0;
874
875 oh = omap_hwmod_lookup(oh_name);
876 if (!oh) {
877 pr_err("Could not look up wd_timer%d hwmod\n", id);
878 return -EINVAL;
879 }
880
881 od = omap_device_build(dev_name, id, oh, NULL, 0,
882 omap_wdt_latency,
883 ARRAY_SIZE(omap_wdt_latency), 0);
884 WARN(IS_ERR(od), "Cant build omap_device for %s:%s.\n",
885 dev_name, oh->name);
886 return 0;
887}
888subsys_initcall(omap_init_wdt);
889#endif
Linux kernel - Deliverables
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