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1dbae815 TL |
1 | /* |
2 | * linux/arch/arm/mach-omap2/devices.c | |
3 | * | |
4 | * OMAP2 platform device setup/initialization | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License, or | |
9 | * (at your option) any later version. | |
10 | */ | |
11 | ||
1dbae815 TL |
12 | #include <linux/module.h> |
13 | #include <linux/kernel.h> | |
14 | #include <linux/init.h> | |
15 | #include <linux/platform_device.h> | |
fced80c7 | 16 | #include <linux/io.h> |
917fa280 | 17 | #include <linux/clk.h> |
1dbae815 | 18 | |
a09e64fb | 19 | #include <mach/hardware.h> |
88341334 | 20 | #include <mach/irqs.h> |
1dbae815 TL |
21 | #include <asm/mach-types.h> |
22 | #include <asm/mach/map.h> | |
88341334 | 23 | #include <asm/pmu.h> |
1dbae815 | 24 | |
ce491cf8 TL |
25 | #include <plat/control.h> |
26 | #include <plat/tc.h> | |
27 | #include <plat/board.h> | |
28 | #include <plat/mux.h> | |
a09e64fb | 29 | #include <mach/gpio.h> |
ce491cf8 | 30 | #include <plat/mmc.h> |
ee5500c4 | 31 | #include <plat/dma.h> |
1dbae815 | 32 | |
4896e394 TL |
33 | #include "mux.h" |
34 | ||
828c707e | 35 | #if defined(CONFIG_VIDEO_OMAP2) || defined(CONFIG_VIDEO_OMAP2_MODULE) |
c40fae95 | 36 | |
828c707e | 37 | static struct resource cam_resources[] = { |
c40fae95 | 38 | { |
828c707e TL |
39 | .start = OMAP24XX_CAMERA_BASE, |
40 | .end = OMAP24XX_CAMERA_BASE + 0xfff, | |
41 | .flags = IORESOURCE_MEM, | |
42 | }, | |
43 | { | |
44 | .start = INT_24XX_CAM_IRQ, | |
45 | .flags = IORESOURCE_IRQ, | |
46 | } | |
47 | }; | |
48 | ||
49 | static struct platform_device omap_cam_device = { | |
50 | .name = "omap24xxcam", | |
51 | .id = -1, | |
52 | .num_resources = ARRAY_SIZE(cam_resources), | |
53 | .resource = cam_resources, | |
54 | }; | |
55 | ||
56 | static inline void omap_init_camera(void) | |
57 | { | |
58 | platform_device_register(&omap_cam_device); | |
59 | } | |
60 | ||
61 | #elif defined(CONFIG_VIDEO_OMAP3) || defined(CONFIG_VIDEO_OMAP3_MODULE) | |
62 | ||
63 | static struct resource omap3isp_resources[] = { | |
64 | { | |
65 | .start = OMAP3430_ISP_BASE, | |
66 | .end = OMAP3430_ISP_END, | |
67 | .flags = IORESOURCE_MEM, | |
68 | }, | |
69 | { | |
70 | .start = OMAP3430_ISP_CBUFF_BASE, | |
71 | .end = OMAP3430_ISP_CBUFF_END, | |
72 | .flags = IORESOURCE_MEM, | |
73 | }, | |
74 | { | |
75 | .start = OMAP3430_ISP_CCP2_BASE, | |
76 | .end = OMAP3430_ISP_CCP2_END, | |
77 | .flags = IORESOURCE_MEM, | |
78 | }, | |
79 | { | |
80 | .start = OMAP3430_ISP_CCDC_BASE, | |
81 | .end = OMAP3430_ISP_CCDC_END, | |
82 | .flags = IORESOURCE_MEM, | |
83 | }, | |
84 | { | |
85 | .start = OMAP3430_ISP_HIST_BASE, | |
86 | .end = OMAP3430_ISP_HIST_END, | |
87 | .flags = IORESOURCE_MEM, | |
88 | }, | |
89 | { | |
90 | .start = OMAP3430_ISP_H3A_BASE, | |
91 | .end = OMAP3430_ISP_H3A_END, | |
92 | .flags = IORESOURCE_MEM, | |
93 | }, | |
94 | { | |
95 | .start = OMAP3430_ISP_PREV_BASE, | |
96 | .end = OMAP3430_ISP_PREV_END, | |
97 | .flags = IORESOURCE_MEM, | |
98 | }, | |
99 | { | |
100 | .start = OMAP3430_ISP_RESZ_BASE, | |
101 | .end = OMAP3430_ISP_RESZ_END, | |
102 | .flags = IORESOURCE_MEM, | |
103 | }, | |
104 | { | |
105 | .start = OMAP3430_ISP_SBL_BASE, | |
106 | .end = OMAP3430_ISP_SBL_END, | |
107 | .flags = IORESOURCE_MEM, | |
108 | }, | |
109 | { | |
110 | .start = OMAP3430_ISP_CSI2A_BASE, | |
111 | .end = OMAP3430_ISP_CSI2A_END, | |
112 | .flags = IORESOURCE_MEM, | |
113 | }, | |
114 | { | |
115 | .start = OMAP3430_ISP_CSI2PHY_BASE, | |
116 | .end = OMAP3430_ISP_CSI2PHY_END, | |
117 | .flags = IORESOURCE_MEM, | |
118 | }, | |
119 | { | |
120 | .start = INT_34XX_CAM_IRQ, | |
121 | .flags = IORESOURCE_IRQ, | |
122 | } | |
123 | }; | |
124 | ||
125 | static struct platform_device omap3isp_device = { | |
126 | .name = "omap3isp", | |
127 | .id = -1, | |
128 | .num_resources = ARRAY_SIZE(omap3isp_resources), | |
129 | .resource = omap3isp_resources, | |
130 | }; | |
131 | ||
132 | static inline void omap_init_camera(void) | |
133 | { | |
134 | platform_device_register(&omap3isp_device); | |
135 | } | |
136 | #else | |
137 | static inline void omap_init_camera(void) | |
138 | { | |
139 | } | |
140 | #endif | |
141 | ||
6c20a683 | 142 | #if defined(CONFIG_OMAP_MBOX_FWK) || defined(CONFIG_OMAP_MBOX_FWK_MODULE) |
c40fae95 | 143 | |
454bf340 | 144 | #define MBOX_REG_SIZE 0x120 |
6c20a683 | 145 | |
454bf340 | 146 | #ifdef CONFIG_ARCH_OMAP2 |
d10f2b6e | 147 | static struct resource omap2_mbox_resources[] = { |
c40fae95 | 148 | { |
6c20a683 HD |
149 | .start = OMAP24XX_MAILBOX_BASE, |
150 | .end = OMAP24XX_MAILBOX_BASE + MBOX_REG_SIZE - 1, | |
c40fae95 TL |
151 | .flags = IORESOURCE_MEM, |
152 | }, | |
153 | { | |
154 | .start = INT_24XX_MAIL_U0_MPU, | |
155 | .flags = IORESOURCE_IRQ, | |
156 | }, | |
157 | { | |
158 | .start = INT_24XX_MAIL_U3_MPU, | |
159 | .flags = IORESOURCE_IRQ, | |
160 | }, | |
161 | }; | |
d10f2b6e TL |
162 | static int omap2_mbox_resources_sz = ARRAY_SIZE(omap2_mbox_resources); |
163 | #else | |
164 | #define omap2_mbox_resources NULL | |
165 | #define omap2_mbox_resources_sz 0 | |
454bf340 | 166 | #endif |
c40fae95 | 167 | |
454bf340 | 168 | #ifdef CONFIG_ARCH_OMAP3 |
d10f2b6e | 169 | static struct resource omap3_mbox_resources[] = { |
6c20a683 HD |
170 | { |
171 | .start = OMAP34XX_MAILBOX_BASE, | |
172 | .end = OMAP34XX_MAILBOX_BASE + MBOX_REG_SIZE - 1, | |
173 | .flags = IORESOURCE_MEM, | |
174 | }, | |
175 | { | |
176 | .start = INT_24XX_MAIL_U0_MPU, | |
177 | .flags = IORESOURCE_IRQ, | |
178 | }, | |
179 | }; | |
d10f2b6e TL |
180 | static int omap3_mbox_resources_sz = ARRAY_SIZE(omap3_mbox_resources); |
181 | #else | |
182 | #define omap3_mbox_resources NULL | |
183 | #define omap3_mbox_resources_sz 0 | |
454bf340 S |
184 | #endif |
185 | ||
186 | #ifdef CONFIG_ARCH_OMAP4 | |
187 | ||
188 | #define OMAP4_MBOX_REG_SIZE 0x130 | |
d10f2b6e | 189 | static struct resource omap4_mbox_resources[] = { |
454bf340 S |
190 | { |
191 | .start = OMAP44XX_MAILBOX_BASE, | |
192 | .end = OMAP44XX_MAILBOX_BASE + | |
193 | OMAP4_MBOX_REG_SIZE - 1, | |
194 | .flags = IORESOURCE_MEM, | |
195 | }, | |
196 | { | |
5772ca7d | 197 | .start = OMAP44XX_IRQ_MAIL_U0, |
454bf340 S |
198 | .flags = IORESOURCE_IRQ, |
199 | }, | |
200 | }; | |
d10f2b6e TL |
201 | static int omap4_mbox_resources_sz = ARRAY_SIZE(omap4_mbox_resources); |
202 | #else | |
203 | #define omap4_mbox_resources NULL | |
204 | #define omap4_mbox_resources_sz 0 | |
454bf340 | 205 | #endif |
6c20a683 | 206 | |
c40fae95 | 207 | static struct platform_device mbox_device = { |
da8cfe03 | 208 | .name = "omap2-mailbox", |
c40fae95 | 209 | .id = -1, |
c40fae95 TL |
210 | }; |
211 | ||
212 | static inline void omap_init_mbox(void) | |
213 | { | |
d10f2b6e TL |
214 | if (cpu_is_omap24xx()) { |
215 | mbox_device.resource = omap2_mbox_resources; | |
216 | mbox_device.num_resources = omap2_mbox_resources_sz; | |
217 | } else if (cpu_is_omap34xx()) { | |
218 | mbox_device.resource = omap3_mbox_resources; | |
219 | mbox_device.num_resources = omap3_mbox_resources_sz; | |
220 | } else if (cpu_is_omap44xx()) { | |
221 | mbox_device.resource = omap4_mbox_resources; | |
222 | mbox_device.num_resources = omap4_mbox_resources_sz; | |
6c20a683 HD |
223 | } else { |
224 | pr_err("%s: platform not supported\n", __func__); | |
225 | return; | |
226 | } | |
c40fae95 TL |
227 | platform_device_register(&mbox_device); |
228 | } | |
229 | #else | |
230 | static inline void omap_init_mbox(void) { } | |
6c20a683 | 231 | #endif /* CONFIG_OMAP_MBOX_FWK */ |
c40fae95 | 232 | |
9b6553cd TL |
233 | #if defined(CONFIG_OMAP_STI) |
234 | ||
646e3ed1 TL |
235 | #if defined(CONFIG_ARCH_OMAP2) |
236 | ||
237 | #define OMAP2_STI_BASE 0x48068000 | |
9b6553cd TL |
238 | #define OMAP2_STI_CHANNEL_BASE 0x54000000 |
239 | #define OMAP2_STI_IRQ 4 | |
240 | ||
241 | static struct resource sti_resources[] = { | |
242 | { | |
243 | .start = OMAP2_STI_BASE, | |
244 | .end = OMAP2_STI_BASE + 0x7ff, | |
245 | .flags = IORESOURCE_MEM, | |
246 | }, | |
247 | { | |
248 | .start = OMAP2_STI_CHANNEL_BASE, | |
249 | .end = OMAP2_STI_CHANNEL_BASE + SZ_64K - 1, | |
250 | .flags = IORESOURCE_MEM, | |
251 | }, | |
252 | { | |
253 | .start = OMAP2_STI_IRQ, | |
254 | .flags = IORESOURCE_IRQ, | |
255 | } | |
256 | }; | |
646e3ed1 TL |
257 | #elif defined(CONFIG_ARCH_OMAP3) |
258 | ||
259 | #define OMAP3_SDTI_BASE 0x54500000 | |
260 | #define OMAP3_SDTI_CHANNEL_BASE 0x54600000 | |
261 | ||
262 | static struct resource sti_resources[] = { | |
263 | { | |
264 | .start = OMAP3_SDTI_BASE, | |
265 | .end = OMAP3_SDTI_BASE + 0xFFF, | |
266 | .flags = IORESOURCE_MEM, | |
267 | }, | |
268 | { | |
269 | .start = OMAP3_SDTI_CHANNEL_BASE, | |
270 | .end = OMAP3_SDTI_CHANNEL_BASE + SZ_1M - 1, | |
271 | .flags = IORESOURCE_MEM, | |
272 | } | |
273 | }; | |
274 | ||
275 | #endif | |
9b6553cd TL |
276 | |
277 | static struct platform_device sti_device = { | |
278 | .name = "sti", | |
279 | .id = -1, | |
9b6553cd TL |
280 | .num_resources = ARRAY_SIZE(sti_resources), |
281 | .resource = sti_resources, | |
282 | }; | |
283 | ||
284 | static inline void omap_init_sti(void) | |
285 | { | |
286 | platform_device_register(&sti_device); | |
287 | } | |
288 | #else | |
289 | static inline void omap_init_sti(void) {} | |
290 | #endif | |
291 | ||
646e3ed1 | 292 | #if defined(CONFIG_SPI_OMAP24XX) || defined(CONFIG_SPI_OMAP24XX_MODULE) |
ed7eb9d9 | 293 | |
ce491cf8 | 294 | #include <plat/mcspi.h> |
ed7eb9d9 JY |
295 | |
296 | #define OMAP2_MCSPI1_BASE 0x48098000 | |
297 | #define OMAP2_MCSPI2_BASE 0x4809a000 | |
646e3ed1 TL |
298 | #define OMAP2_MCSPI3_BASE 0x480b8000 |
299 | #define OMAP2_MCSPI4_BASE 0x480ba000 | |
ed7eb9d9 | 300 | |
7869c0b9 SR |
301 | #define OMAP4_MCSPI1_BASE 0x48098100 |
302 | #define OMAP4_MCSPI2_BASE 0x4809a100 | |
303 | #define OMAP4_MCSPI3_BASE 0x480b8100 | |
304 | #define OMAP4_MCSPI4_BASE 0x480ba100 | |
305 | ||
ed7eb9d9 | 306 | static struct omap2_mcspi_platform_config omap2_mcspi1_config = { |
ed7eb9d9 JY |
307 | .num_cs = 4, |
308 | }; | |
309 | ||
c40fae95 TL |
310 | static struct resource omap2_mcspi1_resources[] = { |
311 | { | |
312 | .start = OMAP2_MCSPI1_BASE, | |
313 | .end = OMAP2_MCSPI1_BASE + 0xff, | |
314 | .flags = IORESOURCE_MEM, | |
315 | }, | |
316 | }; | |
317 | ||
646e3ed1 | 318 | static struct platform_device omap2_mcspi1 = { |
ed7eb9d9 JY |
319 | .name = "omap2_mcspi", |
320 | .id = 1, | |
c40fae95 TL |
321 | .num_resources = ARRAY_SIZE(omap2_mcspi1_resources), |
322 | .resource = omap2_mcspi1_resources, | |
ed7eb9d9 JY |
323 | .dev = { |
324 | .platform_data = &omap2_mcspi1_config, | |
325 | }, | |
326 | }; | |
327 | ||
328 | static struct omap2_mcspi_platform_config omap2_mcspi2_config = { | |
ed7eb9d9 JY |
329 | .num_cs = 2, |
330 | }; | |
331 | ||
c40fae95 TL |
332 | static struct resource omap2_mcspi2_resources[] = { |
333 | { | |
334 | .start = OMAP2_MCSPI2_BASE, | |
335 | .end = OMAP2_MCSPI2_BASE + 0xff, | |
336 | .flags = IORESOURCE_MEM, | |
337 | }, | |
338 | }; | |
339 | ||
646e3ed1 | 340 | static struct platform_device omap2_mcspi2 = { |
ed7eb9d9 JY |
341 | .name = "omap2_mcspi", |
342 | .id = 2, | |
c40fae95 TL |
343 | .num_resources = ARRAY_SIZE(omap2_mcspi2_resources), |
344 | .resource = omap2_mcspi2_resources, | |
ed7eb9d9 JY |
345 | .dev = { |
346 | .platform_data = &omap2_mcspi2_config, | |
347 | }, | |
348 | }; | |
349 | ||
7869c0b9 SR |
350 | #if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3) || \ |
351 | defined(CONFIG_ARCH_OMAP4) | |
646e3ed1 TL |
352 | static struct omap2_mcspi_platform_config omap2_mcspi3_config = { |
353 | .num_cs = 2, | |
354 | }; | |
355 | ||
356 | static struct resource omap2_mcspi3_resources[] = { | |
357 | { | |
358 | .start = OMAP2_MCSPI3_BASE, | |
359 | .end = OMAP2_MCSPI3_BASE + 0xff, | |
360 | .flags = IORESOURCE_MEM, | |
361 | }, | |
362 | }; | |
363 | ||
364 | static struct platform_device omap2_mcspi3 = { | |
365 | .name = "omap2_mcspi", | |
366 | .id = 3, | |
367 | .num_resources = ARRAY_SIZE(omap2_mcspi3_resources), | |
368 | .resource = omap2_mcspi3_resources, | |
369 | .dev = { | |
370 | .platform_data = &omap2_mcspi3_config, | |
371 | }, | |
372 | }; | |
373 | #endif | |
374 | ||
7869c0b9 | 375 | #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4) |
646e3ed1 TL |
376 | static struct omap2_mcspi_platform_config omap2_mcspi4_config = { |
377 | .num_cs = 1, | |
378 | }; | |
379 | ||
380 | static struct resource omap2_mcspi4_resources[] = { | |
381 | { | |
382 | .start = OMAP2_MCSPI4_BASE, | |
383 | .end = OMAP2_MCSPI4_BASE + 0xff, | |
384 | .flags = IORESOURCE_MEM, | |
385 | }, | |
386 | }; | |
387 | ||
388 | static struct platform_device omap2_mcspi4 = { | |
389 | .name = "omap2_mcspi", | |
390 | .id = 4, | |
391 | .num_resources = ARRAY_SIZE(omap2_mcspi4_resources), | |
392 | .resource = omap2_mcspi4_resources, | |
393 | .dev = { | |
394 | .platform_data = &omap2_mcspi4_config, | |
395 | }, | |
396 | }; | |
397 | #endif | |
398 | ||
af41a12f TL |
399 | #ifdef CONFIG_ARCH_OMAP4 |
400 | static inline void omap4_mcspi_fixup(void) | |
ed7eb9d9 | 401 | { |
af41a12f TL |
402 | omap2_mcspi1_resources[0].start = OMAP4_MCSPI1_BASE; |
403 | omap2_mcspi1_resources[0].end = OMAP4_MCSPI1_BASE + 0xff; | |
404 | omap2_mcspi2_resources[0].start = OMAP4_MCSPI2_BASE; | |
405 | omap2_mcspi2_resources[0].end = OMAP4_MCSPI2_BASE + 0xff; | |
406 | omap2_mcspi3_resources[0].start = OMAP4_MCSPI3_BASE; | |
407 | omap2_mcspi3_resources[0].end = OMAP4_MCSPI3_BASE + 0xff; | |
408 | omap2_mcspi4_resources[0].start = OMAP4_MCSPI4_BASE; | |
409 | omap2_mcspi4_resources[0].end = OMAP4_MCSPI4_BASE + 0xff; | |
410 | } | |
411 | #else | |
412 | static inline void omap4_mcspi_fixup(void) | |
413 | { | |
414 | } | |
415 | #endif | |
416 | ||
7869c0b9 SR |
417 | #if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3) || \ |
418 | defined(CONFIG_ARCH_OMAP4) | |
af41a12f TL |
419 | static inline void omap2_mcspi3_init(void) |
420 | { | |
421 | platform_device_register(&omap2_mcspi3); | |
422 | } | |
423 | #else | |
424 | static inline void omap2_mcspi3_init(void) | |
425 | { | |
426 | } | |
646e3ed1 | 427 | #endif |
af41a12f | 428 | |
7869c0b9 | 429 | #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4) |
af41a12f TL |
430 | static inline void omap2_mcspi4_init(void) |
431 | { | |
432 | platform_device_register(&omap2_mcspi4); | |
433 | } | |
434 | #else | |
435 | static inline void omap2_mcspi4_init(void) | |
436 | { | |
437 | } | |
646e3ed1 | 438 | #endif |
af41a12f TL |
439 | |
440 | static void omap_init_mcspi(void) | |
441 | { | |
442 | if (cpu_is_omap44xx()) | |
443 | omap4_mcspi_fixup(); | |
444 | ||
445 | platform_device_register(&omap2_mcspi1); | |
446 | platform_device_register(&omap2_mcspi2); | |
447 | ||
448 | if (cpu_is_omap2430() || cpu_is_omap343x() || cpu_is_omap44xx()) | |
449 | omap2_mcspi3_init(); | |
450 | ||
451 | if (cpu_is_omap343x() || cpu_is_omap44xx()) | |
452 | omap2_mcspi4_init(); | |
ed7eb9d9 JY |
453 | } |
454 | ||
455 | #else | |
456 | static inline void omap_init_mcspi(void) {} | |
457 | #endif | |
458 | ||
88341334 WD |
459 | static struct resource omap2_pmu_resource = { |
460 | .start = 3, | |
461 | .end = 3, | |
462 | .flags = IORESOURCE_IRQ, | |
463 | }; | |
464 | ||
465 | static struct resource omap3_pmu_resource = { | |
466 | .start = INT_34XX_BENCH_MPU_EMUL, | |
467 | .end = INT_34XX_BENCH_MPU_EMUL, | |
468 | .flags = IORESOURCE_IRQ, | |
469 | }; | |
470 | ||
471 | static struct platform_device omap_pmu_device = { | |
472 | .name = "arm-pmu", | |
473 | .id = ARM_PMU_DEVICE_CPU, | |
474 | .num_resources = 1, | |
475 | }; | |
476 | ||
477 | static void omap_init_pmu(void) | |
478 | { | |
479 | if (cpu_is_omap24xx()) | |
480 | omap_pmu_device.resource = &omap2_pmu_resource; | |
481 | else if (cpu_is_omap34xx()) | |
482 | omap_pmu_device.resource = &omap3_pmu_resource; | |
483 | else | |
484 | return; | |
485 | ||
486 | platform_device_register(&omap_pmu_device); | |
487 | } | |
488 | ||
489 | ||
ee5500c4 DK |
490 | #if defined(CONFIG_CRYPTO_DEV_OMAP_SHAM) || defined(CONFIG_CRYPTO_DEV_OMAP_SHAM_MODULE) |
491 | ||
edc774ed | 492 | #ifdef CONFIG_ARCH_OMAP2 |
ee5500c4 | 493 | static struct resource omap2_sham_resources[] = { |
646e3ed1 TL |
494 | { |
495 | .start = OMAP24XX_SEC_SHA1MD5_BASE, | |
496 | .end = OMAP24XX_SEC_SHA1MD5_BASE + 0x64, | |
497 | .flags = IORESOURCE_MEM, | |
498 | }, | |
499 | { | |
500 | .start = INT_24XX_SHA1MD5, | |
501 | .flags = IORESOURCE_IRQ, | |
502 | } | |
503 | }; | |
ee5500c4 DK |
504 | static int omap2_sham_resources_sz = ARRAY_SIZE(omap2_sham_resources); |
505 | #else | |
506 | #define omap2_sham_resources NULL | |
507 | #define omap2_sham_resources_sz 0 | |
508 | #endif | |
646e3ed1 | 509 | |
edc774ed | 510 | #ifdef CONFIG_ARCH_OMAP3 |
ee5500c4 DK |
511 | static struct resource omap3_sham_resources[] = { |
512 | { | |
513 | .start = OMAP34XX_SEC_SHA1MD5_BASE, | |
514 | .end = OMAP34XX_SEC_SHA1MD5_BASE + 0x64, | |
515 | .flags = IORESOURCE_MEM, | |
516 | }, | |
517 | { | |
518 | .start = INT_34XX_SHA1MD52_IRQ, | |
519 | .flags = IORESOURCE_IRQ, | |
520 | }, | |
521 | { | |
522 | .start = OMAP34XX_DMA_SHA1MD5_RX, | |
523 | .flags = IORESOURCE_DMA, | |
524 | } | |
525 | }; | |
526 | static int omap3_sham_resources_sz = ARRAY_SIZE(omap3_sham_resources); | |
527 | #else | |
528 | #define omap3_sham_resources NULL | |
529 | #define omap3_sham_resources_sz 0 | |
530 | #endif | |
531 | ||
532 | static struct platform_device sham_device = { | |
533 | .name = "omap-sham", | |
646e3ed1 | 534 | .id = -1, |
646e3ed1 TL |
535 | }; |
536 | ||
ee5500c4 | 537 | static void omap_init_sham(void) |
646e3ed1 | 538 | { |
ee5500c4 DK |
539 | if (cpu_is_omap24xx()) { |
540 | sham_device.resource = omap2_sham_resources; | |
541 | sham_device.num_resources = omap2_sham_resources_sz; | |
542 | } else if (cpu_is_omap34xx()) { | |
543 | sham_device.resource = omap3_sham_resources; | |
544 | sham_device.num_resources = omap3_sham_resources_sz; | |
545 | } else { | |
546 | pr_err("%s: platform not supported\n", __func__); | |
547 | return; | |
548 | } | |
549 | platform_device_register(&sham_device); | |
646e3ed1 TL |
550 | } |
551 | #else | |
ee5500c4 | 552 | static inline void omap_init_sham(void) { } |
646e3ed1 TL |
553 | #endif |
554 | ||
d8874665 TL |
555 | /*-------------------------------------------------------------------------*/ |
556 | ||
82cf818d | 557 | #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4) |
917fa280 KH |
558 | |
559 | #define MMCHS_SYSCONFIG 0x0010 | |
560 | #define MMCHS_SYSCONFIG_SWRESET (1 << 1) | |
561 | #define MMCHS_SYSSTATUS 0x0014 | |
562 | #define MMCHS_SYSSTATUS_RESETDONE (1 << 0) | |
563 | ||
564 | static struct platform_device dummy_pdev = { | |
565 | .dev = { | |
566 | .bus = &platform_bus_type, | |
567 | }, | |
568 | }; | |
569 | ||
570 | /** | |
571 | * omap_hsmmc_reset() - Full reset of each HS-MMC controller | |
572 | * | |
573 | * Ensure that each MMC controller is fully reset. Controllers | |
574 | * left in an unknown state (by bootloader) may prevent retention | |
575 | * or OFF-mode. This is especially important in cases where the | |
576 | * MMC driver is not enabled, _or_ built as a module. | |
577 | * | |
578 | * In order for reset to work, interface, functional and debounce | |
579 | * clocks must be enabled. The debounce clock comes from func_32k_clk | |
580 | * and is not under SW control, so we only enable i- and f-clocks. | |
581 | **/ | |
582 | static void __init omap_hsmmc_reset(void) | |
583 | { | |
4323e9f7 TL |
584 | u32 i, nr_controllers; |
585 | ||
586 | if (cpu_is_omap242x()) | |
587 | return; | |
588 | ||
589 | nr_controllers = cpu_is_omap44xx() ? OMAP44XX_NR_MMC : | |
82cf818d | 590 | (cpu_is_omap34xx() ? OMAP34XX_NR_MMC : OMAP24XX_NR_MMC); |
917fa280 KH |
591 | |
592 | for (i = 0; i < nr_controllers; i++) { | |
593 | u32 v, base = 0; | |
594 | struct clk *iclk, *fclk; | |
595 | struct device *dev = &dummy_pdev.dev; | |
596 | ||
597 | switch (i) { | |
598 | case 0: | |
599 | base = OMAP2_MMC1_BASE; | |
600 | break; | |
601 | case 1: | |
602 | base = OMAP2_MMC2_BASE; | |
603 | break; | |
604 | case 2: | |
605 | base = OMAP3_MMC3_BASE; | |
606 | break; | |
82cf818d | 607 | case 3: |
608 | if (!cpu_is_omap44xx()) | |
609 | return; | |
610 | base = OMAP4_MMC4_BASE; | |
611 | break; | |
612 | case 4: | |
613 | if (!cpu_is_omap44xx()) | |
614 | return; | |
615 | base = OMAP4_MMC5_BASE; | |
616 | break; | |
917fa280 KH |
617 | } |
618 | ||
82cf818d | 619 | if (cpu_is_omap44xx()) |
620 | base += OMAP4_MMC_REG_OFFSET; | |
621 | ||
917fa280 | 622 | dummy_pdev.id = i; |
1e98ffa8 | 623 | dev_set_name(&dummy_pdev.dev, "mmci-omap-hs.%d", i); |
6f7607cc | 624 | iclk = clk_get(dev, "ick"); |
917fa280 KH |
625 | if (iclk && clk_enable(iclk)) |
626 | iclk = NULL; | |
627 | ||
6f7607cc | 628 | fclk = clk_get(dev, "fck"); |
917fa280 KH |
629 | if (fclk && clk_enable(fclk)) |
630 | fclk = NULL; | |
631 | ||
632 | if (!iclk || !fclk) { | |
633 | printk(KERN_WARNING | |
634 | "%s: Unable to enable clocks for MMC%d, " | |
635 | "cannot reset.\n", __func__, i); | |
636 | break; | |
637 | } | |
638 | ||
639 | omap_writel(MMCHS_SYSCONFIG_SWRESET, base + MMCHS_SYSCONFIG); | |
640 | v = omap_readl(base + MMCHS_SYSSTATUS); | |
641 | while (!(omap_readl(base + MMCHS_SYSSTATUS) & | |
642 | MMCHS_SYSSTATUS_RESETDONE)) | |
643 | cpu_relax(); | |
644 | ||
645 | if (fclk) { | |
646 | clk_disable(fclk); | |
647 | clk_put(fclk); | |
648 | } | |
649 | if (iclk) { | |
650 | clk_disable(iclk); | |
651 | clk_put(iclk); | |
652 | } | |
653 | } | |
654 | } | |
655 | #else | |
656 | static inline void omap_hsmmc_reset(void) {} | |
657 | #endif | |
658 | ||
d8874665 TL |
659 | #if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE) || \ |
660 | defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE) | |
661 | ||
662 | static inline void omap2_mmc_mux(struct omap_mmc_platform_data *mmc_controller, | |
663 | int controller_nr) | |
664 | { | |
ed8303fc | 665 | if ((mmc_controller->slots[0].switch_pin > 0) && \ |
666 | (mmc_controller->slots[0].switch_pin < OMAP_MAX_GPIO_LINES)) | |
667 | omap_mux_init_gpio(mmc_controller->slots[0].switch_pin, | |
668 | OMAP_PIN_INPUT_PULLUP); | |
669 | if ((mmc_controller->slots[0].gpio_wp > 0) && \ | |
670 | (mmc_controller->slots[0].gpio_wp < OMAP_MAX_GPIO_LINES)) | |
671 | omap_mux_init_gpio(mmc_controller->slots[0].gpio_wp, | |
672 | OMAP_PIN_INPUT_PULLUP); | |
673 | ||
d8874665 TL |
674 | if (cpu_is_omap2420() && controller_nr == 0) { |
675 | omap_cfg_reg(H18_24XX_MMC_CMD); | |
676 | omap_cfg_reg(H15_24XX_MMC_CLKI); | |
677 | omap_cfg_reg(G19_24XX_MMC_CLKO); | |
678 | omap_cfg_reg(F20_24XX_MMC_DAT0); | |
679 | omap_cfg_reg(F19_24XX_MMC_DAT_DIR0); | |
680 | omap_cfg_reg(G18_24XX_MMC_CMD_DIR); | |
90c62bf0 | 681 | if (mmc_controller->slots[0].wires == 4) { |
d8874665 TL |
682 | omap_cfg_reg(H14_24XX_MMC_DAT1); |
683 | omap_cfg_reg(E19_24XX_MMC_DAT2); | |
684 | omap_cfg_reg(D19_24XX_MMC_DAT3); | |
685 | omap_cfg_reg(E20_24XX_MMC_DAT_DIR1); | |
686 | omap_cfg_reg(F18_24XX_MMC_DAT_DIR2); | |
687 | omap_cfg_reg(E18_24XX_MMC_DAT_DIR3); | |
688 | } | |
689 | ||
690 | /* | |
691 | * Use internal loop-back in MMC/SDIO Module Input Clock | |
692 | * selection | |
693 | */ | |
694 | if (mmc_controller->slots[0].internal_clock) { | |
695 | u32 v = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0); | |
696 | v |= (1 << 24); | |
697 | omap_ctrl_writel(v, OMAP2_CONTROL_DEVCONF0); | |
698 | } | |
699 | } | |
57b9daa0 | 700 | |
4596d14a | 701 | if (cpu_is_omap34xx()) { |
57b9daa0 | 702 | if (controller_nr == 0) { |
4896e394 TL |
703 | omap_mux_init_signal("sdmmc1_clk", |
704 | OMAP_PIN_INPUT_PULLUP); | |
705 | omap_mux_init_signal("sdmmc1_cmd", | |
706 | OMAP_PIN_INPUT_PULLUP); | |
707 | omap_mux_init_signal("sdmmc1_dat0", | |
708 | OMAP_PIN_INPUT_PULLUP); | |
57b9daa0 VP |
709 | if (mmc_controller->slots[0].wires == 4 || |
710 | mmc_controller->slots[0].wires == 8) { | |
4896e394 TL |
711 | omap_mux_init_signal("sdmmc1_dat1", |
712 | OMAP_PIN_INPUT_PULLUP); | |
713 | omap_mux_init_signal("sdmmc1_dat2", | |
714 | OMAP_PIN_INPUT_PULLUP); | |
715 | omap_mux_init_signal("sdmmc1_dat3", | |
716 | OMAP_PIN_INPUT_PULLUP); | |
57b9daa0 VP |
717 | } |
718 | if (mmc_controller->slots[0].wires == 8) { | |
4896e394 TL |
719 | omap_mux_init_signal("sdmmc1_dat4", |
720 | OMAP_PIN_INPUT_PULLUP); | |
721 | omap_mux_init_signal("sdmmc1_dat5", | |
722 | OMAP_PIN_INPUT_PULLUP); | |
723 | omap_mux_init_signal("sdmmc1_dat6", | |
724 | OMAP_PIN_INPUT_PULLUP); | |
725 | omap_mux_init_signal("sdmmc1_dat7", | |
726 | OMAP_PIN_INPUT_PULLUP); | |
57b9daa0 VP |
727 | } |
728 | } | |
729 | if (controller_nr == 1) { | |
730 | /* MMC2 */ | |
4896e394 TL |
731 | omap_mux_init_signal("sdmmc2_clk", |
732 | OMAP_PIN_INPUT_PULLUP); | |
733 | omap_mux_init_signal("sdmmc2_cmd", | |
734 | OMAP_PIN_INPUT_PULLUP); | |
735 | omap_mux_init_signal("sdmmc2_dat0", | |
736 | OMAP_PIN_INPUT_PULLUP); | |
57b9daa0 VP |
737 | |
738 | /* | |
739 | * For 8 wire configurations, Lines DAT4, 5, 6 and 7 need to be muxed | |
740 | * in the board-*.c files | |
741 | */ | |
742 | if (mmc_controller->slots[0].wires == 4 || | |
743 | mmc_controller->slots[0].wires == 8) { | |
4896e394 TL |
744 | omap_mux_init_signal("sdmmc2_dat1", |
745 | OMAP_PIN_INPUT_PULLUP); | |
746 | omap_mux_init_signal("sdmmc2_dat2", | |
747 | OMAP_PIN_INPUT_PULLUP); | |
748 | omap_mux_init_signal("sdmmc2_dat3", | |
749 | OMAP_PIN_INPUT_PULLUP); | |
57b9daa0 | 750 | } |
4679232d | 751 | if (mmc_controller->slots[0].wires == 8) { |
4896e394 TL |
752 | omap_mux_init_signal("sdmmc2_dat4.sdmmc2_dat4", |
753 | OMAP_PIN_INPUT_PULLUP); | |
754 | omap_mux_init_signal("sdmmc2_dat5.sdmmc2_dat5", | |
755 | OMAP_PIN_INPUT_PULLUP); | |
756 | omap_mux_init_signal("sdmmc2_dat6.sdmmc2_dat6", | |
757 | OMAP_PIN_INPUT_PULLUP); | |
758 | omap_mux_init_signal("sdmmc2_dat7.sdmmc2_dat7", | |
759 | OMAP_PIN_INPUT_PULLUP); | |
4679232d | 760 | } |
57b9daa0 VP |
761 | } |
762 | ||
763 | /* | |
764 | * For MMC3 the pins need to be muxed in the board-*.c files | |
765 | */ | |
766 | } | |
d8874665 TL |
767 | } |
768 | ||
769 | void __init omap2_init_mmc(struct omap_mmc_platform_data **mmc_data, | |
770 | int nr_controllers) | |
771 | { | |
772 | int i; | |
0dffb5c5 | 773 | char *name; |
d8874665 TL |
774 | |
775 | for (i = 0; i < nr_controllers; i++) { | |
776 | unsigned long base, size; | |
777 | unsigned int irq = 0; | |
778 | ||
779 | if (!mmc_data[i]) | |
780 | continue; | |
781 | ||
782 | omap2_mmc_mux(mmc_data[i], i); | |
783 | ||
784 | switch (i) { | |
785 | case 0: | |
786 | base = OMAP2_MMC1_BASE; | |
787 | irq = INT_24XX_MMC_IRQ; | |
788 | break; | |
789 | case 1: | |
790 | base = OMAP2_MMC2_BASE; | |
791 | irq = INT_24XX_MMC2_IRQ; | |
792 | break; | |
793 | case 2: | |
82cf818d | 794 | if (!cpu_is_omap44xx() && !cpu_is_omap34xx()) |
d8874665 TL |
795 | return; |
796 | base = OMAP3_MMC3_BASE; | |
797 | irq = INT_34XX_MMC3_IRQ; | |
798 | break; | |
82cf818d | 799 | case 3: |
800 | if (!cpu_is_omap44xx()) | |
801 | return; | |
802 | base = OMAP4_MMC4_BASE + OMAP4_MMC_REG_OFFSET; | |
5772ca7d | 803 | irq = OMAP44XX_IRQ_MMC4; |
82cf818d | 804 | break; |
805 | case 4: | |
806 | if (!cpu_is_omap44xx()) | |
807 | return; | |
808 | base = OMAP4_MMC5_BASE + OMAP4_MMC_REG_OFFSET; | |
9df76b7f | 809 | irq = OMAP44XX_IRQ_MMC5; |
82cf818d | 810 | break; |
d8874665 TL |
811 | default: |
812 | continue; | |
813 | } | |
814 | ||
0dffb5c5 | 815 | if (cpu_is_omap2420()) { |
d8874665 | 816 | size = OMAP2420_MMC_SIZE; |
0dffb5c5 | 817 | name = "mmci-omap"; |
82cf818d | 818 | } else if (cpu_is_omap44xx()) { |
819 | if (i < 3) { | |
820 | base += OMAP4_MMC_REG_OFFSET; | |
5772ca7d | 821 | irq += OMAP44XX_IRQ_GIC_START; |
82cf818d | 822 | } |
823 | size = OMAP4_HSMMC_SIZE; | |
824 | name = "mmci-omap-hs"; | |
0dffb5c5 | 825 | } else { |
82cf818d | 826 | size = OMAP3_HSMMC_SIZE; |
0dffb5c5 TL |
827 | name = "mmci-omap-hs"; |
828 | } | |
829 | omap_mmc_add(name, i, base, size, irq, mmc_data[i]); | |
d8874665 TL |
830 | }; |
831 | } | |
832 | ||
833 | #endif | |
834 | ||
835 | /*-------------------------------------------------------------------------*/ | |
836 | ||
646e3ed1 TL |
837 | #if defined(CONFIG_HDQ_MASTER_OMAP) || defined(CONFIG_HDQ_MASTER_OMAP_MODULE) |
838 | #if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3430) | |
839 | #define OMAP_HDQ_BASE 0x480B2000 | |
840 | #endif | |
841 | static struct resource omap_hdq_resources[] = { | |
842 | { | |
843 | .start = OMAP_HDQ_BASE, | |
844 | .end = OMAP_HDQ_BASE + 0x1C, | |
845 | .flags = IORESOURCE_MEM, | |
846 | }, | |
847 | { | |
848 | .start = INT_24XX_HDQ_IRQ, | |
849 | .flags = IORESOURCE_IRQ, | |
850 | }, | |
851 | }; | |
852 | static struct platform_device omap_hdq_dev = { | |
853 | .name = "omap_hdq", | |
854 | .id = 0, | |
855 | .dev = { | |
856 | .platform_data = NULL, | |
857 | }, | |
858 | .num_resources = ARRAY_SIZE(omap_hdq_resources), | |
859 | .resource = omap_hdq_resources, | |
860 | }; | |
861 | static inline void omap_hdq_init(void) | |
862 | { | |
863 | (void) platform_device_register(&omap_hdq_dev); | |
864 | } | |
865 | #else | |
866 | static inline void omap_hdq_init(void) {} | |
867 | #endif | |
868 | ||
b227358d VH |
869 | /*---------------------------------------------------------------------------*/ |
870 | ||
871 | #if defined(CONFIG_VIDEO_OMAP2_VOUT) || \ | |
872 | defined(CONFIG_VIDEO_OMAP2_VOUT_MODULE) | |
873 | #if defined(CONFIG_FB_OMAP2) || defined(CONFIG_FB_OMAP2_MODULE) | |
874 | static struct resource omap_vout_resource[3 - CONFIG_FB_OMAP2_NUM_FBS] = { | |
875 | }; | |
876 | #else | |
877 | static struct resource omap_vout_resource[2] = { | |
878 | }; | |
879 | #endif | |
880 | ||
881 | static struct platform_device omap_vout_device = { | |
882 | .name = "omap_vout", | |
883 | .num_resources = ARRAY_SIZE(omap_vout_resource), | |
884 | .resource = &omap_vout_resource[0], | |
885 | .id = -1, | |
886 | }; | |
887 | static void omap_init_vout(void) | |
888 | { | |
889 | if (platform_device_register(&omap_vout_device) < 0) | |
890 | printk(KERN_ERR "Unable to register OMAP-VOUT device\n"); | |
891 | } | |
892 | #else | |
893 | static inline void omap_init_vout(void) {} | |
894 | #endif | |
895 | ||
1dbae815 TL |
896 | /*-------------------------------------------------------------------------*/ |
897 | ||
898 | static int __init omap2_init_devices(void) | |
899 | { | |
900 | /* please keep these calls, and their implementations above, | |
901 | * in alphabetical order so they're easier to sort through. | |
902 | */ | |
917fa280 | 903 | omap_hsmmc_reset(); |
828c707e | 904 | omap_init_camera(); |
c40fae95 | 905 | omap_init_mbox(); |
ed7eb9d9 | 906 | omap_init_mcspi(); |
88341334 | 907 | omap_init_pmu(); |
646e3ed1 | 908 | omap_hdq_init(); |
9b6553cd | 909 | omap_init_sti(); |
ee5500c4 | 910 | omap_init_sham(); |
b227358d | 911 | omap_init_vout(); |
1dbae815 TL |
912 | |
913 | return 0; | |
914 | } | |
915 | arch_initcall(omap2_init_devices); |