[deliverable/linux.git] / arch / arm / mach-omap2 / display.c

/*
 * OMAP2plus display device setup / initialization.
 *
 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
 *	Senthilvadivu Guruswamy
 *	Sumit Semwal
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
 * kind, whether express or implied; without even the implied warranty
 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <linux/string.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/io.h>
#include <linux/clk.h>
#include <linux/err.h>
#include <linux/delay.h>

#include <video/omapdss.h>
#include "omap_hwmod.h"
#include "omap_device.h"
#include "omap-pm.h"
#include "common.h"

#include "soc.h"
#include "iomap.h"
#include "mux.h"
#include "control.h"
#include "display.h"
#include "prm.h"

#define DISPC_CONTROL		0x0040
#define DISPC_CONTROL2		0x0238
#define DISPC_CONTROL3		0x0848
#define DISPC_IRQSTATUS		0x0018

#define DSS_SYSCONFIG		0x10
#define DSS_SYSSTATUS		0x14
#define DSS_CONTROL		0x40
#define DSS_SDI_CONTROL		0x44
#define DSS_PLL_CONTROL		0x48

#define LCD_EN_MASK		(0x1 << 0)
#define DIGIT_EN_MASK		(0x1 << 1)

#define FRAMEDONE_IRQ_SHIFT	0
#define EVSYNC_EVEN_IRQ_SHIFT	2
#define EVSYNC_ODD_IRQ_SHIFT	3
#define FRAMEDONE2_IRQ_SHIFT	22
#define FRAMEDONE3_IRQ_SHIFT	30
#define FRAMEDONETV_IRQ_SHIFT	24

/*
 * FRAMEDONE_IRQ_TIMEOUT: how long (in milliseconds) to wait during DISPC
 *     reset before deciding that something has gone wrong
 */
#define FRAMEDONE_IRQ_TIMEOUT		100

static struct platform_device omap_display_device = {
	.name          = "omapdss",
	.id            = -1,
	.dev            = {
		.platform_data = NULL,
	},
};

struct omap_dss_hwmod_data {
	const char *oh_name;
	const char *dev_name;
	const int id;
};

static const struct omap_dss_hwmod_data omap2_dss_hwmod_data[] __initconst = {
	{ "dss_core", "omapdss_dss", -1 },
	{ "dss_dispc", "omapdss_dispc", -1 },
	{ "dss_rfbi", "omapdss_rfbi", -1 },
	{ "dss_venc", "omapdss_venc", -1 },
};

static const struct omap_dss_hwmod_data omap3_dss_hwmod_data[] __initconst = {
	{ "dss_core", "omapdss_dss", -1 },
	{ "dss_dispc", "omapdss_dispc", -1 },
	{ "dss_rfbi", "omapdss_rfbi", -1 },
	{ "dss_venc", "omapdss_venc", -1 },
	{ "dss_dsi1", "omapdss_dsi", 0 },
};

static const struct omap_dss_hwmod_data omap4_dss_hwmod_data[] __initconst = {
	{ "dss_core", "omapdss_dss", -1 },
	{ "dss_dispc", "omapdss_dispc", -1 },
	{ "dss_rfbi", "omapdss_rfbi", -1 },
	{ "dss_dsi1", "omapdss_dsi", 0 },
	{ "dss_dsi2", "omapdss_dsi", 1 },
	{ "dss_hdmi", "omapdss_hdmi", -1 },
};

static void __init omap4_hdmi_mux_pads(enum omap_hdmi_flags flags)
{
	u32 reg;
	u16 control_i2c_1;

	omap_mux_init_signal("hdmi_cec",
			OMAP_PIN_INPUT_PULLUP);
	omap_mux_init_signal("hdmi_ddc_scl",
			OMAP_PIN_INPUT_PULLUP);
	omap_mux_init_signal("hdmi_ddc_sda",
			OMAP_PIN_INPUT_PULLUP);

	/*
	 * CONTROL_I2C_1: HDMI_DDC_SDA_PULLUPRESX (bit 28) and
	 * HDMI_DDC_SCL_PULLUPRESX (bit 24) are set to disable
	 * internal pull up resistor.
	 */
	if (flags & OMAP_HDMI_SDA_SCL_EXTERNAL_PULLUP) {
		control_i2c_1 = OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_I2C_1;
		reg = omap4_ctrl_pad_readl(control_i2c_1);
		reg |= (OMAP4_HDMI_DDC_SDA_PULLUPRESX_MASK |
			OMAP4_HDMI_DDC_SCL_PULLUPRESX_MASK);
			omap4_ctrl_pad_writel(reg, control_i2c_1);
	}
}

static int omap4_dsi_mux_pads(int dsi_id, unsigned lanes)
{
	u32 enable_mask, enable_shift;
	u32 pipd_mask, pipd_shift;
	u32 reg;

	if (dsi_id == 0) {
		enable_mask = OMAP4_DSI1_LANEENABLE_MASK;
		enable_shift = OMAP4_DSI1_LANEENABLE_SHIFT;
		pipd_mask = OMAP4_DSI1_PIPD_MASK;
		pipd_shift = OMAP4_DSI1_PIPD_SHIFT;
	} else if (dsi_id == 1) {
		enable_mask = OMAP4_DSI2_LANEENABLE_MASK;
		enable_shift = OMAP4_DSI2_LANEENABLE_SHIFT;
		pipd_mask = OMAP4_DSI2_PIPD_MASK;
		pipd_shift = OMAP4_DSI2_PIPD_SHIFT;
	} else {
		return -ENODEV;
	}

	reg = omap4_ctrl_pad_readl(OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_DSIPHY);

	reg &= ~enable_mask;
	reg &= ~pipd_mask;

	reg |= (lanes << enable_shift) & enable_mask;
	reg |= (lanes << pipd_shift) & pipd_mask;

	omap4_ctrl_pad_writel(reg, OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_DSIPHY);

	return 0;
}

int __init omap_hdmi_init(enum omap_hdmi_flags flags)
{
	if (cpu_is_omap44xx())
		omap4_hdmi_mux_pads(flags);

	return 0;
}

static int omap_dsi_enable_pads(int dsi_id, unsigned lane_mask)
{
	if (cpu_is_omap44xx())
		return omap4_dsi_mux_pads(dsi_id, lane_mask);

	return 0;
}

static void omap_dsi_disable_pads(int dsi_id, unsigned lane_mask)
{
	if (cpu_is_omap44xx())
		omap4_dsi_mux_pads(dsi_id, 0);
}

static int omap_dss_set_min_bus_tput(struct device *dev, unsigned long tput)
{
	return omap_pm_set_min_bus_tput(dev, OCP_INITIATOR_AGENT, tput);
}

static struct platform_device *create_dss_pdev(const char *pdev_name,
		int pdev_id, const char *oh_name, void *pdata, int pdata_len,
		struct platform_device *parent)
{
	struct platform_device *pdev;
	struct omap_device *od;
	struct omap_hwmod *ohs[1];
	struct omap_hwmod *oh;
	int r;

	oh = omap_hwmod_lookup(oh_name);
	if (!oh) {
		pr_err("Could not look up %s\n", oh_name);
		r = -ENODEV;
		goto err;
	}

	pdev = platform_device_alloc(pdev_name, pdev_id);
	if (!pdev) {
		pr_err("Could not create pdev for %s\n", pdev_name);
		r = -ENOMEM;
		goto err;
	}

	if (parent != NULL)
		pdev->dev.parent = &parent->dev;

	if (pdev->id != -1)
		dev_set_name(&pdev->dev, "%s.%d", pdev->name, pdev->id);
	else
		dev_set_name(&pdev->dev, "%s", pdev->name);

	ohs[0] = oh;
	od = omap_device_alloc(pdev, ohs, 1, NULL, 0);
	if (IS_ERR(od)) {
		pr_err("Could not alloc omap_device for %s\n", pdev_name);
		r = -ENOMEM;
		goto err;
	}

	r = platform_device_add_data(pdev, pdata, pdata_len);
	if (r) {
		pr_err("Could not set pdata for %s\n", pdev_name);
		goto err;
	}

	r = omap_device_register(pdev);
	if (r) {
		pr_err("Could not register omap_device for %s\n", pdev_name);
		goto err;
	}

	return pdev;

err:
	return ERR_PTR(r);
}

static struct platform_device *create_simple_dss_pdev(const char *pdev_name,
		int pdev_id, void *pdata, int pdata_len,
		struct platform_device *parent)
{
	struct platform_device *pdev;
	int r;

	pdev = platform_device_alloc(pdev_name, pdev_id);
	if (!pdev) {
		pr_err("Could not create pdev for %s\n", pdev_name);
		r = -ENOMEM;
		goto err;
	}

	if (parent != NULL)
		pdev->dev.parent = &parent->dev;

	if (pdev->id != -1)
		dev_set_name(&pdev->dev, "%s.%d", pdev->name, pdev->id);
	else
		dev_set_name(&pdev->dev, "%s", pdev->name);

	r = platform_device_add_data(pdev, pdata, pdata_len);
	if (r) {
		pr_err("Could not set pdata for %s\n", pdev_name);
		goto err;
	}

	r = platform_device_add(pdev);
	if (r) {
		pr_err("Could not register platform_device for %s\n", pdev_name);
		goto err;
	}

	return pdev;

err:
	return ERR_PTR(r);
}

static enum omapdss_version __init omap_display_get_version(void)
{
	if (cpu_is_omap24xx())
		return OMAPDSS_VER_OMAP24xx;
	else if (cpu_is_omap3630())
		return OMAPDSS_VER_OMAP3630;
	else if (cpu_is_omap34xx()) {
		if (soc_is_am35xx()) {
			return OMAPDSS_VER_AM35xx;
		} else {
			if (omap_rev() < OMAP3430_REV_ES3_0)
				return OMAPDSS_VER_OMAP34xx_ES1;
			else
				return OMAPDSS_VER_OMAP34xx_ES3;
		}
	} else if (omap_rev() == OMAP4430_REV_ES1_0)
		return OMAPDSS_VER_OMAP4430_ES1;
	else if (omap_rev() == OMAP4430_REV_ES2_0 ||
			omap_rev() == OMAP4430_REV_ES2_1 ||
			omap_rev() == OMAP4430_REV_ES2_2)
		return OMAPDSS_VER_OMAP4430_ES2;
	else if (cpu_is_omap44xx())
		return OMAPDSS_VER_OMAP4;
	else if (soc_is_omap54xx())
		return OMAPDSS_VER_OMAP5;
	else
		return OMAPDSS_VER_UNKNOWN;
}

int __init omap_display_init(struct omap_dss_board_info *board_data)
{
	int r = 0;
	struct platform_device *pdev;
	int i, oh_count;
	const struct omap_dss_hwmod_data *curr_dss_hwmod;
	struct platform_device *dss_pdev;
	enum omapdss_version ver;

	/* create omapdss device */

	ver = omap_display_get_version();

	if (ver == OMAPDSS_VER_UNKNOWN) {
		pr_err("DSS not supported on this SoC\n");
		return -ENODEV;
	}

	board_data->version = ver;
	board_data->dsi_enable_pads = omap_dsi_enable_pads;
	board_data->dsi_disable_pads = omap_dsi_disable_pads;
	board_data->get_context_loss_count = omap_pm_get_dev_context_loss_count;
	board_data->set_min_bus_tput = omap_dss_set_min_bus_tput;

	omap_display_device.dev.platform_data = board_data;

	r = platform_device_register(&omap_display_device);
	if (r < 0) {
		pr_err("Unable to register omapdss device\n");
		return r;
	}

	/* create devices for dss hwmods */

	if (cpu_is_omap24xx()) {
		curr_dss_hwmod = omap2_dss_hwmod_data;
		oh_count = ARRAY_SIZE(omap2_dss_hwmod_data);
	} else if (cpu_is_omap34xx()) {
		curr_dss_hwmod = omap3_dss_hwmod_data;
		oh_count = ARRAY_SIZE(omap3_dss_hwmod_data);
	} else {
		curr_dss_hwmod = omap4_dss_hwmod_data;
		oh_count = ARRAY_SIZE(omap4_dss_hwmod_data);
	}

	/*
	 * First create the pdev for dss_core, which is used as a parent device
	 * by the other dss pdevs. Note: dss_core has to be the first item in
	 * the hwmod list.
	 */
	dss_pdev = create_dss_pdev(curr_dss_hwmod[0].dev_name,
			curr_dss_hwmod[0].id,
			curr_dss_hwmod[0].oh_name,
			board_data, sizeof(*board_data),
			NULL);

	if (IS_ERR(dss_pdev)) {
		pr_err("Could not build omap_device for %s\n",
				curr_dss_hwmod[0].oh_name);

		return PTR_ERR(dss_pdev);
	}

	for (i = 1; i < oh_count; i++) {
		pdev = create_dss_pdev(curr_dss_hwmod[i].dev_name,
				curr_dss_hwmod[i].id,
				curr_dss_hwmod[i].oh_name,
				board_data, sizeof(*board_data),
				dss_pdev);

		if (IS_ERR(pdev)) {
			pr_err("Could not build omap_device for %s\n",
					curr_dss_hwmod[i].oh_name);

			return PTR_ERR(pdev);
		}
	}

	/* Create devices for DPI and SDI */

	pdev = create_simple_dss_pdev("omapdss_dpi", -1,
			board_data, sizeof(*board_data), dss_pdev);
	if (IS_ERR(pdev)) {
		pr_err("Could not build platform_device for omapdss_dpi\n");
		return PTR_ERR(pdev);
	}

	if (cpu_is_omap34xx()) {
		pdev = create_simple_dss_pdev("omapdss_sdi", -1,
				board_data, sizeof(*board_data), dss_pdev);
		if (IS_ERR(pdev)) {
			pr_err("Could not build platform_device for omapdss_sdi\n");
			return PTR_ERR(pdev);
		}
	}

	return 0;
}

static void dispc_disable_outputs(void)
{
	u32 v, irq_mask = 0;
	bool lcd_en, digit_en, lcd2_en = false, lcd3_en = false;
	int i;
	struct omap_dss_dispc_dev_attr *da;
	struct omap_hwmod *oh;

	oh = omap_hwmod_lookup("dss_dispc");
	if (!oh) {
		WARN(1, "display: could not disable outputs during reset - could not find dss_dispc hwmod\n");
		return;
	}

	if (!oh->dev_attr) {
		pr_err("display: could not disable outputs during reset due to missing dev_attr\n");
		return;
	}

	da = (struct omap_dss_dispc_dev_attr *)oh->dev_attr;

	/* store value of LCDENABLE and DIGITENABLE bits */
	v = omap_hwmod_read(oh, DISPC_CONTROL);
	lcd_en = v & LCD_EN_MASK;
	digit_en = v & DIGIT_EN_MASK;

	/* store value of LCDENABLE for LCD2 */
	if (da->manager_count > 2) {
		v = omap_hwmod_read(oh, DISPC_CONTROL2);
		lcd2_en = v & LCD_EN_MASK;
	}

	/* store value of LCDENABLE for LCD3 */
	if (da->manager_count > 3) {
		v = omap_hwmod_read(oh, DISPC_CONTROL3);
		lcd3_en = v & LCD_EN_MASK;
	}

	if (!(lcd_en | digit_en | lcd2_en | lcd3_en))
		return; /* no managers currently enabled */

	/*
	 * If any manager was enabled, we need to disable it before
	 * DSS clocks are disabled or DISPC module is reset
	 */
	if (lcd_en)
		irq_mask |= 1 << FRAMEDONE_IRQ_SHIFT;

	if (digit_en) {
		if (da->has_framedonetv_irq) {
			irq_mask |= 1 << FRAMEDONETV_IRQ_SHIFT;
		} else {
			irq_mask |= 1 << EVSYNC_EVEN_IRQ_SHIFT |
				1 << EVSYNC_ODD_IRQ_SHIFT;
		}
	}

	if (lcd2_en)
		irq_mask |= 1 << FRAMEDONE2_IRQ_SHIFT;
	if (lcd3_en)
		irq_mask |= 1 << FRAMEDONE3_IRQ_SHIFT;

	/*
	 * clear any previous FRAMEDONE, FRAMEDONETV,
	 * EVSYNC_EVEN/ODD, FRAMEDONE2 or FRAMEDONE3 interrupts
	 */
	omap_hwmod_write(irq_mask, oh, DISPC_IRQSTATUS);

	/* disable LCD and TV managers */
	v = omap_hwmod_read(oh, DISPC_CONTROL);
	v &= ~(LCD_EN_MASK | DIGIT_EN_MASK);
	omap_hwmod_write(v, oh, DISPC_CONTROL);

	/* disable LCD2 manager */
	if (da->manager_count > 2) {
		v = omap_hwmod_read(oh, DISPC_CONTROL2);
		v &= ~LCD_EN_MASK;
		omap_hwmod_write(v, oh, DISPC_CONTROL2);
	}

	/* disable LCD3 manager */
	if (da->manager_count > 3) {
		v = omap_hwmod_read(oh, DISPC_CONTROL3);
		v &= ~LCD_EN_MASK;
		omap_hwmod_write(v, oh, DISPC_CONTROL3);
	}

	i = 0;
	while ((omap_hwmod_read(oh, DISPC_IRQSTATUS) & irq_mask) !=
	       irq_mask) {
		i++;
		if (i > FRAMEDONE_IRQ_TIMEOUT) {
			pr_err("didn't get FRAMEDONE1/2/3 or TV interrupt\n");
			break;
		}
		mdelay(1);
	}
}

int omap_dss_reset(struct omap_hwmod *oh)
{
	struct omap_hwmod_opt_clk *oc;
	int c = 0;
	int i, r;

	if (!(oh->class->sysc->sysc_flags & SYSS_HAS_RESET_STATUS)) {
		pr_err("dss_core: hwmod data doesn't contain reset data\n");
		return -EINVAL;
	}

	for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++)
		if (oc->_clk)
			clk_prepare_enable(oc->_clk);

	dispc_disable_outputs();

	/* clear SDI registers */
	if (cpu_is_omap3430()) {
		omap_hwmod_write(0x0, oh, DSS_SDI_CONTROL);
		omap_hwmod_write(0x0, oh, DSS_PLL_CONTROL);
	}

	/*
	 * clear DSS_CONTROL register to switch DSS clock sources to
	 * PRCM clock, if any
	 */
	omap_hwmod_write(0x0, oh, DSS_CONTROL);

	omap_test_timeout((omap_hwmod_read(oh, oh->class->sysc->syss_offs)
				& SYSS_RESETDONE_MASK),
			MAX_MODULE_SOFTRESET_WAIT, c);

	if (c == MAX_MODULE_SOFTRESET_WAIT)
		pr_warning("dss_core: waiting for reset to finish failed\n");
	else
		pr_debug("dss_core: softreset done\n");

	for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++)
		if (oc->_clk)
			clk_disable_unprepare(oc->_clk);

	r = (c == MAX_MODULE_SOFTRESET_WAIT) ? -ETIMEDOUT : 0;

	return r;
}
Commit	Line	Data
b7ee79ab SS	1	/*
	2	* OMAP2plus display device setup / initialization.
	3	*
	4	* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
	5	* Senthilvadivu Guruswamy
	6	* Sumit Semwal
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License version 2 as
	10	* published by the Free Software Foundation.
	11	*
	12	* This program is distributed "as is" WITHOUT ANY WARRANTY of any
	13	* kind, whether express or implied; without even the implied warranty
	14	* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*/
	17
d44b28c4	18	#include <linux/string.h>
b7ee79ab SS	19	#include <linux/kernel.h>
	20	#include <linux/init.h>
	21	#include <linux/platform_device.h>
	22	#include <linux/io.h>
	23	#include <linux/clk.h>
	24	#include <linux/err.h>
deee6d53	25	#include <linux/delay.h>
b7ee79ab	26
a0b38cc4	27	#include <video/omapdss.h>
2a296c8f	28	#include "omap_hwmod.h"
25c7d49e	29	#include "omap_device.h"
1d5aef49	30	#include "omap-pm.h"
deee6d53	31	#include "common.h"
b7ee79ab	32
e4c060db	33	#include "soc.h"
ee0839c2	34	#include "iomap.h"
ee9dfd82	35	#include "mux.h"
dc35835c	36	#include "control.h"
b923d40d	37	#include "display.h"
b13159af	38	#include "prm.h"
b923d40d AT	39
	40	#define DISPC_CONTROL 0x0040
	41	#define DISPC_CONTROL2 0x0238
465698ee	42	#define DISPC_CONTROL3 0x0848
b923d40d AT	43	#define DISPC_IRQSTATUS 0x0018
	44
	45	#define DSS_SYSCONFIG 0x10
	46	#define DSS_SYSSTATUS 0x14
	47	#define DSS_CONTROL 0x40
	48	#define DSS_SDI_CONTROL 0x44
	49	#define DSS_PLL_CONTROL 0x48
	50
	51	#define LCD_EN_MASK (0x1 << 0)
	52	#define DIGIT_EN_MASK (0x1 << 1)
	53
	54	#define FRAMEDONE_IRQ_SHIFT 0
	55	#define EVSYNC_EVEN_IRQ_SHIFT 2
	56	#define EVSYNC_ODD_IRQ_SHIFT 3
	57	#define FRAMEDONE2_IRQ_SHIFT 22
465698ee	58	#define FRAMEDONE3_IRQ_SHIFT 30
b923d40d AT	59	#define FRAMEDONETV_IRQ_SHIFT 24
	60
	61	/*
	62	* FRAMEDONE_IRQ_TIMEOUT: how long (in milliseconds) to wait during DISPC
	63	* reset before deciding that something has gone wrong
	64	*/
	65	#define FRAMEDONE_IRQ_TIMEOUT 100
dc35835c	66
b7ee79ab SS	67	static struct platform_device omap_display_device = {
	68	.name = "omapdss",
	69	.id = -1,
	70	.dev = {
	71	.platform_data = NULL,
	72	},
	73	};
	74
179e0453 AT	75	struct omap_dss_hwmod_data {
	76	const char *oh_name;
	77	const char *dev_name;
	78	const int id;
	79	};
	80
bcad6dc3	81	static const struct omap_dss_hwmod_data omap2_dss_hwmod_data[] __initconst = {
179e0453 AT	82	{ "dss_core", "omapdss_dss", -1 },
	83	{ "dss_dispc", "omapdss_dispc", -1 },
	84	{ "dss_rfbi", "omapdss_rfbi", -1 },
	85	{ "dss_venc", "omapdss_venc", -1 },
	86	};
	87
bcad6dc3	88	static const struct omap_dss_hwmod_data omap3_dss_hwmod_data[] __initconst = {
179e0453 AT	89	{ "dss_core", "omapdss_dss", -1 },
	90	{ "dss_dispc", "omapdss_dispc", -1 },
	91	{ "dss_rfbi", "omapdss_rfbi", -1 },
	92	{ "dss_venc", "omapdss_venc", -1 },
7c68dd96	93	{ "dss_dsi1", "omapdss_dsi", 0 },
179e0453 AT	94	};
179e0453 AT	95
bcad6dc3	96	static const struct omap_dss_hwmod_data omap4_dss_hwmod_data[] __initconst = {
179e0453 AT	97	{ "dss_core", "omapdss_dss", -1 },
	98	{ "dss_dispc", "omapdss_dispc", -1 },
	99	{ "dss_rfbi", "omapdss_rfbi", -1 },
7c68dd96 TV	100	{ "dss_dsi1", "omapdss_dsi", 0 },
7c68dd96 TV	101	{ "dss_dsi2", "omapdss_dsi", 1 },
179e0453 AT	102	{ "dss_hdmi", "omapdss_hdmi", -1 },
	103	};
	104
e8a30b25	105	static void __init omap4_hdmi_mux_pads(enum omap_hdmi_flags flags)
ee9dfd82	106	{
9a901683 M	107	u32 reg;
	108	u16 control_i2c_1;
	109
ee9dfd82 M	110	omap_mux_init_signal("hdmi_cec",
ee9dfd82 M	111	OMAP_PIN_INPUT_PULLUP);
ee9dfd82 M	112	omap_mux_init_signal("hdmi_ddc_scl",
	113	OMAP_PIN_INPUT_PULLUP);
	114	omap_mux_init_signal("hdmi_ddc_sda",
	115	OMAP_PIN_INPUT_PULLUP);
9a901683 M	116
	117	/*
	118	* CONTROL_I2C_1: HDMI_DDC_SDA_PULLUPRESX (bit 28) and
	119	* HDMI_DDC_SCL_PULLUPRESX (bit 24) are set to disable
	120	* internal pull up resistor.
	121	*/
	122	if (flags & OMAP_HDMI_SDA_SCL_EXTERNAL_PULLUP) {
	123	control_i2c_1 = OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_I2C_1;
	124	reg = omap4_ctrl_pad_readl(control_i2c_1);
	125	reg \|= (OMAP4_HDMI_DDC_SDA_PULLUPRESX_MASK \|
	126	OMAP4_HDMI_DDC_SCL_PULLUPRESX_MASK);
	127	omap4_ctrl_pad_writel(reg, control_i2c_1);
	128	}
ee9dfd82 M	129	}
ee9dfd82 M	130
e8a30b25	131	static int omap4_dsi_mux_pads(int dsi_id, unsigned lanes)
dc35835c TV	132	{
	133	u32 enable_mask, enable_shift;
	134	u32 pipd_mask, pipd_shift;
	135	u32 reg;
	136
	137	if (dsi_id == 0) {
	138	enable_mask = OMAP4_DSI1_LANEENABLE_MASK;
	139	enable_shift = OMAP4_DSI1_LANEENABLE_SHIFT;
	140	pipd_mask = OMAP4_DSI1_PIPD_MASK;
	141	pipd_shift = OMAP4_DSI1_PIPD_SHIFT;
	142	} else if (dsi_id == 1) {
	143	enable_mask = OMAP4_DSI2_LANEENABLE_MASK;
	144	enable_shift = OMAP4_DSI2_LANEENABLE_SHIFT;
	145	pipd_mask = OMAP4_DSI2_PIPD_MASK;
	146	pipd_shift = OMAP4_DSI2_PIPD_SHIFT;
	147	} else {
	148	return -ENODEV;
	149	}
	150
	151	reg = omap4_ctrl_pad_readl(OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_DSIPHY);
	152
	153	reg &= ~enable_mask;
	154	reg &= ~pipd_mask;
	155
	156	reg \|= (lanes << enable_shift) & enable_mask;
	157	reg \|= (lanes << pipd_shift) & pipd_mask;
	158
	159	omap4_ctrl_pad_writel(reg, OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_DSIPHY);
	160
	161	return 0;
	162	}
	163
d1589f09	164	int __init omap_hdmi_init(enum omap_hdmi_flags flags)
ee9dfd82 M	165	{
ee9dfd82 M	166	if (cpu_is_omap44xx())
9a901683	167	omap4_hdmi_mux_pads(flags);
ee9dfd82 M	168
	169	return 0;
	170	}
	171
e8a30b25	172	static int omap_dsi_enable_pads(int dsi_id, unsigned lane_mask)
5bc416cb	173	{
dc35835c TV	174	if (cpu_is_omap44xx())
	175	return omap4_dsi_mux_pads(dsi_id, lane_mask);
	176
5bc416cb TV	177	return 0;
	178	}
	179
e8a30b25	180	static void omap_dsi_disable_pads(int dsi_id, unsigned lane_mask)
5bc416cb	181	{
dc35835c TV	182	if (cpu_is_omap44xx())
dc35835c TV	183	omap4_dsi_mux_pads(dsi_id, 0);
5bc416cb TV	184	}
5bc416cb TV	185
62c1dcfc TV	186	static int omap_dss_set_min_bus_tput(struct device *dev, unsigned long tput)
	187	{
	188	return omap_pm_set_min_bus_tput(dev, OCP_INITIATOR_AGENT, tput);
	189	}
	190
966eaed0 TV	191	static struct platform_device create_dss_pdev(const char pdev_name,
	192	int pdev_id, const char oh_name, void pdata, int pdata_len,
	193	struct platform_device *parent)
	194	{
	195	struct platform_device *pdev;
	196	struct omap_device *od;
	197	struct omap_hwmod *ohs[1];
	198	struct omap_hwmod *oh;
	199	int r;
	200
	201	oh = omap_hwmod_lookup(oh_name);
	202	if (!oh) {
	203	pr_err("Could not look up %s\n", oh_name);
	204	r = -ENODEV;
	205	goto err;
	206	}
	207
	208	pdev = platform_device_alloc(pdev_name, pdev_id);
	209	if (!pdev) {
	210	pr_err("Could not create pdev for %s\n", pdev_name);
	211	r = -ENOMEM;
	212	goto err;
	213	}
	214
	215	if (parent != NULL)
	216	pdev->dev.parent = &parent->dev;
	217
	218	if (pdev->id != -1)
	219	dev_set_name(&pdev->dev, "%s.%d", pdev->name, pdev->id);
	220	else
	221	dev_set_name(&pdev->dev, "%s", pdev->name);
	222
	223	ohs[0] = oh;
	224	od = omap_device_alloc(pdev, ohs, 1, NULL, 0);
9ee67723	225	if (IS_ERR(od)) {
966eaed0 TV	226	pr_err("Could not alloc omap_device for %s\n", pdev_name);
	227	r = -ENOMEM;
	228	goto err;
	229	}
	230
	231	r = platform_device_add_data(pdev, pdata, pdata_len);
	232	if (r) {
	233	pr_err("Could not set pdata for %s\n", pdev_name);
	234	goto err;
	235	}
	236
	237	r = omap_device_register(pdev);
	238	if (r) {
	239	pr_err("Could not register omap_device for %s\n", pdev_name);
	240	goto err;
	241	}
	242
	243	return pdev;
	244
	245	err:
	246	return ERR_PTR(r);
	247	}
	248
53f576a8 TV	249	static struct platform_device create_simple_dss_pdev(const char pdev_name,
	250	int pdev_id, void *pdata, int pdata_len,
	251	struct platform_device *parent)
	252	{
	253	struct platform_device *pdev;
	254	int r;
	255
	256	pdev = platform_device_alloc(pdev_name, pdev_id);
	257	if (!pdev) {
	258	pr_err("Could not create pdev for %s\n", pdev_name);
	259	r = -ENOMEM;
	260	goto err;
	261	}
	262
	263	if (parent != NULL)
	264	pdev->dev.parent = &parent->dev;
	265
	266	if (pdev->id != -1)
	267	dev_set_name(&pdev->dev, "%s.%d", pdev->name, pdev->id);
	268	else
	269	dev_set_name(&pdev->dev, "%s", pdev->name);
	270
	271	r = platform_device_add_data(pdev, pdata, pdata_len);
	272	if (r) {
	273	pr_err("Could not set pdata for %s\n", pdev_name);
	274	goto err;
	275	}
	276
c3a21fc7	277	r = platform_device_add(pdev);
53f576a8	278	if (r) {
c3a21fc7	279	pr_err("Could not register platform_device for %s\n", pdev_name);
53f576a8 TV	280	goto err;
	281	}
	282
	283	return pdev;
	284
	285	err:
	286	return ERR_PTR(r);
	287	}
	288
acd18af9 TV	289	static enum omapdss_version __init omap_display_get_version(void)
	290	{
	291	if (cpu_is_omap24xx())
	292	return OMAPDSS_VER_OMAP24xx;
	293	else if (cpu_is_omap3630())
	294	return OMAPDSS_VER_OMAP3630;
	295	else if (cpu_is_omap34xx()) {
	296	if (soc_is_am35xx()) {
	297	return OMAPDSS_VER_AM35xx;
	298	} else {
	299	if (omap_rev() < OMAP3430_REV_ES3_0)
	300	return OMAPDSS_VER_OMAP34xx_ES1;
	301	else
	302	return OMAPDSS_VER_OMAP34xx_ES3;
	303	}
	304	} else if (omap_rev() == OMAP4430_REV_ES1_0)
	305	return OMAPDSS_VER_OMAP4430_ES1;
	306	else if (omap_rev() == OMAP4430_REV_ES2_0 \|\|
	307	omap_rev() == OMAP4430_REV_ES2_1 \|\|
	308	omap_rev() == OMAP4430_REV_ES2_2)
	309	return OMAPDSS_VER_OMAP4430_ES2;
	310	else if (cpu_is_omap44xx())
	311	return OMAPDSS_VER_OMAP4;
	312	else if (soc_is_omap54xx())
	313	return OMAPDSS_VER_OMAP5;
	314	else
	315	return OMAPDSS_VER_UNKNOWN;
	316	}
	317
b7ee79ab SS	318	int __init omap_display_init(struct omap_dss_board_info *board_data)
	319	{
	320	int r = 0;
3528c58e	321	struct platform_device *pdev;
179e0453	322	int i, oh_count;
179e0453	323	const struct omap_dss_hwmod_data *curr_dss_hwmod;
966eaed0	324	struct platform_device *dss_pdev;
acd18af9	325	enum omapdss_version ver;
cf07f531	326
00928eaf TV	327	/* create omapdss device */
00928eaf TV	328
acd18af9 TV	329	ver = omap_display_get_version();
	330
	331	if (ver == OMAPDSS_VER_UNKNOWN) {
	332	pr_err("DSS not supported on this SoC\n");
	333	return -ENODEV;
	334	}
	335
	336	board_data->version = ver;
00928eaf TV	337	board_data->dsi_enable_pads = omap_dsi_enable_pads;
	338	board_data->dsi_disable_pads = omap_dsi_disable_pads;
	339	board_data->get_context_loss_count = omap_pm_get_dev_context_loss_count;
	340	board_data->set_min_bus_tput = omap_dss_set_min_bus_tput;
	341
	342	omap_display_device.dev.platform_data = board_data;
	343
	344	r = platform_device_register(&omap_display_device);
	345	if (r < 0) {
	346	pr_err("Unable to register omapdss device\n");
	347	return r;
	348	}
	349
	350	/* create devices for dss hwmods */
cf07f531	351
179e0453 AT	352	if (cpu_is_omap24xx()) {
	353	curr_dss_hwmod = omap2_dss_hwmod_data;
	354	oh_count = ARRAY_SIZE(omap2_dss_hwmod_data);
	355	} else if (cpu_is_omap34xx()) {
	356	curr_dss_hwmod = omap3_dss_hwmod_data;
	357	oh_count = ARRAY_SIZE(omap3_dss_hwmod_data);
	358	} else {
	359	curr_dss_hwmod = omap4_dss_hwmod_data;
	360	oh_count = ARRAY_SIZE(omap4_dss_hwmod_data);
	361	}
545376e7	362
966eaed0 TV	363	/*
	364	* First create the pdev for dss_core, which is used as a parent device
	365	* by the other dss pdevs. Note: dss_core has to be the first item in
	366	* the hwmod list.
	367	*/
	368	dss_pdev = create_dss_pdev(curr_dss_hwmod[0].dev_name,
	369	curr_dss_hwmod[0].id,
	370	curr_dss_hwmod[0].oh_name,
35deca3d	371	board_data, sizeof(*board_data),
966eaed0	372	NULL);
fd4b34f6	373
966eaed0 TV	374	if (IS_ERR(dss_pdev)) {
	375	pr_err("Could not build omap_device for %s\n",
	376	curr_dss_hwmod[0].oh_name);
	377
	378	return PTR_ERR(dss_pdev);
	379	}
	380
	381	for (i = 1; i < oh_count; i++) {
	382	pdev = create_dss_pdev(curr_dss_hwmod[i].dev_name,
	383	curr_dss_hwmod[i].id,
	384	curr_dss_hwmod[i].oh_name,
35deca3d	385	board_data, sizeof(*board_data),
966eaed0 TV	386	dss_pdev);
	387
	388	if (IS_ERR(pdev)) {
	389	pr_err("Could not build omap_device for %s\n",
	390	curr_dss_hwmod[i].oh_name);
cf07f531	391
966eaed0 TV	392	return PTR_ERR(pdev);
966eaed0 TV	393	}
cf07f531	394	}
b7ee79ab	395
53f576a8 TV	396	/* Create devices for DPI and SDI */
53f576a8 TV	397
35deca3d TV	398	pdev = create_simple_dss_pdev("omapdss_dpi", -1,
35deca3d TV	399	board_data, sizeof(*board_data), dss_pdev);
53f576a8 TV	400	if (IS_ERR(pdev)) {
	401	pr_err("Could not build platform_device for omapdss_dpi\n");
	402	return PTR_ERR(pdev);
	403	}
	404
	405	if (cpu_is_omap34xx()) {
35deca3d TV	406	pdev = create_simple_dss_pdev("omapdss_sdi", -1,
35deca3d TV	407	board_data, sizeof(*board_data), dss_pdev);
53f576a8 TV	408	if (IS_ERR(pdev)) {
	409	pr_err("Could not build platform_device for omapdss_sdi\n");
	410	return PTR_ERR(pdev);
	411	}
	412	}
	413
00928eaf	414	return 0;
b7ee79ab	415	}
13662dc5	416
b923d40d AT	417	static void dispc_disable_outputs(void)
	418	{
	419	u32 v, irq_mask = 0;
465698ee	420	bool lcd_en, digit_en, lcd2_en = false, lcd3_en = false;
b923d40d AT	421	int i;
	422	struct omap_dss_dispc_dev_attr *da;
	423	struct omap_hwmod *oh;
	424
	425	oh = omap_hwmod_lookup("dss_dispc");
	426	if (!oh) {
	427	WARN(1, "display: could not disable outputs during reset - could not find dss_dispc hwmod\n");
	428	return;
	429	}
	430
	431	if (!oh->dev_attr) {
	432	pr_err("display: could not disable outputs during reset due to missing dev_attr\n");
	433	return;
	434	}
	435
	436	da = (struct omap_dss_dispc_dev_attr *)oh->dev_attr;
	437
	438	/* store value of LCDENABLE and DIGITENABLE bits */
	439	v = omap_hwmod_read(oh, DISPC_CONTROL);
	440	lcd_en = v & LCD_EN_MASK;
	441	digit_en = v & DIGIT_EN_MASK;
	442
	443	/* store value of LCDENABLE for LCD2 */
	444	if (da->manager_count > 2) {
	445	v = omap_hwmod_read(oh, DISPC_CONTROL2);
	446	lcd2_en = v & LCD_EN_MASK;
	447	}
	448
465698ee CM	449	/* store value of LCDENABLE for LCD3 */
	450	if (da->manager_count > 3) {
	451	v = omap_hwmod_read(oh, DISPC_CONTROL3);
	452	lcd3_en = v & LCD_EN_MASK;
	453	}
	454
	455	if (!(lcd_en \| digit_en \| lcd2_en \| lcd3_en))
b923d40d AT	456	return; /* no managers currently enabled */
	457
	458	/*
	459	* If any manager was enabled, we need to disable it before
	460	* DSS clocks are disabled or DISPC module is reset
	461	*/
	462	if (lcd_en)
	463	irq_mask \|= 1 << FRAMEDONE_IRQ_SHIFT;
	464
	465	if (digit_en) {
	466	if (da->has_framedonetv_irq) {
	467	irq_mask \|= 1 << FRAMEDONETV_IRQ_SHIFT;
	468	} else {
	469	irq_mask \|= 1 << EVSYNC_EVEN_IRQ_SHIFT \|
	470	1 << EVSYNC_ODD_IRQ_SHIFT;
	471	}
	472	}
	473
	474	if (lcd2_en)
	475	irq_mask \|= 1 << FRAMEDONE2_IRQ_SHIFT;
465698ee CM	476	if (lcd3_en)
465698ee CM	477	irq_mask \|= 1 << FRAMEDONE3_IRQ_SHIFT;
b923d40d AT	478
	479	/*
	480	* clear any previous FRAMEDONE, FRAMEDONETV,
465698ee	481	* EVSYNC_EVEN/ODD, FRAMEDONE2 or FRAMEDONE3 interrupts
b923d40d AT	482	*/
	483	omap_hwmod_write(irq_mask, oh, DISPC_IRQSTATUS);
	484
	485	/* disable LCD and TV managers */
	486	v = omap_hwmod_read(oh, DISPC_CONTROL);
	487	v &= ~(LCD_EN_MASK \| DIGIT_EN_MASK);
	488	omap_hwmod_write(v, oh, DISPC_CONTROL);
	489
	490	/* disable LCD2 manager */
	491	if (da->manager_count > 2) {
	492	v = omap_hwmod_read(oh, DISPC_CONTROL2);
	493	v &= ~LCD_EN_MASK;
	494	omap_hwmod_write(v, oh, DISPC_CONTROL2);
	495	}
	496
465698ee CM	497	/* disable LCD3 manager */
	498	if (da->manager_count > 3) {
	499	v = omap_hwmod_read(oh, DISPC_CONTROL3);
	500	v &= ~LCD_EN_MASK;
	501	omap_hwmod_write(v, oh, DISPC_CONTROL3);
	502	}
	503
b923d40d AT	504	i = 0;
	505	while ((omap_hwmod_read(oh, DISPC_IRQSTATUS) & irq_mask) !=
	506	irq_mask) {
	507	i++;
	508	if (i > FRAMEDONE_IRQ_TIMEOUT) {
465698ee	509	pr_err("didn't get FRAMEDONE1/2/3 or TV interrupt\n");
b923d40d AT	510	break;
	511	}
	512	mdelay(1);
	513	}
	514	}
	515
13662dc5 TV	516	int omap_dss_reset(struct omap_hwmod *oh)
	517	{
	518	struct omap_hwmod_opt_clk *oc;
	519	int c = 0;
	520	int i, r;
	521
	522	if (!(oh->class->sysc->sysc_flags & SYSS_HAS_RESET_STATUS)) {
	523	pr_err("dss_core: hwmod data doesn't contain reset data\n");
	524	return -EINVAL;
	525	}
	526
	527	for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++)
	528	if (oc->_clk)
4d7cb45e	529	clk_prepare_enable(oc->_clk);
13662dc5	530
b923d40d AT	531	dispc_disable_outputs();
	532
	533	/* clear SDI registers */
	534	if (cpu_is_omap3430()) {
	535	omap_hwmod_write(0x0, oh, DSS_SDI_CONTROL);
	536	omap_hwmod_write(0x0, oh, DSS_PLL_CONTROL);
	537	}
	538
	539	/*
	540	* clear DSS_CONTROL register to switch DSS clock sources to
	541	* PRCM clock, if any
	542	*/
	543	omap_hwmod_write(0x0, oh, DSS_CONTROL);
	544
13662dc5 TV	545	omap_test_timeout((omap_hwmod_read(oh, oh->class->sysc->syss_offs)
	546	& SYSS_RESETDONE_MASK),
	547	MAX_MODULE_SOFTRESET_WAIT, c);
	548
	549	if (c == MAX_MODULE_SOFTRESET_WAIT)
	550	pr_warning("dss_core: waiting for reset to finish failed\n");
	551	else
	552	pr_debug("dss_core: softreset done\n");
	553
	554	for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++)
	555	if (oc->_clk)
4d7cb45e	556	clk_disable_unprepare(oc->_clk);
13662dc5 TV	557
	558	r = (c == MAX_MODULE_SOFTRESET_WAIT) ? -ETIMEDOUT : 0;
	559
	560	return r;
	561	}