[deliverable/linux.git] / arch / arm / mach-omap2 / display.c

/*
 * OMAP2plus display device setup / initialization.
 *
 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
 *	Senthilvadivu Guruswamy
 *	Sumit Semwal
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
 * kind, whether express or implied; without even the implied warranty
 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <linux/string.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/io.h>
#include <linux/clk.h>
#include <linux/err.h>
#include <linux/delay.h>
#include <linux/of.h>
#include <linux/of_platform.h>
#include <linux/slab.h>
#include <linux/mfd/syscon.h>
#include <linux/regmap.h>

#include <video/omapdss.h>
#include "omap_hwmod.h"
#include "omap_device.h"
#include "omap-pm.h"
#include "common.h"

#include "soc.h"
#include "iomap.h"
#include "control.h"
#include "display.h"
#include "prm.h"

#define DISPC_CONTROL		0x0040
#define DISPC_CONTROL2		0x0238
#define DISPC_CONTROL3		0x0848
#define DISPC_IRQSTATUS		0x0018

#define DSS_SYSCONFIG		0x10
#define DSS_SYSSTATUS		0x14
#define DSS_CONTROL		0x40
#define DSS_SDI_CONTROL		0x44
#define DSS_PLL_CONTROL		0x48

#define LCD_EN_MASK		(0x1 << 0)
#define DIGIT_EN_MASK		(0x1 << 1)

#define FRAMEDONE_IRQ_SHIFT	0
#define EVSYNC_EVEN_IRQ_SHIFT	2
#define EVSYNC_ODD_IRQ_SHIFT	3
#define FRAMEDONE2_IRQ_SHIFT	22
#define FRAMEDONE3_IRQ_SHIFT	30
#define FRAMEDONETV_IRQ_SHIFT	24

/*
 * FRAMEDONE_IRQ_TIMEOUT: how long (in milliseconds) to wait during DISPC
 *     reset before deciding that something has gone wrong
 */
#define FRAMEDONE_IRQ_TIMEOUT		100

static struct platform_device omap_display_device = {
	.name          = "omapdss",
	.id            = -1,
	.dev            = {
		.platform_data = NULL,
	},
};

struct omap_dss_hwmod_data {
	const char *oh_name;
	const char *dev_name;
	const int id;
};

static const struct omap_dss_hwmod_data omap2_dss_hwmod_data[] __initconst = {
	{ "dss_core", "omapdss_dss", -1 },
	{ "dss_dispc", "omapdss_dispc", -1 },
	{ "dss_rfbi", "omapdss_rfbi", -1 },
	{ "dss_venc", "omapdss_venc", -1 },
};

static const struct omap_dss_hwmod_data omap3_dss_hwmod_data[] __initconst = {
	{ "dss_core", "omapdss_dss", -1 },
	{ "dss_dispc", "omapdss_dispc", -1 },
	{ "dss_rfbi", "omapdss_rfbi", -1 },
	{ "dss_venc", "omapdss_venc", -1 },
	{ "dss_dsi1", "omapdss_dsi", 0 },
};

static const struct omap_dss_hwmod_data omap4_dss_hwmod_data[] __initconst = {
	{ "dss_core", "omapdss_dss", -1 },
	{ "dss_dispc", "omapdss_dispc", -1 },
	{ "dss_rfbi", "omapdss_rfbi", -1 },
	{ "dss_dsi1", "omapdss_dsi", 0 },
	{ "dss_dsi2", "omapdss_dsi", 1 },
	{ "dss_hdmi", "omapdss_hdmi", -1 },
};

#define OMAP4_DSIPHY_SYSCON_OFFSET		0x78

static struct regmap *omap4_dsi_mux_syscon;

static int omap4_dsi_mux_pads(int dsi_id, unsigned lanes)
{
	u32 enable_mask, enable_shift;
	u32 pipd_mask, pipd_shift;
	u32 reg;

	if (dsi_id == 0) {
		enable_mask = OMAP4_DSI1_LANEENABLE_MASK;
		enable_shift = OMAP4_DSI1_LANEENABLE_SHIFT;
		pipd_mask = OMAP4_DSI1_PIPD_MASK;
		pipd_shift = OMAP4_DSI1_PIPD_SHIFT;
	} else if (dsi_id == 1) {
		enable_mask = OMAP4_DSI2_LANEENABLE_MASK;
		enable_shift = OMAP4_DSI2_LANEENABLE_SHIFT;
		pipd_mask = OMAP4_DSI2_PIPD_MASK;
		pipd_shift = OMAP4_DSI2_PIPD_SHIFT;
	} else {
		return -ENODEV;
	}

	regmap_read(omap4_dsi_mux_syscon, OMAP4_DSIPHY_SYSCON_OFFSET, &reg);

	reg &= ~enable_mask;
	reg &= ~pipd_mask;

	reg |= (lanes << enable_shift) & enable_mask;
	reg |= (lanes << pipd_shift) & pipd_mask;

	regmap_write(omap4_dsi_mux_syscon, OMAP4_DSIPHY_SYSCON_OFFSET, reg);

	return 0;
}

static int omap_dsi_enable_pads(int dsi_id, unsigned lane_mask)
{
	if (cpu_is_omap44xx())
		return omap4_dsi_mux_pads(dsi_id, lane_mask);

	return 0;
}

static void omap_dsi_disable_pads(int dsi_id, unsigned lane_mask)
{
	if (cpu_is_omap44xx())
		omap4_dsi_mux_pads(dsi_id, 0);
}

static int omap_dss_set_min_bus_tput(struct device *dev, unsigned long tput)
{
	return omap_pm_set_min_bus_tput(dev, OCP_INITIATOR_AGENT, tput);
}

static struct platform_device *create_dss_pdev(const char *pdev_name,
		int pdev_id, const char *oh_name, void *pdata, int pdata_len,
		struct platform_device *parent)
{
	struct platform_device *pdev;
	struct omap_device *od;
	struct omap_hwmod *ohs[1];
	struct omap_hwmod *oh;
	int r;

	oh = omap_hwmod_lookup(oh_name);
	if (!oh) {
		pr_err("Could not look up %s\n", oh_name);
		r = -ENODEV;
		goto err;
	}

	pdev = platform_device_alloc(pdev_name, pdev_id);
	if (!pdev) {
		pr_err("Could not create pdev for %s\n", pdev_name);
		r = -ENOMEM;
		goto err;
	}

	if (parent != NULL)
		pdev->dev.parent = &parent->dev;

	if (pdev->id != -1)
		dev_set_name(&pdev->dev, "%s.%d", pdev->name, pdev->id);
	else
		dev_set_name(&pdev->dev, "%s", pdev->name);

	ohs[0] = oh;
	od = omap_device_alloc(pdev, ohs, 1);
	if (IS_ERR(od)) {
		pr_err("Could not alloc omap_device for %s\n", pdev_name);
		r = -ENOMEM;
		goto err;
	}

	r = platform_device_add_data(pdev, pdata, pdata_len);
	if (r) {
		pr_err("Could not set pdata for %s\n", pdev_name);
		goto err;
	}

	r = omap_device_register(pdev);
	if (r) {
		pr_err("Could not register omap_device for %s\n", pdev_name);
		goto err;
	}

	return pdev;

err:
	return ERR_PTR(r);
}

static struct platform_device *create_simple_dss_pdev(const char *pdev_name,
		int pdev_id, void *pdata, int pdata_len,
		struct platform_device *parent)
{
	struct platform_device *pdev;
	int r;

	pdev = platform_device_alloc(pdev_name, pdev_id);
	if (!pdev) {
		pr_err("Could not create pdev for %s\n", pdev_name);
		r = -ENOMEM;
		goto err;
	}

	if (parent != NULL)
		pdev->dev.parent = &parent->dev;

	if (pdev->id != -1)
		dev_set_name(&pdev->dev, "%s.%d", pdev->name, pdev->id);
	else
		dev_set_name(&pdev->dev, "%s", pdev->name);

	r = platform_device_add_data(pdev, pdata, pdata_len);
	if (r) {
		pr_err("Could not set pdata for %s\n", pdev_name);
		goto err;
	}

	r = platform_device_add(pdev);
	if (r) {
		pr_err("Could not register platform_device for %s\n", pdev_name);
		goto err;
	}

	return pdev;

err:
	return ERR_PTR(r);
}

static enum omapdss_version __init omap_display_get_version(void)
{
	if (cpu_is_omap24xx())
		return OMAPDSS_VER_OMAP24xx;
	else if (cpu_is_omap3630())
		return OMAPDSS_VER_OMAP3630;
	else if (cpu_is_omap34xx()) {
		if (soc_is_am35xx()) {
			return OMAPDSS_VER_AM35xx;
		} else {
			if (omap_rev() < OMAP3430_REV_ES3_0)
				return OMAPDSS_VER_OMAP34xx_ES1;
			else
				return OMAPDSS_VER_OMAP34xx_ES3;
		}
	} else if (omap_rev() == OMAP4430_REV_ES1_0)
		return OMAPDSS_VER_OMAP4430_ES1;
	else if (omap_rev() == OMAP4430_REV_ES2_0 ||
			omap_rev() == OMAP4430_REV_ES2_1 ||
			omap_rev() == OMAP4430_REV_ES2_2)
		return OMAPDSS_VER_OMAP4430_ES2;
	else if (cpu_is_omap44xx())
		return OMAPDSS_VER_OMAP4;
	else if (soc_is_omap54xx())
		return OMAPDSS_VER_OMAP5;
	else if (soc_is_am43xx())
		return OMAPDSS_VER_AM43xx;
	else if (soc_is_dra7xx())
		return OMAPDSS_VER_DRA7xx;
	else
		return OMAPDSS_VER_UNKNOWN;
}

int __init omap_display_init(struct omap_dss_board_info *board_data)
{
	int r = 0;
	struct platform_device *pdev;
	int i, oh_count;
	const struct omap_dss_hwmod_data *curr_dss_hwmod;
	struct platform_device *dss_pdev;
	enum omapdss_version ver;

	/* create omapdss device */

	ver = omap_display_get_version();

	if (ver == OMAPDSS_VER_UNKNOWN) {
		pr_err("DSS not supported on this SoC\n");
		return -ENODEV;
	}

	board_data->version = ver;
	board_data->dsi_enable_pads = omap_dsi_enable_pads;
	board_data->dsi_disable_pads = omap_dsi_disable_pads;
	board_data->set_min_bus_tput = omap_dss_set_min_bus_tput;

	omap_display_device.dev.platform_data = board_data;

	r = platform_device_register(&omap_display_device);
	if (r < 0) {
		pr_err("Unable to register omapdss device\n");
		return r;
	}

	/* create devices for dss hwmods */

	if (cpu_is_omap24xx()) {
		curr_dss_hwmod = omap2_dss_hwmod_data;
		oh_count = ARRAY_SIZE(omap2_dss_hwmod_data);
	} else if (cpu_is_omap34xx()) {
		curr_dss_hwmod = omap3_dss_hwmod_data;
		oh_count = ARRAY_SIZE(omap3_dss_hwmod_data);
	} else {
		curr_dss_hwmod = omap4_dss_hwmod_data;
		oh_count = ARRAY_SIZE(omap4_dss_hwmod_data);
	}

	/*
	 * First create the pdev for dss_core, which is used as a parent device
	 * by the other dss pdevs. Note: dss_core has to be the first item in
	 * the hwmod list.
	 */
	dss_pdev = create_dss_pdev(curr_dss_hwmod[0].dev_name,
			curr_dss_hwmod[0].id,
			curr_dss_hwmod[0].oh_name,
			board_data, sizeof(*board_data),
			NULL);

	if (IS_ERR(dss_pdev)) {
		pr_err("Could not build omap_device for %s\n",
				curr_dss_hwmod[0].oh_name);

		return PTR_ERR(dss_pdev);
	}

	for (i = 1; i < oh_count; i++) {
		pdev = create_dss_pdev(curr_dss_hwmod[i].dev_name,
				curr_dss_hwmod[i].id,
				curr_dss_hwmod[i].oh_name,
				board_data, sizeof(*board_data),
				dss_pdev);

		if (IS_ERR(pdev)) {
			pr_err("Could not build omap_device for %s\n",
					curr_dss_hwmod[i].oh_name);

			return PTR_ERR(pdev);
		}
	}

	/* Create devices for DPI and SDI */

	pdev = create_simple_dss_pdev("omapdss_dpi", 0,
			board_data, sizeof(*board_data), dss_pdev);
	if (IS_ERR(pdev)) {
		pr_err("Could not build platform_device for omapdss_dpi\n");
		return PTR_ERR(pdev);
	}

	if (cpu_is_omap34xx()) {
		pdev = create_simple_dss_pdev("omapdss_sdi", 0,
				board_data, sizeof(*board_data), dss_pdev);
		if (IS_ERR(pdev)) {
			pr_err("Could not build platform_device for omapdss_sdi\n");
			return PTR_ERR(pdev);
		}
	}

	/* create DRM device */
	r = omap_init_drm();
	if (r < 0) {
		pr_err("Unable to register omapdrm device\n");
		return r;
	}

	/* create vrfb device */
	r = omap_init_vrfb();
	if (r < 0) {
		pr_err("Unable to register omapvrfb device\n");
		return r;
	}

	/* create FB device */
	r = omap_init_fb();
	if (r < 0) {
		pr_err("Unable to register omapfb device\n");
		return r;
	}

	/* create V4L2 display device */
	r = omap_init_vout();
	if (r < 0) {
		pr_err("Unable to register omap_vout device\n");
		return r;
	}

	return 0;
}

static void dispc_disable_outputs(void)
{
	u32 v, irq_mask = 0;
	bool lcd_en, digit_en, lcd2_en = false, lcd3_en = false;
	int i;
	struct omap_dss_dispc_dev_attr *da;
	struct omap_hwmod *oh;

	oh = omap_hwmod_lookup("dss_dispc");
	if (!oh) {
		WARN(1, "display: could not disable outputs during reset - could not find dss_dispc hwmod\n");
		return;
	}

	if (!oh->dev_attr) {
		pr_err("display: could not disable outputs during reset due to missing dev_attr\n");
		return;
	}

	da = (struct omap_dss_dispc_dev_attr *)oh->dev_attr;

	/* store value of LCDENABLE and DIGITENABLE bits */
	v = omap_hwmod_read(oh, DISPC_CONTROL);
	lcd_en = v & LCD_EN_MASK;
	digit_en = v & DIGIT_EN_MASK;

	/* store value of LCDENABLE for LCD2 */
	if (da->manager_count > 2) {
		v = omap_hwmod_read(oh, DISPC_CONTROL2);
		lcd2_en = v & LCD_EN_MASK;
	}

	/* store value of LCDENABLE for LCD3 */
	if (da->manager_count > 3) {
		v = omap_hwmod_read(oh, DISPC_CONTROL3);
		lcd3_en = v & LCD_EN_MASK;
	}

	if (!(lcd_en | digit_en | lcd2_en | lcd3_en))
		return; /* no managers currently enabled */

	/*
	 * If any manager was enabled, we need to disable it before
	 * DSS clocks are disabled or DISPC module is reset
	 */
	if (lcd_en)
		irq_mask |= 1 << FRAMEDONE_IRQ_SHIFT;

	if (digit_en) {
		if (da->has_framedonetv_irq) {
			irq_mask |= 1 << FRAMEDONETV_IRQ_SHIFT;
		} else {
			irq_mask |= 1 << EVSYNC_EVEN_IRQ_SHIFT |
				1 << EVSYNC_ODD_IRQ_SHIFT;
		}
	}

	if (lcd2_en)
		irq_mask |= 1 << FRAMEDONE2_IRQ_SHIFT;
	if (lcd3_en)
		irq_mask |= 1 << FRAMEDONE3_IRQ_SHIFT;

	/*
	 * clear any previous FRAMEDONE, FRAMEDONETV,
	 * EVSYNC_EVEN/ODD, FRAMEDONE2 or FRAMEDONE3 interrupts
	 */
	omap_hwmod_write(irq_mask, oh, DISPC_IRQSTATUS);

	/* disable LCD and TV managers */
	v = omap_hwmod_read(oh, DISPC_CONTROL);
	v &= ~(LCD_EN_MASK | DIGIT_EN_MASK);
	omap_hwmod_write(v, oh, DISPC_CONTROL);

	/* disable LCD2 manager */
	if (da->manager_count > 2) {
		v = omap_hwmod_read(oh, DISPC_CONTROL2);
		v &= ~LCD_EN_MASK;
		omap_hwmod_write(v, oh, DISPC_CONTROL2);
	}

	/* disable LCD3 manager */
	if (da->manager_count > 3) {
		v = omap_hwmod_read(oh, DISPC_CONTROL3);
		v &= ~LCD_EN_MASK;
		omap_hwmod_write(v, oh, DISPC_CONTROL3);
	}

	i = 0;
	while ((omap_hwmod_read(oh, DISPC_IRQSTATUS) & irq_mask) !=
	       irq_mask) {
		i++;
		if (i > FRAMEDONE_IRQ_TIMEOUT) {
			pr_err("didn't get FRAMEDONE1/2/3 or TV interrupt\n");
			break;
		}
		mdelay(1);
	}
}

int omap_dss_reset(struct omap_hwmod *oh)
{
	struct omap_hwmod_opt_clk *oc;
	int c = 0;
	int i, r;

	if (!(oh->class->sysc->sysc_flags & SYSS_HAS_RESET_STATUS)) {
		pr_err("dss_core: hwmod data doesn't contain reset data\n");
		return -EINVAL;
	}

	for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++)
		if (oc->_clk)
			clk_prepare_enable(oc->_clk);

	dispc_disable_outputs();

	/* clear SDI registers */
	if (cpu_is_omap3430()) {
		omap_hwmod_write(0x0, oh, DSS_SDI_CONTROL);
		omap_hwmod_write(0x0, oh, DSS_PLL_CONTROL);
	}

	/*
	 * clear DSS_CONTROL register to switch DSS clock sources to
	 * PRCM clock, if any
	 */
	omap_hwmod_write(0x0, oh, DSS_CONTROL);

	omap_test_timeout((omap_hwmod_read(oh, oh->class->sysc->syss_offs)
				& SYSS_RESETDONE_MASK),
			MAX_MODULE_SOFTRESET_WAIT, c);

	if (c == MAX_MODULE_SOFTRESET_WAIT)
		pr_warn("dss_core: waiting for reset to finish failed\n");
	else
		pr_debug("dss_core: softreset done\n");

	for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++)
		if (oc->_clk)
			clk_disable_unprepare(oc->_clk);

	r = (c == MAX_MODULE_SOFTRESET_WAIT) ? -ETIMEDOUT : 0;

	return r;
}

void __init omapdss_early_init_of(void)
{

}

static const char * const omapdss_compat_names[] __initconst = {
	"ti,omap2-dss",
	"ti,omap3-dss",
	"ti,omap4-dss",
	"ti,omap5-dss",
	"ti,dra7-dss",
};

struct device_node * __init omapdss_find_dss_of_node(void)
{
	struct device_node *node;
	int i;

	for (i = 0; i < ARRAY_SIZE(omapdss_compat_names); ++i) {
		node = of_find_compatible_node(NULL, NULL,
			omapdss_compat_names[i]);
		if (node)
			return node;
	}

	return NULL;
}

int __init omapdss_init_of(void)
{
	int r;
	enum omapdss_version ver;
	struct device_node *node;
	struct platform_device *pdev;

	static struct omap_dss_board_info board_data = {
		.dsi_enable_pads = omap_dsi_enable_pads,
		.dsi_disable_pads = omap_dsi_disable_pads,
		.set_min_bus_tput = omap_dss_set_min_bus_tput,
	};

	/* only create dss helper devices if dss is enabled in the .dts */

	node = omapdss_find_dss_of_node();
	if (!node)
		return 0;

	if (!of_device_is_available(node))
		return 0;

	ver = omap_display_get_version();

	if (ver == OMAPDSS_VER_UNKNOWN) {
		pr_err("DSS not supported on this SoC\n");
		return -ENODEV;
	}

	pdev = of_find_device_by_node(node);

	if (!pdev) {
		pr_err("Unable to find DSS platform device\n");
		return -ENODEV;
	}

	r = of_platform_populate(node, NULL, NULL, &pdev->dev);
	if (r) {
		pr_err("Unable to populate DSS submodule devices\n");
		return r;
	}

	board_data.version = ver;

	omap_display_device.dev.platform_data = &board_data;

	r = platform_device_register(&omap_display_device);
	if (r < 0) {
		pr_err("Unable to register omapdss device\n");
		return r;
	}

	/* create DRM device */
	r = omap_init_drm();
	if (r < 0) {
		pr_err("Unable to register omapdrm device\n");
		return r;
	}

	/* create vrfb device */
	r = omap_init_vrfb();
	if (r < 0) {
		pr_err("Unable to register omapvrfb device\n");
		return r;
	}

	/* create FB device */
	r = omap_init_fb();
	if (r < 0) {
		pr_err("Unable to register omapfb device\n");
		return r;
	}

	/* create V4L2 display device */
	r = omap_init_vout();
	if (r < 0) {
		pr_err("Unable to register omap_vout device\n");
		return r;
	}

	/* add DSI info for omap4 */
	node = of_find_node_by_name(NULL, "omap4_padconf_global");
	if (node)
		omap4_dsi_mux_syscon = syscon_node_to_regmap(node);

	return 0;
}
Commit	Line	Data
b7ee79ab SS	1	/*
	2	* OMAP2plus display device setup / initialization.
	3	*
	4	* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
	5	* Senthilvadivu Guruswamy
	6	* Sumit Semwal
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License version 2 as
	10	* published by the Free Software Foundation.
	11	*
	12	* This program is distributed "as is" WITHOUT ANY WARRANTY of any
	13	* kind, whether express or implied; without even the implied warranty
	14	* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*/
	17
d44b28c4	18	#include <linux/string.h>
b7ee79ab SS	19	#include <linux/kernel.h>
	20	#include <linux/init.h>
	21	#include <linux/platform_device.h>
	22	#include <linux/io.h>
	23	#include <linux/clk.h>
	24	#include <linux/err.h>
deee6d53	25	#include <linux/delay.h>
dcdf407b TV	26	#include <linux/of.h>
dcdf407b TV	27	#include <linux/of_platform.h>
6a0e6b38	28	#include <linux/slab.h>
23d34981 TK	29	#include <linux/mfd/syscon.h>
23d34981 TK	30	#include <linux/regmap.h>
b7ee79ab	31
a0b38cc4	32	#include <video/omapdss.h>
2a296c8f	33	#include "omap_hwmod.h"
25c7d49e	34	#include "omap_device.h"
1d5aef49	35	#include "omap-pm.h"
deee6d53	36	#include "common.h"
b7ee79ab	37
e4c060db	38	#include "soc.h"
ee0839c2	39	#include "iomap.h"
dc35835c	40	#include "control.h"
b923d40d	41	#include "display.h"
b13159af	42	#include "prm.h"
b923d40d AT	43
	44	#define DISPC_CONTROL 0x0040
	45	#define DISPC_CONTROL2 0x0238
465698ee	46	#define DISPC_CONTROL3 0x0848
b923d40d AT	47	#define DISPC_IRQSTATUS 0x0018
	48
	49	#define DSS_SYSCONFIG 0x10
	50	#define DSS_SYSSTATUS 0x14
	51	#define DSS_CONTROL 0x40
	52	#define DSS_SDI_CONTROL 0x44
	53	#define DSS_PLL_CONTROL 0x48
	54
	55	#define LCD_EN_MASK (0x1 << 0)
	56	#define DIGIT_EN_MASK (0x1 << 1)
	57
	58	#define FRAMEDONE_IRQ_SHIFT 0
	59	#define EVSYNC_EVEN_IRQ_SHIFT 2
	60	#define EVSYNC_ODD_IRQ_SHIFT 3
	61	#define FRAMEDONE2_IRQ_SHIFT 22
465698ee	62	#define FRAMEDONE3_IRQ_SHIFT 30
b923d40d AT	63	#define FRAMEDONETV_IRQ_SHIFT 24
	64
	65	/*
	66	* FRAMEDONE_IRQ_TIMEOUT: how long (in milliseconds) to wait during DISPC
	67	* reset before deciding that something has gone wrong
	68	*/
	69	#define FRAMEDONE_IRQ_TIMEOUT 100
dc35835c	70
b7ee79ab SS	71	static struct platform_device omap_display_device = {
	72	.name = "omapdss",
	73	.id = -1,
	74	.dev = {
	75	.platform_data = NULL,
	76	},
	77	};
	78
179e0453 AT	79	struct omap_dss_hwmod_data {
	80	const char *oh_name;
	81	const char *dev_name;
	82	const int id;
	83	};
	84
bcad6dc3	85	static const struct omap_dss_hwmod_data omap2_dss_hwmod_data[] __initconst = {
179e0453 AT	86	{ "dss_core", "omapdss_dss", -1 },
	87	{ "dss_dispc", "omapdss_dispc", -1 },
	88	{ "dss_rfbi", "omapdss_rfbi", -1 },
	89	{ "dss_venc", "omapdss_venc", -1 },
	90	};
	91
bcad6dc3	92	static const struct omap_dss_hwmod_data omap3_dss_hwmod_data[] __initconst = {
179e0453 AT	93	{ "dss_core", "omapdss_dss", -1 },
	94	{ "dss_dispc", "omapdss_dispc", -1 },
	95	{ "dss_rfbi", "omapdss_rfbi", -1 },
	96	{ "dss_venc", "omapdss_venc", -1 },
7c68dd96	97	{ "dss_dsi1", "omapdss_dsi", 0 },
179e0453 AT	98	};
179e0453 AT	99
bcad6dc3	100	static const struct omap_dss_hwmod_data omap4_dss_hwmod_data[] __initconst = {
179e0453 AT	101	{ "dss_core", "omapdss_dss", -1 },
	102	{ "dss_dispc", "omapdss_dispc", -1 },
	103	{ "dss_rfbi", "omapdss_rfbi", -1 },
7c68dd96 TV	104	{ "dss_dsi1", "omapdss_dsi", 0 },
7c68dd96 TV	105	{ "dss_dsi2", "omapdss_dsi", 1 },
179e0453 AT	106	{ "dss_hdmi", "omapdss_hdmi", -1 },
	107	};
	108
23d34981 TK	109	#define OMAP4_DSIPHY_SYSCON_OFFSET 0x78
	110
	111	static struct regmap *omap4_dsi_mux_syscon;
	112
130f769e TV	113	static int omap4_dsi_mux_pads(int dsi_id, unsigned lanes)
	114	{
	115	u32 enable_mask, enable_shift;
	116	u32 pipd_mask, pipd_shift;
	117	u32 reg;
	118
	119	if (dsi_id == 0) {
	120	enable_mask = OMAP4_DSI1_LANEENABLE_MASK;
	121	enable_shift = OMAP4_DSI1_LANEENABLE_SHIFT;
	122	pipd_mask = OMAP4_DSI1_PIPD_MASK;
	123	pipd_shift = OMAP4_DSI1_PIPD_SHIFT;
	124	} else if (dsi_id == 1) {
	125	enable_mask = OMAP4_DSI2_LANEENABLE_MASK;
	126	enable_shift = OMAP4_DSI2_LANEENABLE_SHIFT;
	127	pipd_mask = OMAP4_DSI2_PIPD_MASK;
	128	pipd_shift = OMAP4_DSI2_PIPD_SHIFT;
	129	} else {
	130	return -ENODEV;
	131	}
	132
23d34981	133	regmap_read(omap4_dsi_mux_syscon, OMAP4_DSIPHY_SYSCON_OFFSET, &reg);
130f769e TV	134
	135	reg &= ~enable_mask;
	136	reg &= ~pipd_mask;
	137
	138	reg \|= (lanes << enable_shift) & enable_mask;
	139	reg \|= (lanes << pipd_shift) & pipd_mask;
	140
23d34981	141	regmap_write(omap4_dsi_mux_syscon, OMAP4_DSIPHY_SYSCON_OFFSET, reg);
130f769e TV	142
	143	return 0;
	144	}
	145
e8a30b25	146	static int omap_dsi_enable_pads(int dsi_id, unsigned lane_mask)
5bc416cb	147	{
130f769e TV	148	if (cpu_is_omap44xx())
	149	return omap4_dsi_mux_pads(dsi_id, lane_mask);
	150
5bc416cb TV	151	return 0;
	152	}
	153
e8a30b25	154	static void omap_dsi_disable_pads(int dsi_id, unsigned lane_mask)
5bc416cb	155	{
130f769e TV	156	if (cpu_is_omap44xx())
130f769e TV	157	omap4_dsi_mux_pads(dsi_id, 0);
5bc416cb TV	158	}
5bc416cb TV	159
62c1dcfc TV	160	static int omap_dss_set_min_bus_tput(struct device *dev, unsigned long tput)
	161	{
	162	return omap_pm_set_min_bus_tput(dev, OCP_INITIATOR_AGENT, tput);
	163	}
	164
966eaed0 TV	165	static struct platform_device create_dss_pdev(const char pdev_name,
	166	int pdev_id, const char oh_name, void pdata, int pdata_len,
	167	struct platform_device *parent)
	168	{
	169	struct platform_device *pdev;
	170	struct omap_device *od;
	171	struct omap_hwmod *ohs[1];
	172	struct omap_hwmod *oh;
	173	int r;
	174
	175	oh = omap_hwmod_lookup(oh_name);
	176	if (!oh) {
	177	pr_err("Could not look up %s\n", oh_name);
	178	r = -ENODEV;
	179	goto err;
	180	}
	181
	182	pdev = platform_device_alloc(pdev_name, pdev_id);
	183	if (!pdev) {
	184	pr_err("Could not create pdev for %s\n", pdev_name);
	185	r = -ENOMEM;
	186	goto err;
	187	}
	188
	189	if (parent != NULL)
	190	pdev->dev.parent = &parent->dev;
	191
	192	if (pdev->id != -1)
	193	dev_set_name(&pdev->dev, "%s.%d", pdev->name, pdev->id);
	194	else
	195	dev_set_name(&pdev->dev, "%s", pdev->name);
	196
	197	ohs[0] = oh;
c1d1cd59	198	od = omap_device_alloc(pdev, ohs, 1);
9ee67723	199	if (IS_ERR(od)) {
966eaed0 TV	200	pr_err("Could not alloc omap_device for %s\n", pdev_name);
	201	r = -ENOMEM;
	202	goto err;
	203	}
	204
	205	r = platform_device_add_data(pdev, pdata, pdata_len);
	206	if (r) {
	207	pr_err("Could not set pdata for %s\n", pdev_name);
	208	goto err;
	209	}
	210
	211	r = omap_device_register(pdev);
	212	if (r) {
	213	pr_err("Could not register omap_device for %s\n", pdev_name);
	214	goto err;
	215	}
	216
	217	return pdev;
	218
	219	err:
	220	return ERR_PTR(r);
	221	}
	222
53f576a8 TV	223	static struct platform_device create_simple_dss_pdev(const char pdev_name,
	224	int pdev_id, void *pdata, int pdata_len,
	225	struct platform_device *parent)
	226	{
	227	struct platform_device *pdev;
	228	int r;
	229
	230	pdev = platform_device_alloc(pdev_name, pdev_id);
	231	if (!pdev) {
	232	pr_err("Could not create pdev for %s\n", pdev_name);
	233	r = -ENOMEM;
	234	goto err;
	235	}
	236
	237	if (parent != NULL)
	238	pdev->dev.parent = &parent->dev;
	239
	240	if (pdev->id != -1)
	241	dev_set_name(&pdev->dev, "%s.%d", pdev->name, pdev->id);
	242	else
	243	dev_set_name(&pdev->dev, "%s", pdev->name);
	244
	245	r = platform_device_add_data(pdev, pdata, pdata_len);
	246	if (r) {
	247	pr_err("Could not set pdata for %s\n", pdev_name);
	248	goto err;
	249	}
	250
c3a21fc7	251	r = platform_device_add(pdev);
53f576a8	252	if (r) {
c3a21fc7	253	pr_err("Could not register platform_device for %s\n", pdev_name);
53f576a8 TV	254	goto err;
	255	}
	256
	257	return pdev;
	258
	259	err:
	260	return ERR_PTR(r);
	261	}
	262
acd18af9 TV	263	static enum omapdss_version __init omap_display_get_version(void)
	264	{
	265	if (cpu_is_omap24xx())
	266	return OMAPDSS_VER_OMAP24xx;
	267	else if (cpu_is_omap3630())
	268	return OMAPDSS_VER_OMAP3630;
	269	else if (cpu_is_omap34xx()) {
	270	if (soc_is_am35xx()) {
	271	return OMAPDSS_VER_AM35xx;
	272	} else {
	273	if (omap_rev() < OMAP3430_REV_ES3_0)
	274	return OMAPDSS_VER_OMAP34xx_ES1;
	275	else
	276	return OMAPDSS_VER_OMAP34xx_ES3;
	277	}
	278	} else if (omap_rev() == OMAP4430_REV_ES1_0)
	279	return OMAPDSS_VER_OMAP4430_ES1;
	280	else if (omap_rev() == OMAP4430_REV_ES2_0 \|\|
	281	omap_rev() == OMAP4430_REV_ES2_1 \|\|
	282	omap_rev() == OMAP4430_REV_ES2_2)
	283	return OMAPDSS_VER_OMAP4430_ES2;
	284	else if (cpu_is_omap44xx())
	285	return OMAPDSS_VER_OMAP4;
	286	else if (soc_is_omap54xx())
	287	return OMAPDSS_VER_OMAP5;
d6279d4a SP	288	else if (soc_is_am43xx())
d6279d4a SP	289	return OMAPDSS_VER_AM43xx;
403ee909 TV	290	else if (soc_is_dra7xx())
403ee909 TV	291	return OMAPDSS_VER_DRA7xx;
acd18af9 TV	292	else
	293	return OMAPDSS_VER_UNKNOWN;
	294	}
	295
b7ee79ab SS	296	int __init omap_display_init(struct omap_dss_board_info *board_data)
	297	{
	298	int r = 0;
3528c58e	299	struct platform_device *pdev;
179e0453	300	int i, oh_count;
179e0453	301	const struct omap_dss_hwmod_data *curr_dss_hwmod;
966eaed0	302	struct platform_device *dss_pdev;
acd18af9	303	enum omapdss_version ver;
cf07f531	304
00928eaf TV	305	/* create omapdss device */
00928eaf TV	306
acd18af9 TV	307	ver = omap_display_get_version();
	308
	309	if (ver == OMAPDSS_VER_UNKNOWN) {
	310	pr_err("DSS not supported on this SoC\n");
	311	return -ENODEV;
	312	}
	313
	314	board_data->version = ver;
00928eaf TV	315	board_data->dsi_enable_pads = omap_dsi_enable_pads;
00928eaf TV	316	board_data->dsi_disable_pads = omap_dsi_disable_pads;
00928eaf TV	317	board_data->set_min_bus_tput = omap_dss_set_min_bus_tput;
	318
	319	omap_display_device.dev.platform_data = board_data;
	320
	321	r = platform_device_register(&omap_display_device);
	322	if (r < 0) {
	323	pr_err("Unable to register omapdss device\n");
	324	return r;
	325	}
	326
	327	/* create devices for dss hwmods */
cf07f531	328
179e0453 AT	329	if (cpu_is_omap24xx()) {
	330	curr_dss_hwmod = omap2_dss_hwmod_data;
	331	oh_count = ARRAY_SIZE(omap2_dss_hwmod_data);
	332	} else if (cpu_is_omap34xx()) {
	333	curr_dss_hwmod = omap3_dss_hwmod_data;
	334	oh_count = ARRAY_SIZE(omap3_dss_hwmod_data);
	335	} else {
	336	curr_dss_hwmod = omap4_dss_hwmod_data;
	337	oh_count = ARRAY_SIZE(omap4_dss_hwmod_data);
	338	}
545376e7	339
966eaed0 TV	340	/*
	341	* First create the pdev for dss_core, which is used as a parent device
	342	* by the other dss pdevs. Note: dss_core has to be the first item in
	343	* the hwmod list.
	344	*/
	345	dss_pdev = create_dss_pdev(curr_dss_hwmod[0].dev_name,
	346	curr_dss_hwmod[0].id,
	347	curr_dss_hwmod[0].oh_name,
35deca3d	348	board_data, sizeof(*board_data),
966eaed0	349	NULL);
fd4b34f6	350
966eaed0 TV	351	if (IS_ERR(dss_pdev)) {
	352	pr_err("Could not build omap_device for %s\n",
	353	curr_dss_hwmod[0].oh_name);
	354
	355	return PTR_ERR(dss_pdev);
	356	}
	357
	358	for (i = 1; i < oh_count; i++) {
	359	pdev = create_dss_pdev(curr_dss_hwmod[i].dev_name,
	360	curr_dss_hwmod[i].id,
	361	curr_dss_hwmod[i].oh_name,
35deca3d	362	board_data, sizeof(*board_data),
966eaed0 TV	363	dss_pdev);
	364
	365	if (IS_ERR(pdev)) {
	366	pr_err("Could not build omap_device for %s\n",
	367	curr_dss_hwmod[i].oh_name);
cf07f531	368
966eaed0 TV	369	return PTR_ERR(pdev);
966eaed0 TV	370	}
cf07f531	371	}
b7ee79ab	372
53f576a8 TV	373	/* Create devices for DPI and SDI */
53f576a8 TV	374
35f5df6f	375	pdev = create_simple_dss_pdev("omapdss_dpi", 0,
35deca3d	376	board_data, sizeof(*board_data), dss_pdev);
53f576a8 TV	377	if (IS_ERR(pdev)) {
	378	pr_err("Could not build platform_device for omapdss_dpi\n");
	379	return PTR_ERR(pdev);
	380	}
	381
	382	if (cpu_is_omap34xx()) {
35f5df6f	383	pdev = create_simple_dss_pdev("omapdss_sdi", 0,
35deca3d	384	board_data, sizeof(*board_data), dss_pdev);
53f576a8 TV	385	if (IS_ERR(pdev)) {
	386	pr_err("Could not build platform_device for omapdss_sdi\n");
	387	return PTR_ERR(pdev);
	388	}
	389	}
	390
7a59743d AT	391	/* create DRM device */
	392	r = omap_init_drm();
	393	if (r < 0) {
	394	pr_err("Unable to register omapdrm device\n");
	395	return r;
	396	}
	397
fc8df752 AT	398	/* create vrfb device */
	399	r = omap_init_vrfb();
	400	if (r < 0) {
	401	pr_err("Unable to register omapvrfb device\n");
	402	return r;
	403	}
	404
	405	/* create FB device */
	406	r = omap_init_fb();
	407	if (r < 0) {
	408	pr_err("Unable to register omapfb device\n");
	409	return r;
	410	}
	411
576e5bda AT	412	/* create V4L2 display device */
	413	r = omap_init_vout();
	414	if (r < 0) {
	415	pr_err("Unable to register omap_vout device\n");
	416	return r;
	417	}
	418
00928eaf	419	return 0;
b7ee79ab	420	}
13662dc5	421
b923d40d AT	422	static void dispc_disable_outputs(void)
	423	{
	424	u32 v, irq_mask = 0;
465698ee	425	bool lcd_en, digit_en, lcd2_en = false, lcd3_en = false;
b923d40d AT	426	int i;
	427	struct omap_dss_dispc_dev_attr *da;
	428	struct omap_hwmod *oh;
	429
	430	oh = omap_hwmod_lookup("dss_dispc");
	431	if (!oh) {
	432	WARN(1, "display: could not disable outputs during reset - could not find dss_dispc hwmod\n");
	433	return;
	434	}
	435
	436	if (!oh->dev_attr) {
	437	pr_err("display: could not disable outputs during reset due to missing dev_attr\n");
	438	return;
	439	}
	440
	441	da = (struct omap_dss_dispc_dev_attr *)oh->dev_attr;
	442
	443	/* store value of LCDENABLE and DIGITENABLE bits */
	444	v = omap_hwmod_read(oh, DISPC_CONTROL);
	445	lcd_en = v & LCD_EN_MASK;
	446	digit_en = v & DIGIT_EN_MASK;
	447
	448	/* store value of LCDENABLE for LCD2 */
	449	if (da->manager_count > 2) {
	450	v = omap_hwmod_read(oh, DISPC_CONTROL2);
	451	lcd2_en = v & LCD_EN_MASK;
	452	}
	453
465698ee CM	454	/* store value of LCDENABLE for LCD3 */
	455	if (da->manager_count > 3) {
	456	v = omap_hwmod_read(oh, DISPC_CONTROL3);
	457	lcd3_en = v & LCD_EN_MASK;
	458	}
	459
	460	if (!(lcd_en \| digit_en \| lcd2_en \| lcd3_en))
b923d40d AT	461	return; /* no managers currently enabled */
	462
	463	/*
	464	* If any manager was enabled, we need to disable it before
	465	* DSS clocks are disabled or DISPC module is reset
	466	*/
	467	if (lcd_en)
	468	irq_mask \|= 1 << FRAMEDONE_IRQ_SHIFT;
	469
	470	if (digit_en) {
	471	if (da->has_framedonetv_irq) {
	472	irq_mask \|= 1 << FRAMEDONETV_IRQ_SHIFT;
	473	} else {
	474	irq_mask \|= 1 << EVSYNC_EVEN_IRQ_SHIFT \|
	475	1 << EVSYNC_ODD_IRQ_SHIFT;
	476	}
	477	}
	478
	479	if (lcd2_en)
	480	irq_mask \|= 1 << FRAMEDONE2_IRQ_SHIFT;
465698ee CM	481	if (lcd3_en)
465698ee CM	482	irq_mask \|= 1 << FRAMEDONE3_IRQ_SHIFT;
b923d40d AT	483
	484	/*
	485	* clear any previous FRAMEDONE, FRAMEDONETV,
465698ee	486	* EVSYNC_EVEN/ODD, FRAMEDONE2 or FRAMEDONE3 interrupts
b923d40d AT	487	*/
	488	omap_hwmod_write(irq_mask, oh, DISPC_IRQSTATUS);
	489
	490	/* disable LCD and TV managers */
	491	v = omap_hwmod_read(oh, DISPC_CONTROL);
	492	v &= ~(LCD_EN_MASK \| DIGIT_EN_MASK);
	493	omap_hwmod_write(v, oh, DISPC_CONTROL);
	494
	495	/* disable LCD2 manager */
	496	if (da->manager_count > 2) {
	497	v = omap_hwmod_read(oh, DISPC_CONTROL2);
	498	v &= ~LCD_EN_MASK;
	499	omap_hwmod_write(v, oh, DISPC_CONTROL2);
	500	}
	501
465698ee CM	502	/* disable LCD3 manager */
	503	if (da->manager_count > 3) {
	504	v = omap_hwmod_read(oh, DISPC_CONTROL3);
	505	v &= ~LCD_EN_MASK;
	506	omap_hwmod_write(v, oh, DISPC_CONTROL3);
	507	}
	508
b923d40d AT	509	i = 0;
	510	while ((omap_hwmod_read(oh, DISPC_IRQSTATUS) & irq_mask) !=
	511	irq_mask) {
	512	i++;
	513	if (i > FRAMEDONE_IRQ_TIMEOUT) {
465698ee	514	pr_err("didn't get FRAMEDONE1/2/3 or TV interrupt\n");
b923d40d AT	515	break;
	516	}
	517	mdelay(1);
	518	}
	519	}
	520
13662dc5 TV	521	int omap_dss_reset(struct omap_hwmod *oh)
	522	{
	523	struct omap_hwmod_opt_clk *oc;
	524	int c = 0;
	525	int i, r;
	526
	527	if (!(oh->class->sysc->sysc_flags & SYSS_HAS_RESET_STATUS)) {
	528	pr_err("dss_core: hwmod data doesn't contain reset data\n");
	529	return -EINVAL;
	530	}
	531
	532	for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++)
	533	if (oc->_clk)
4d7cb45e	534	clk_prepare_enable(oc->_clk);
13662dc5	535
b923d40d AT	536	dispc_disable_outputs();
	537
	538	/* clear SDI registers */
	539	if (cpu_is_omap3430()) {
	540	omap_hwmod_write(0x0, oh, DSS_SDI_CONTROL);
	541	omap_hwmod_write(0x0, oh, DSS_PLL_CONTROL);
	542	}
	543
	544	/*
	545	* clear DSS_CONTROL register to switch DSS clock sources to
	546	* PRCM clock, if any
	547	*/
	548	omap_hwmod_write(0x0, oh, DSS_CONTROL);
	549
13662dc5 TV	550	omap_test_timeout((omap_hwmod_read(oh, oh->class->sysc->syss_offs)
	551	& SYSS_RESETDONE_MASK),
	552	MAX_MODULE_SOFTRESET_WAIT, c);
	553
	554	if (c == MAX_MODULE_SOFTRESET_WAIT)
3d0cb73e	555	pr_warn("dss_core: waiting for reset to finish failed\n");
13662dc5 TV	556	else
	557	pr_debug("dss_core: softreset done\n");
	558
	559	for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++)
	560	if (oc->_clk)
4d7cb45e	561	clk_disable_unprepare(oc->_clk);
13662dc5 TV	562
	563	r = (c == MAX_MODULE_SOFTRESET_WAIT) ? -ETIMEDOUT : 0;
	564
	565	return r;
	566	}
dcdf407b	567
6a0e6b38 TV	568	void __init omapdss_early_init_of(void)
6a0e6b38 TV	569	{
6a0e6b38	570
6a0e6b38 TV	571	}
6a0e6b38 TV	572
5b5992ac TV	573	static const char * const omapdss_compat_names[] __initconst = {
	574	"ti,omap2-dss",
	575	"ti,omap3-dss",
	576	"ti,omap4-dss",
	577	"ti,omap5-dss",
403ee909	578	"ti,dra7-dss",
5b5992ac TV	579	};
5b5992ac TV	580
dcdf407b TV	581	struct device_node * __init omapdss_find_dss_of_node(void)
	582	{
	583	struct device_node *node;
5b5992ac	584	int i;
dcdf407b	585
5b5992ac TV	586	for (i = 0; i < ARRAY_SIZE(omapdss_compat_names); ++i) {
	587	node = of_find_compatible_node(NULL, NULL,
	588	omapdss_compat_names[i]);
	589	if (node)
	590	return node;
	591	}
9a308948	592
dcdf407b TV	593	return NULL;
	594	}
	595
	596	int __init omapdss_init_of(void)
	597	{
	598	int r;
	599	enum omapdss_version ver;
	600	struct device_node *node;
	601	struct platform_device *pdev;
	602
	603	static struct omap_dss_board_info board_data = {
	604	.dsi_enable_pads = omap_dsi_enable_pads,
	605	.dsi_disable_pads = omap_dsi_disable_pads,
dcdf407b TV	606	.set_min_bus_tput = omap_dss_set_min_bus_tput,
	607	};
	608
	609	/* only create dss helper devices if dss is enabled in the .dts */
	610
	611	node = omapdss_find_dss_of_node();
	612	if (!node)
	613	return 0;
	614
	615	if (!of_device_is_available(node))
	616	return 0;
	617
	618	ver = omap_display_get_version();
	619
	620	if (ver == OMAPDSS_VER_UNKNOWN) {
	621	pr_err("DSS not supported on this SoC\n");
	622	return -ENODEV;
	623	}
	624
	625	pdev = of_find_device_by_node(node);
	626
	627	if (!pdev) {
	628	pr_err("Unable to find DSS platform device\n");
	629	return -ENODEV;
	630	}
	631
	632	r = of_platform_populate(node, NULL, NULL, &pdev->dev);
	633	if (r) {
	634	pr_err("Unable to populate DSS submodule devices\n");
	635	return r;
	636	}
	637
	638	board_data.version = ver;
	639
	640	omap_display_device.dev.platform_data = &board_data;
	641
	642	r = platform_device_register(&omap_display_device);
	643	if (r < 0) {
	644	pr_err("Unable to register omapdss device\n");
	645	return r;
	646	}
	647
	648	/* create DRM device */
	649	r = omap_init_drm();
	650	if (r < 0) {
	651	pr_err("Unable to register omapdrm device\n");
	652	return r;
	653	}
	654
	655	/* create vrfb device */
	656	r = omap_init_vrfb();
	657	if (r < 0) {
	658	pr_err("Unable to register omapvrfb device\n");
	659	return r;
	660	}
	661
	662	/* create FB device */
	663	r = omap_init_fb();
	664	if (r < 0) {
	665	pr_err("Unable to register omapfb device\n");
	666	return r;
	667	}
	668
	669	/* create V4L2 display device */
670	r = omap_init_vout();
671	if (r < 0) {
672	pr_err("Unable to register omap_vout device\n");
673	return r;
674	}
675
23d34981 TK	676	/* add DSI info for omap4 */
	677	node = of_find_node_by_name(NULL, "omap4_padconf_global");
	678	if (node)
	679	omap4_dsi_mux_syscon = syscon_node_to_regmap(node);
	680
dcdf407b TV	681	return 0;
dcdf407b TV	682	}