[deliverable/linux.git] / arch / arm / mach-omap2 / display.c

/*
 * OMAP2plus display device setup / initialization.
 *
 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
 *	Senthilvadivu Guruswamy
 *	Sumit Semwal
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
 * kind, whether express or implied; without even the implied warranty
 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <linux/string.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/io.h>
#include <linux/clk.h>
#include <linux/err.h>
#include <linux/delay.h>

#include <video/omapdss.h>
#include <plat/omap_hwmod.h>
#include <plat/omap_device.h>
#include <plat/omap-pm.h>
#include "common.h"

#include "iomap.h"
#include "mux.h"
#include "control.h"
#include "display.h"

#define DISPC_CONTROL		0x0040
#define DISPC_CONTROL2		0x0238
#define DISPC_CONTROL3		0x0848
#define DISPC_IRQSTATUS		0x0018

#define DSS_SYSCONFIG		0x10
#define DSS_SYSSTATUS		0x14
#define DSS_CONTROL		0x40
#define DSS_SDI_CONTROL		0x44
#define DSS_PLL_CONTROL		0x48

#define LCD_EN_MASK		(0x1 << 0)
#define DIGIT_EN_MASK		(0x1 << 1)

#define FRAMEDONE_IRQ_SHIFT	0
#define EVSYNC_EVEN_IRQ_SHIFT	2
#define EVSYNC_ODD_IRQ_SHIFT	3
#define FRAMEDONE2_IRQ_SHIFT	22
#define FRAMEDONE3_IRQ_SHIFT	30
#define FRAMEDONETV_IRQ_SHIFT	24

/*
 * FRAMEDONE_IRQ_TIMEOUT: how long (in milliseconds) to wait during DISPC
 *     reset before deciding that something has gone wrong
 */
#define FRAMEDONE_IRQ_TIMEOUT		100

static struct platform_device omap_display_device = {
	.name          = "omapdss",
	.id            = -1,
	.dev            = {
		.platform_data = NULL,
	},
};

struct omap_dss_hwmod_data {
	const char *oh_name;
	const char *dev_name;
	const int id;
};

static const struct omap_dss_hwmod_data omap2_dss_hwmod_data[] __initdata = {
	{ "dss_core", "omapdss_dss", -1 },
	{ "dss_dispc", "omapdss_dispc", -1 },
	{ "dss_rfbi", "omapdss_rfbi", -1 },
	{ "dss_venc", "omapdss_venc", -1 },
};

static const struct omap_dss_hwmod_data omap3_dss_hwmod_data[] __initdata = {
	{ "dss_core", "omapdss_dss", -1 },
	{ "dss_dispc", "omapdss_dispc", -1 },
	{ "dss_rfbi", "omapdss_rfbi", -1 },
	{ "dss_venc", "omapdss_venc", -1 },
	{ "dss_dsi1", "omapdss_dsi", 0 },
};

static const struct omap_dss_hwmod_data omap4_dss_hwmod_data[] __initdata = {
	{ "dss_core", "omapdss_dss", -1 },
	{ "dss_dispc", "omapdss_dispc", -1 },
	{ "dss_rfbi", "omapdss_rfbi", -1 },
	{ "dss_venc", "omapdss_venc", -1 },
	{ "dss_dsi1", "omapdss_dsi", 0 },
	{ "dss_dsi2", "omapdss_dsi", 1 },
	{ "dss_hdmi", "omapdss_hdmi", -1 },
};

static void __init omap4_hdmi_mux_pads(enum omap_hdmi_flags flags)
{
	u32 reg;
	u16 control_i2c_1;

	omap_mux_init_signal("hdmi_cec",
			OMAP_PIN_INPUT_PULLUP);
	omap_mux_init_signal("hdmi_ddc_scl",
			OMAP_PIN_INPUT_PULLUP);
	omap_mux_init_signal("hdmi_ddc_sda",
			OMAP_PIN_INPUT_PULLUP);

	/*
	 * CONTROL_I2C_1: HDMI_DDC_SDA_PULLUPRESX (bit 28) and
	 * HDMI_DDC_SCL_PULLUPRESX (bit 24) are set to disable
	 * internal pull up resistor.
	 */
	if (flags & OMAP_HDMI_SDA_SCL_EXTERNAL_PULLUP) {
		control_i2c_1 = OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_I2C_1;
		reg = omap4_ctrl_pad_readl(control_i2c_1);
		reg |= (OMAP4_HDMI_DDC_SDA_PULLUPRESX_MASK |
			OMAP4_HDMI_DDC_SCL_PULLUPRESX_MASK);
			omap4_ctrl_pad_writel(reg, control_i2c_1);
	}
}

static int omap4_dsi_mux_pads(int dsi_id, unsigned lanes)
{
	u32 enable_mask, enable_shift;
	u32 pipd_mask, pipd_shift;
	u32 reg;

	if (dsi_id == 0) {
		enable_mask = OMAP4_DSI1_LANEENABLE_MASK;
		enable_shift = OMAP4_DSI1_LANEENABLE_SHIFT;
		pipd_mask = OMAP4_DSI1_PIPD_MASK;
		pipd_shift = OMAP4_DSI1_PIPD_SHIFT;
	} else if (dsi_id == 1) {
		enable_mask = OMAP4_DSI2_LANEENABLE_MASK;
		enable_shift = OMAP4_DSI2_LANEENABLE_SHIFT;
		pipd_mask = OMAP4_DSI2_PIPD_MASK;
		pipd_shift = OMAP4_DSI2_PIPD_SHIFT;
	} else {
		return -ENODEV;
	}

	reg = omap4_ctrl_pad_readl(OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_DSIPHY);

	reg &= ~enable_mask;
	reg &= ~pipd_mask;

	reg |= (lanes << enable_shift) & enable_mask;
	reg |= (lanes << pipd_shift) & pipd_mask;

	omap4_ctrl_pad_writel(reg, OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_DSIPHY);

	return 0;
}

int __init omap_hdmi_init(enum omap_hdmi_flags flags)
{
	if (cpu_is_omap44xx())
		omap4_hdmi_mux_pads(flags);

	return 0;
}

static int omap_dsi_enable_pads(int dsi_id, unsigned lane_mask)
{
	if (cpu_is_omap44xx())
		return omap4_dsi_mux_pads(dsi_id, lane_mask);

	return 0;
}

static void omap_dsi_disable_pads(int dsi_id, unsigned lane_mask)
{
	if (cpu_is_omap44xx())
		omap4_dsi_mux_pads(dsi_id, 0);
}

static int omap_dss_set_min_bus_tput(struct device *dev, unsigned long tput)
{
	return omap_pm_set_min_bus_tput(dev, OCP_INITIATOR_AGENT, tput);
}

static struct platform_device *create_dss_pdev(const char *pdev_name,
		int pdev_id, const char *oh_name, void *pdata, int pdata_len,
		struct platform_device *parent)
{
	struct platform_device *pdev;
	struct omap_device *od;
	struct omap_hwmod *ohs[1];
	struct omap_hwmod *oh;
	int r;

	oh = omap_hwmod_lookup(oh_name);
	if (!oh) {
		pr_err("Could not look up %s\n", oh_name);
		r = -ENODEV;
		goto err;
	}

	pdev = platform_device_alloc(pdev_name, pdev_id);
	if (!pdev) {
		pr_err("Could not create pdev for %s\n", pdev_name);
		r = -ENOMEM;
		goto err;
	}

	if (parent != NULL)
		pdev->dev.parent = &parent->dev;

	if (pdev->id != -1)
		dev_set_name(&pdev->dev, "%s.%d", pdev->name, pdev->id);
	else
		dev_set_name(&pdev->dev, "%s", pdev->name);

	ohs[0] = oh;
	od = omap_device_alloc(pdev, ohs, 1, NULL, 0);
	if (!od) {
		pr_err("Could not alloc omap_device for %s\n", pdev_name);
		r = -ENOMEM;
		goto err;
	}

	r = platform_device_add_data(pdev, pdata, pdata_len);
	if (r) {
		pr_err("Could not set pdata for %s\n", pdev_name);
		goto err;
	}

	r = omap_device_register(pdev);
	if (r) {
		pr_err("Could not register omap_device for %s\n", pdev_name);
		goto err;
	}

	return pdev;

err:
	return ERR_PTR(r);
}

static struct platform_device *create_simple_dss_pdev(const char *pdev_name,
		int pdev_id, void *pdata, int pdata_len,
		struct platform_device *parent)
{
	struct platform_device *pdev;
	int r;

	pdev = platform_device_alloc(pdev_name, pdev_id);
	if (!pdev) {
		pr_err("Could not create pdev for %s\n", pdev_name);
		r = -ENOMEM;
		goto err;
	}

	if (parent != NULL)
		pdev->dev.parent = &parent->dev;

	if (pdev->id != -1)
		dev_set_name(&pdev->dev, "%s.%d", pdev->name, pdev->id);
	else
		dev_set_name(&pdev->dev, "%s", pdev->name);

	r = platform_device_add_data(pdev, pdata, pdata_len);
	if (r) {
		pr_err("Could not set pdata for %s\n", pdev_name);
		goto err;
	}

	r = platform_device_add(pdev);
	if (r) {
		pr_err("Could not register platform_device for %s\n", pdev_name);
		goto err;
	}

	return pdev;

err:
	return ERR_PTR(r);
}

int __init omap_display_init(struct omap_dss_board_info *board_data)
{
	int r = 0;
	struct platform_device *pdev;
	int i, oh_count;
	const struct omap_dss_hwmod_data *curr_dss_hwmod;
	struct platform_device *dss_pdev;

	/* create omapdss device */

	board_data->dsi_enable_pads = omap_dsi_enable_pads;
	board_data->dsi_disable_pads = omap_dsi_disable_pads;
	board_data->get_context_loss_count = omap_pm_get_dev_context_loss_count;
	board_data->set_min_bus_tput = omap_dss_set_min_bus_tput;

	omap_display_device.dev.platform_data = board_data;

	r = platform_device_register(&omap_display_device);
	if (r < 0) {
		pr_err("Unable to register omapdss device\n");
		return r;
	}

	/* create devices for dss hwmods */

	if (cpu_is_omap24xx()) {
		curr_dss_hwmod = omap2_dss_hwmod_data;
		oh_count = ARRAY_SIZE(omap2_dss_hwmod_data);
	} else if (cpu_is_omap34xx()) {
		curr_dss_hwmod = omap3_dss_hwmod_data;
		oh_count = ARRAY_SIZE(omap3_dss_hwmod_data);
	} else {
		curr_dss_hwmod = omap4_dss_hwmod_data;
		oh_count = ARRAY_SIZE(omap4_dss_hwmod_data);
	}

	/*
	 * First create the pdev for dss_core, which is used as a parent device
	 * by the other dss pdevs. Note: dss_core has to be the first item in
	 * the hwmod list.
	 */
	dss_pdev = create_dss_pdev(curr_dss_hwmod[0].dev_name,
			curr_dss_hwmod[0].id,
			curr_dss_hwmod[0].oh_name,
			board_data, sizeof(*board_data),
			NULL);

	if (IS_ERR(dss_pdev)) {
		pr_err("Could not build omap_device for %s\n",
				curr_dss_hwmod[0].oh_name);

		return PTR_ERR(dss_pdev);
	}

	for (i = 1; i < oh_count; i++) {
		pdev = create_dss_pdev(curr_dss_hwmod[i].dev_name,
				curr_dss_hwmod[i].id,
				curr_dss_hwmod[i].oh_name,
				board_data, sizeof(*board_data),
				dss_pdev);

		if (IS_ERR(pdev)) {
			pr_err("Could not build omap_device for %s\n",
					curr_dss_hwmod[i].oh_name);

			return PTR_ERR(pdev);
		}
	}

	/* Create devices for DPI and SDI */

	pdev = create_simple_dss_pdev("omapdss_dpi", -1,
			board_data, sizeof(*board_data), dss_pdev);
	if (IS_ERR(pdev)) {
		pr_err("Could not build platform_device for omapdss_dpi\n");
		return PTR_ERR(pdev);
	}

	if (cpu_is_omap34xx()) {
		pdev = create_simple_dss_pdev("omapdss_sdi", -1,
				board_data, sizeof(*board_data), dss_pdev);
		if (IS_ERR(pdev)) {
			pr_err("Could not build platform_device for omapdss_sdi\n");
			return PTR_ERR(pdev);
		}
	}

	return 0;
}

static void dispc_disable_outputs(void)
{
	u32 v, irq_mask = 0;
	bool lcd_en, digit_en, lcd2_en = false, lcd3_en = false;
	int i;
	struct omap_dss_dispc_dev_attr *da;
	struct omap_hwmod *oh;

	oh = omap_hwmod_lookup("dss_dispc");
	if (!oh) {
		WARN(1, "display: could not disable outputs during reset - could not find dss_dispc hwmod\n");
		return;
	}

	if (!oh->dev_attr) {
		pr_err("display: could not disable outputs during reset due to missing dev_attr\n");
		return;
	}

	da = (struct omap_dss_dispc_dev_attr *)oh->dev_attr;

	/* store value of LCDENABLE and DIGITENABLE bits */
	v = omap_hwmod_read(oh, DISPC_CONTROL);
	lcd_en = v & LCD_EN_MASK;
	digit_en = v & DIGIT_EN_MASK;

	/* store value of LCDENABLE for LCD2 */
	if (da->manager_count > 2) {
		v = omap_hwmod_read(oh, DISPC_CONTROL2);
		lcd2_en = v & LCD_EN_MASK;
	}

	/* store value of LCDENABLE for LCD3 */
	if (da->manager_count > 3) {
		v = omap_hwmod_read(oh, DISPC_CONTROL3);
		lcd3_en = v & LCD_EN_MASK;
	}

	if (!(lcd_en | digit_en | lcd2_en | lcd3_en))
		return; /* no managers currently enabled */

	/*
	 * If any manager was enabled, we need to disable it before
	 * DSS clocks are disabled or DISPC module is reset
	 */
	if (lcd_en)
		irq_mask |= 1 << FRAMEDONE_IRQ_SHIFT;

	if (digit_en) {
		if (da->has_framedonetv_irq) {
			irq_mask |= 1 << FRAMEDONETV_IRQ_SHIFT;
		} else {
			irq_mask |= 1 << EVSYNC_EVEN_IRQ_SHIFT |
				1 << EVSYNC_ODD_IRQ_SHIFT;
		}
	}

	if (lcd2_en)
		irq_mask |= 1 << FRAMEDONE2_IRQ_SHIFT;
	if (lcd3_en)
		irq_mask |= 1 << FRAMEDONE3_IRQ_SHIFT;

	/*
	 * clear any previous FRAMEDONE, FRAMEDONETV,
	 * EVSYNC_EVEN/ODD, FRAMEDONE2 or FRAMEDONE3 interrupts
	 */
	omap_hwmod_write(irq_mask, oh, DISPC_IRQSTATUS);

	/* disable LCD and TV managers */
	v = omap_hwmod_read(oh, DISPC_CONTROL);
	v &= ~(LCD_EN_MASK | DIGIT_EN_MASK);
	omap_hwmod_write(v, oh, DISPC_CONTROL);

	/* disable LCD2 manager */
	if (da->manager_count > 2) {
		v = omap_hwmod_read(oh, DISPC_CONTROL2);
		v &= ~LCD_EN_MASK;
		omap_hwmod_write(v, oh, DISPC_CONTROL2);
	}

	/* disable LCD3 manager */
	if (da->manager_count > 3) {
		v = omap_hwmod_read(oh, DISPC_CONTROL3);
		v &= ~LCD_EN_MASK;
		omap_hwmod_write(v, oh, DISPC_CONTROL3);
	}

	i = 0;
	while ((omap_hwmod_read(oh, DISPC_IRQSTATUS) & irq_mask) !=
	       irq_mask) {
		i++;
		if (i > FRAMEDONE_IRQ_TIMEOUT) {
			pr_err("didn't get FRAMEDONE1/2/3 or TV interrupt\n");
			break;
		}
		mdelay(1);
	}
}

#define MAX_MODULE_SOFTRESET_WAIT	10000
int omap_dss_reset(struct omap_hwmod *oh)
{
	struct omap_hwmod_opt_clk *oc;
	int c = 0;
	int i, r;

	if (!(oh->class->sysc->sysc_flags & SYSS_HAS_RESET_STATUS)) {
		pr_err("dss_core: hwmod data doesn't contain reset data\n");
		return -EINVAL;
	}

	for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++)
		if (oc->_clk)
			clk_enable(oc->_clk);

	dispc_disable_outputs();

	/* clear SDI registers */
	if (cpu_is_omap3430()) {
		omap_hwmod_write(0x0, oh, DSS_SDI_CONTROL);
		omap_hwmod_write(0x0, oh, DSS_PLL_CONTROL);
	}

	/*
	 * clear DSS_CONTROL register to switch DSS clock sources to
	 * PRCM clock, if any
	 */
	omap_hwmod_write(0x0, oh, DSS_CONTROL);

	omap_test_timeout((omap_hwmod_read(oh, oh->class->sysc->syss_offs)
				& SYSS_RESETDONE_MASK),
			MAX_MODULE_SOFTRESET_WAIT, c);

	if (c == MAX_MODULE_SOFTRESET_WAIT)
		pr_warning("dss_core: waiting for reset to finish failed\n");
	else
		pr_debug("dss_core: softreset done\n");

	for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++)
		if (oc->_clk)
			clk_disable(oc->_clk);

	r = (c == MAX_MODULE_SOFTRESET_WAIT) ? -ETIMEDOUT : 0;

	return r;
}
Commit	Line	Data
b7ee79ab SS	1	/*
	2	* OMAP2plus display device setup / initialization.
	3	*
	4	* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
	5	* Senthilvadivu Guruswamy
	6	* Sumit Semwal
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License version 2 as
	10	* published by the Free Software Foundation.
	11	*
	12	* This program is distributed "as is" WITHOUT ANY WARRANTY of any
	13	* kind, whether express or implied; without even the implied warranty
	14	* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*/
	17
d44b28c4	18	#include <linux/string.h>
b7ee79ab SS	19	#include <linux/kernel.h>
	20	#include <linux/init.h>
	21	#include <linux/platform_device.h>
	22	#include <linux/io.h>
	23	#include <linux/clk.h>
	24	#include <linux/err.h>
deee6d53	25	#include <linux/delay.h>
b7ee79ab	26
a0b38cc4	27	#include <video/omapdss.h>
cf07f531 SG	28	#include <plat/omap_hwmod.h>
cf07f531 SG	29	#include <plat/omap_device.h>
700dee78	30	#include <plat/omap-pm.h>
deee6d53	31	#include "common.h"
b7ee79ab	32
ee0839c2	33	#include "iomap.h"
ee9dfd82	34	#include "mux.h"
dc35835c	35	#include "control.h"
b923d40d AT	36	#include "display.h"
	37
	38	#define DISPC_CONTROL 0x0040
	39	#define DISPC_CONTROL2 0x0238
465698ee	40	#define DISPC_CONTROL3 0x0848
b923d40d AT	41	#define DISPC_IRQSTATUS 0x0018
	42
	43	#define DSS_SYSCONFIG 0x10
	44	#define DSS_SYSSTATUS 0x14
	45	#define DSS_CONTROL 0x40
	46	#define DSS_SDI_CONTROL 0x44
	47	#define DSS_PLL_CONTROL 0x48
	48
	49	#define LCD_EN_MASK (0x1 << 0)
	50	#define DIGIT_EN_MASK (0x1 << 1)
	51
	52	#define FRAMEDONE_IRQ_SHIFT 0
	53	#define EVSYNC_EVEN_IRQ_SHIFT 2
	54	#define EVSYNC_ODD_IRQ_SHIFT 3
	55	#define FRAMEDONE2_IRQ_SHIFT 22
465698ee	56	#define FRAMEDONE3_IRQ_SHIFT 30
b923d40d AT	57	#define FRAMEDONETV_IRQ_SHIFT 24
	58
	59	/*
	60	* FRAMEDONE_IRQ_TIMEOUT: how long (in milliseconds) to wait during DISPC
	61	* reset before deciding that something has gone wrong
	62	*/
	63	#define FRAMEDONE_IRQ_TIMEOUT 100
dc35835c	64
b7ee79ab SS	65	static struct platform_device omap_display_device = {
	66	.name = "omapdss",
	67	.id = -1,
	68	.dev = {
	69	.platform_data = NULL,
	70	},
	71	};
	72
179e0453 AT	73	struct omap_dss_hwmod_data {
	74	const char *oh_name;
	75	const char *dev_name;
	76	const int id;
	77	};
	78
	79	static const struct omap_dss_hwmod_data omap2_dss_hwmod_data[] __initdata = {
	80	{ "dss_core", "omapdss_dss", -1 },
	81	{ "dss_dispc", "omapdss_dispc", -1 },
	82	{ "dss_rfbi", "omapdss_rfbi", -1 },
	83	{ "dss_venc", "omapdss_venc", -1 },
	84	};
	85
	86	static const struct omap_dss_hwmod_data omap3_dss_hwmod_data[] __initdata = {
	87	{ "dss_core", "omapdss_dss", -1 },
	88	{ "dss_dispc", "omapdss_dispc", -1 },
	89	{ "dss_rfbi", "omapdss_rfbi", -1 },
	90	{ "dss_venc", "omapdss_venc", -1 },
7c68dd96	91	{ "dss_dsi1", "omapdss_dsi", 0 },
179e0453 AT	92	};
	93
	94	static const struct omap_dss_hwmod_data omap4_dss_hwmod_data[] __initdata = {
	95	{ "dss_core", "omapdss_dss", -1 },
	96	{ "dss_dispc", "omapdss_dispc", -1 },
	97	{ "dss_rfbi", "omapdss_rfbi", -1 },
	98	{ "dss_venc", "omapdss_venc", -1 },
7c68dd96 TV	99	{ "dss_dsi1", "omapdss_dsi", 0 },
7c68dd96 TV	100	{ "dss_dsi2", "omapdss_dsi", 1 },
179e0453 AT	101	{ "dss_hdmi", "omapdss_hdmi", -1 },
	102	};
	103
e8a30b25	104	static void __init omap4_hdmi_mux_pads(enum omap_hdmi_flags flags)
ee9dfd82	105	{
9a901683 M	106	u32 reg;
	107	u16 control_i2c_1;
	108
ee9dfd82 M	109	omap_mux_init_signal("hdmi_cec",
ee9dfd82 M	110	OMAP_PIN_INPUT_PULLUP);
ee9dfd82 M	111	omap_mux_init_signal("hdmi_ddc_scl",
	112	OMAP_PIN_INPUT_PULLUP);
	113	omap_mux_init_signal("hdmi_ddc_sda",
	114	OMAP_PIN_INPUT_PULLUP);
9a901683 M	115
	116	/*
	117	* CONTROL_I2C_1: HDMI_DDC_SDA_PULLUPRESX (bit 28) and
	118	* HDMI_DDC_SCL_PULLUPRESX (bit 24) are set to disable
	119	* internal pull up resistor.
	120	*/
	121	if (flags & OMAP_HDMI_SDA_SCL_EXTERNAL_PULLUP) {
	122	control_i2c_1 = OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_I2C_1;
	123	reg = omap4_ctrl_pad_readl(control_i2c_1);
	124	reg \|= (OMAP4_HDMI_DDC_SDA_PULLUPRESX_MASK \|
	125	OMAP4_HDMI_DDC_SCL_PULLUPRESX_MASK);
	126	omap4_ctrl_pad_writel(reg, control_i2c_1);
	127	}
ee9dfd82 M	128	}
ee9dfd82 M	129
e8a30b25	130	static int omap4_dsi_mux_pads(int dsi_id, unsigned lanes)
dc35835c TV	131	{
	132	u32 enable_mask, enable_shift;
	133	u32 pipd_mask, pipd_shift;
	134	u32 reg;
	135
	136	if (dsi_id == 0) {
	137	enable_mask = OMAP4_DSI1_LANEENABLE_MASK;
	138	enable_shift = OMAP4_DSI1_LANEENABLE_SHIFT;
	139	pipd_mask = OMAP4_DSI1_PIPD_MASK;
	140	pipd_shift = OMAP4_DSI1_PIPD_SHIFT;
	141	} else if (dsi_id == 1) {
	142	enable_mask = OMAP4_DSI2_LANEENABLE_MASK;
	143	enable_shift = OMAP4_DSI2_LANEENABLE_SHIFT;
	144	pipd_mask = OMAP4_DSI2_PIPD_MASK;
	145	pipd_shift = OMAP4_DSI2_PIPD_SHIFT;
	146	} else {
	147	return -ENODEV;
	148	}
	149
	150	reg = omap4_ctrl_pad_readl(OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_DSIPHY);
	151
	152	reg &= ~enable_mask;
	153	reg &= ~pipd_mask;
	154
	155	reg \|= (lanes << enable_shift) & enable_mask;
	156	reg \|= (lanes << pipd_shift) & pipd_mask;
	157
	158	omap4_ctrl_pad_writel(reg, OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_DSIPHY);
	159
	160	return 0;
	161	}
	162
d1589f09	163	int __init omap_hdmi_init(enum omap_hdmi_flags flags)
ee9dfd82 M	164	{
ee9dfd82 M	165	if (cpu_is_omap44xx())
9a901683	166	omap4_hdmi_mux_pads(flags);
ee9dfd82 M	167
	168	return 0;
	169	}
	170
e8a30b25	171	static int omap_dsi_enable_pads(int dsi_id, unsigned lane_mask)
5bc416cb	172	{
dc35835c TV	173	if (cpu_is_omap44xx())
	174	return omap4_dsi_mux_pads(dsi_id, lane_mask);
	175
5bc416cb TV	176	return 0;
	177	}
	178
e8a30b25	179	static void omap_dsi_disable_pads(int dsi_id, unsigned lane_mask)
5bc416cb	180	{
dc35835c TV	181	if (cpu_is_omap44xx())
dc35835c TV	182	omap4_dsi_mux_pads(dsi_id, 0);
5bc416cb TV	183	}
5bc416cb TV	184
62c1dcfc TV	185	static int omap_dss_set_min_bus_tput(struct device *dev, unsigned long tput)
	186	{
	187	return omap_pm_set_min_bus_tput(dev, OCP_INITIATOR_AGENT, tput);
	188	}
	189
966eaed0 TV	190	static struct platform_device create_dss_pdev(const char pdev_name,
	191	int pdev_id, const char oh_name, void pdata, int pdata_len,
	192	struct platform_device *parent)
	193	{
	194	struct platform_device *pdev;
	195	struct omap_device *od;
	196	struct omap_hwmod *ohs[1];
	197	struct omap_hwmod *oh;
	198	int r;
	199
	200	oh = omap_hwmod_lookup(oh_name);
	201	if (!oh) {
	202	pr_err("Could not look up %s\n", oh_name);
	203	r = -ENODEV;
	204	goto err;
	205	}
	206
	207	pdev = platform_device_alloc(pdev_name, pdev_id);
	208	if (!pdev) {
	209	pr_err("Could not create pdev for %s\n", pdev_name);
	210	r = -ENOMEM;
	211	goto err;
	212	}
	213
	214	if (parent != NULL)
	215	pdev->dev.parent = &parent->dev;
	216
	217	if (pdev->id != -1)
	218	dev_set_name(&pdev->dev, "%s.%d", pdev->name, pdev->id);
	219	else
	220	dev_set_name(&pdev->dev, "%s", pdev->name);
	221
	222	ohs[0] = oh;
	223	od = omap_device_alloc(pdev, ohs, 1, NULL, 0);
	224	if (!od) {
	225	pr_err("Could not alloc omap_device for %s\n", pdev_name);
	226	r = -ENOMEM;
	227	goto err;
	228	}
	229
	230	r = platform_device_add_data(pdev, pdata, pdata_len);
	231	if (r) {
	232	pr_err("Could not set pdata for %s\n", pdev_name);
	233	goto err;
	234	}
	235
	236	r = omap_device_register(pdev);
	237	if (r) {
	238	pr_err("Could not register omap_device for %s\n", pdev_name);
	239	goto err;
	240	}
	241
	242	return pdev;
	243
	244	err:
	245	return ERR_PTR(r);
	246	}
	247
53f576a8 TV	248	static struct platform_device create_simple_dss_pdev(const char pdev_name,
	249	int pdev_id, void *pdata, int pdata_len,
	250	struct platform_device *parent)
	251	{
	252	struct platform_device *pdev;
	253	int r;
	254
	255	pdev = platform_device_alloc(pdev_name, pdev_id);
	256	if (!pdev) {
	257	pr_err("Could not create pdev for %s\n", pdev_name);
	258	r = -ENOMEM;
	259	goto err;
	260	}
	261
	262	if (parent != NULL)
	263	pdev->dev.parent = &parent->dev;
	264
	265	if (pdev->id != -1)
	266	dev_set_name(&pdev->dev, "%s.%d", pdev->name, pdev->id);
	267	else
	268	dev_set_name(&pdev->dev, "%s", pdev->name);
	269
	270	r = platform_device_add_data(pdev, pdata, pdata_len);
	271	if (r) {
	272	pr_err("Could not set pdata for %s\n", pdev_name);
	273	goto err;
	274	}
	275
c3a21fc7	276	r = platform_device_add(pdev);
53f576a8	277	if (r) {
c3a21fc7	278	pr_err("Could not register platform_device for %s\n", pdev_name);
53f576a8 TV	279	goto err;
	280	}
	281
	282	return pdev;
	283
	284	err:
	285	return ERR_PTR(r);
	286	}
	287
b7ee79ab SS	288	int __init omap_display_init(struct omap_dss_board_info *board_data)
	289	{
	290	int r = 0;
3528c58e	291	struct platform_device *pdev;
179e0453	292	int i, oh_count;
179e0453	293	const struct omap_dss_hwmod_data *curr_dss_hwmod;
966eaed0	294	struct platform_device *dss_pdev;
cf07f531	295
00928eaf TV	296	/* create omapdss device */
	297
	298	board_data->dsi_enable_pads = omap_dsi_enable_pads;
	299	board_data->dsi_disable_pads = omap_dsi_disable_pads;
	300	board_data->get_context_loss_count = omap_pm_get_dev_context_loss_count;
	301	board_data->set_min_bus_tput = omap_dss_set_min_bus_tput;
	302
	303	omap_display_device.dev.platform_data = board_data;
	304
	305	r = platform_device_register(&omap_display_device);
	306	if (r < 0) {
	307	pr_err("Unable to register omapdss device\n");
	308	return r;
	309	}
	310
	311	/* create devices for dss hwmods */
cf07f531	312
179e0453 AT	313	if (cpu_is_omap24xx()) {
	314	curr_dss_hwmod = omap2_dss_hwmod_data;
	315	oh_count = ARRAY_SIZE(omap2_dss_hwmod_data);
	316	} else if (cpu_is_omap34xx()) {
	317	curr_dss_hwmod = omap3_dss_hwmod_data;
	318	oh_count = ARRAY_SIZE(omap3_dss_hwmod_data);
	319	} else {
	320	curr_dss_hwmod = omap4_dss_hwmod_data;
	321	oh_count = ARRAY_SIZE(omap4_dss_hwmod_data);
	322	}
545376e7	323
966eaed0 TV	324	/*
	325	* First create the pdev for dss_core, which is used as a parent device
	326	* by the other dss pdevs. Note: dss_core has to be the first item in
	327	* the hwmod list.
	328	*/
	329	dss_pdev = create_dss_pdev(curr_dss_hwmod[0].dev_name,
	330	curr_dss_hwmod[0].id,
	331	curr_dss_hwmod[0].oh_name,
35deca3d	332	board_data, sizeof(*board_data),
966eaed0	333	NULL);
fd4b34f6	334
966eaed0 TV	335	if (IS_ERR(dss_pdev)) {
	336	pr_err("Could not build omap_device for %s\n",
	337	curr_dss_hwmod[0].oh_name);
	338
	339	return PTR_ERR(dss_pdev);
	340	}
	341
	342	for (i = 1; i < oh_count; i++) {
	343	pdev = create_dss_pdev(curr_dss_hwmod[i].dev_name,
	344	curr_dss_hwmod[i].id,
	345	curr_dss_hwmod[i].oh_name,
35deca3d	346	board_data, sizeof(*board_data),
966eaed0 TV	347	dss_pdev);
	348
	349	if (IS_ERR(pdev)) {
	350	pr_err("Could not build omap_device for %s\n",
	351	curr_dss_hwmod[i].oh_name);
cf07f531	352
966eaed0 TV	353	return PTR_ERR(pdev);
966eaed0 TV	354	}
cf07f531	355	}
b7ee79ab	356
53f576a8 TV	357	/* Create devices for DPI and SDI */
53f576a8 TV	358
35deca3d TV	359	pdev = create_simple_dss_pdev("omapdss_dpi", -1,
35deca3d TV	360	board_data, sizeof(*board_data), dss_pdev);
53f576a8 TV	361	if (IS_ERR(pdev)) {
	362	pr_err("Could not build platform_device for omapdss_dpi\n");
	363	return PTR_ERR(pdev);
	364	}
	365
	366	if (cpu_is_omap34xx()) {
35deca3d TV	367	pdev = create_simple_dss_pdev("omapdss_sdi", -1,
35deca3d TV	368	board_data, sizeof(*board_data), dss_pdev);
53f576a8 TV	369	if (IS_ERR(pdev)) {
	370	pr_err("Could not build platform_device for omapdss_sdi\n");
	371	return PTR_ERR(pdev);
	372	}
	373	}
	374
00928eaf	375	return 0;
b7ee79ab	376	}
13662dc5	377
b923d40d AT	378	static void dispc_disable_outputs(void)
	379	{
	380	u32 v, irq_mask = 0;
465698ee	381	bool lcd_en, digit_en, lcd2_en = false, lcd3_en = false;
b923d40d AT	382	int i;
	383	struct omap_dss_dispc_dev_attr *da;
	384	struct omap_hwmod *oh;
	385
	386	oh = omap_hwmod_lookup("dss_dispc");
	387	if (!oh) {
	388	WARN(1, "display: could not disable outputs during reset - could not find dss_dispc hwmod\n");
	389	return;
	390	}
	391
	392	if (!oh->dev_attr) {
	393	pr_err("display: could not disable outputs during reset due to missing dev_attr\n");
	394	return;
	395	}
	396
	397	da = (struct omap_dss_dispc_dev_attr *)oh->dev_attr;
	398
	399	/* store value of LCDENABLE and DIGITENABLE bits */
	400	v = omap_hwmod_read(oh, DISPC_CONTROL);
	401	lcd_en = v & LCD_EN_MASK;
	402	digit_en = v & DIGIT_EN_MASK;
	403
	404	/* store value of LCDENABLE for LCD2 */
	405	if (da->manager_count > 2) {
	406	v = omap_hwmod_read(oh, DISPC_CONTROL2);
	407	lcd2_en = v & LCD_EN_MASK;
	408	}
	409
465698ee CM	410	/* store value of LCDENABLE for LCD3 */
	411	if (da->manager_count > 3) {
	412	v = omap_hwmod_read(oh, DISPC_CONTROL3);
	413	lcd3_en = v & LCD_EN_MASK;
	414	}
	415
	416	if (!(lcd_en \| digit_en \| lcd2_en \| lcd3_en))
b923d40d AT	417	return; /* no managers currently enabled */
	418
	419	/*
	420	* If any manager was enabled, we need to disable it before
	421	* DSS clocks are disabled or DISPC module is reset
	422	*/
	423	if (lcd_en)
	424	irq_mask \|= 1 << FRAMEDONE_IRQ_SHIFT;
	425
	426	if (digit_en) {
	427	if (da->has_framedonetv_irq) {
	428	irq_mask \|= 1 << FRAMEDONETV_IRQ_SHIFT;
	429	} else {
	430	irq_mask \|= 1 << EVSYNC_EVEN_IRQ_SHIFT \|
	431	1 << EVSYNC_ODD_IRQ_SHIFT;
	432	}
	433	}
	434
	435	if (lcd2_en)
	436	irq_mask \|= 1 << FRAMEDONE2_IRQ_SHIFT;
465698ee CM	437	if (lcd3_en)
465698ee CM	438	irq_mask \|= 1 << FRAMEDONE3_IRQ_SHIFT;
b923d40d AT	439
	440	/*
	441	* clear any previous FRAMEDONE, FRAMEDONETV,
465698ee	442	* EVSYNC_EVEN/ODD, FRAMEDONE2 or FRAMEDONE3 interrupts
b923d40d AT	443	*/
	444	omap_hwmod_write(irq_mask, oh, DISPC_IRQSTATUS);
	445
	446	/* disable LCD and TV managers */
	447	v = omap_hwmod_read(oh, DISPC_CONTROL);
	448	v &= ~(LCD_EN_MASK \| DIGIT_EN_MASK);
	449	omap_hwmod_write(v, oh, DISPC_CONTROL);
	450
	451	/* disable LCD2 manager */
	452	if (da->manager_count > 2) {
	453	v = omap_hwmod_read(oh, DISPC_CONTROL2);
	454	v &= ~LCD_EN_MASK;
	455	omap_hwmod_write(v, oh, DISPC_CONTROL2);
	456	}
	457
465698ee CM	458	/* disable LCD3 manager */
	459	if (da->manager_count > 3) {
	460	v = omap_hwmod_read(oh, DISPC_CONTROL3);
	461	v &= ~LCD_EN_MASK;
	462	omap_hwmod_write(v, oh, DISPC_CONTROL3);
	463	}
	464
b923d40d AT	465	i = 0;
	466	while ((omap_hwmod_read(oh, DISPC_IRQSTATUS) & irq_mask) !=
	467	irq_mask) {
	468	i++;
	469	if (i > FRAMEDONE_IRQ_TIMEOUT) {
465698ee	470	pr_err("didn't get FRAMEDONE1/2/3 or TV interrupt\n");
b923d40d AT	471	break;
	472	}
	473	mdelay(1);
	474	}
	475	}
	476
13662dc5 TV	477	#define MAX_MODULE_SOFTRESET_WAIT 10000
	478	int omap_dss_reset(struct omap_hwmod *oh)
	479	{
	480	struct omap_hwmod_opt_clk *oc;
	481	int c = 0;
	482	int i, r;
	483
	484	if (!(oh->class->sysc->sysc_flags & SYSS_HAS_RESET_STATUS)) {
	485	pr_err("dss_core: hwmod data doesn't contain reset data\n");
	486	return -EINVAL;
	487	}
	488
	489	for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++)
	490	if (oc->_clk)
	491	clk_enable(oc->_clk);
	492
b923d40d AT	493	dispc_disable_outputs();
	494
	495	/* clear SDI registers */
	496	if (cpu_is_omap3430()) {
	497	omap_hwmod_write(0x0, oh, DSS_SDI_CONTROL);
	498	omap_hwmod_write(0x0, oh, DSS_PLL_CONTROL);
	499	}
	500
	501	/*
	502	* clear DSS_CONTROL register to switch DSS clock sources to
	503	* PRCM clock, if any
	504	*/
	505	omap_hwmod_write(0x0, oh, DSS_CONTROL);
	506
13662dc5 TV	507	omap_test_timeout((omap_hwmod_read(oh, oh->class->sysc->syss_offs)
	508	& SYSS_RESETDONE_MASK),
	509	MAX_MODULE_SOFTRESET_WAIT, c);
	510
	511	if (c == MAX_MODULE_SOFTRESET_WAIT)
	512	pr_warning("dss_core: waiting for reset to finish failed\n");
	513	else
	514	pr_debug("dss_core: softreset done\n");
	515
	516	for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++)
	517	if (oc->_clk)
	518	clk_disable(oc->_clk);
	519
	520	r = (c == MAX_MODULE_SOFTRESET_WAIT) ? -ETIMEDOUT : 0;
	521
	522	return r;
	523	}