[deliverable/linux.git] / arch / arm / mach-omap2 / display.c

/*
 * OMAP2plus display device setup / initialization.
 *
 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
 *	Senthilvadivu Guruswamy
 *	Sumit Semwal
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
 * kind, whether express or implied; without even the implied warranty
 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <linux/string.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/io.h>
#include <linux/clk.h>
#include <linux/err.h>
#include <linux/delay.h>
#include <linux/of.h>
#include <linux/of_platform.h>
#include <linux/slab.h>

#include <video/omapdss.h>
#include "omap_hwmod.h"
#include "omap_device.h"
#include "omap-pm.h"
#include "common.h"

#include "soc.h"
#include "iomap.h"
#include "control.h"
#include "display.h"
#include "prm.h"

#define DISPC_CONTROL		0x0040
#define DISPC_CONTROL2		0x0238
#define DISPC_CONTROL3		0x0848
#define DISPC_IRQSTATUS		0x0018

#define DSS_SYSCONFIG		0x10
#define DSS_SYSSTATUS		0x14
#define DSS_CONTROL		0x40
#define DSS_SDI_CONTROL		0x44
#define DSS_PLL_CONTROL		0x48

#define LCD_EN_MASK		(0x1 << 0)
#define DIGIT_EN_MASK		(0x1 << 1)

#define FRAMEDONE_IRQ_SHIFT	0
#define EVSYNC_EVEN_IRQ_SHIFT	2
#define EVSYNC_ODD_IRQ_SHIFT	3
#define FRAMEDONE2_IRQ_SHIFT	22
#define FRAMEDONE3_IRQ_SHIFT	30
#define FRAMEDONETV_IRQ_SHIFT	24

/*
 * FRAMEDONE_IRQ_TIMEOUT: how long (in milliseconds) to wait during DISPC
 *     reset before deciding that something has gone wrong
 */
#define FRAMEDONE_IRQ_TIMEOUT		100

static struct platform_device omap_display_device = {
	.name          = "omapdss",
	.id            = -1,
	.dev            = {
		.platform_data = NULL,
	},
};

struct omap_dss_hwmod_data {
	const char *oh_name;
	const char *dev_name;
	const int id;
};

static const struct omap_dss_hwmod_data omap2_dss_hwmod_data[] __initconst = {
	{ "dss_core", "omapdss_dss", -1 },
	{ "dss_dispc", "omapdss_dispc", -1 },
	{ "dss_rfbi", "omapdss_rfbi", -1 },
	{ "dss_venc", "omapdss_venc", -1 },
};

static const struct omap_dss_hwmod_data omap3_dss_hwmod_data[] __initconst = {
	{ "dss_core", "omapdss_dss", -1 },
	{ "dss_dispc", "omapdss_dispc", -1 },
	{ "dss_rfbi", "omapdss_rfbi", -1 },
	{ "dss_venc", "omapdss_venc", -1 },
	{ "dss_dsi1", "omapdss_dsi", 0 },
};

static const struct omap_dss_hwmod_data omap4_dss_hwmod_data[] __initconst = {
	{ "dss_core", "omapdss_dss", -1 },
	{ "dss_dispc", "omapdss_dispc", -1 },
	{ "dss_rfbi", "omapdss_rfbi", -1 },
	{ "dss_dsi1", "omapdss_dsi", 0 },
	{ "dss_dsi2", "omapdss_dsi", 1 },
	{ "dss_hdmi", "omapdss_hdmi", -1 },
};

static int omap4_dsi_mux_pads(int dsi_id, unsigned lanes)
{
	u32 enable_mask, enable_shift;
	u32 pipd_mask, pipd_shift;
	u32 reg;

	if (dsi_id == 0) {
		enable_mask = OMAP4_DSI1_LANEENABLE_MASK;
		enable_shift = OMAP4_DSI1_LANEENABLE_SHIFT;
		pipd_mask = OMAP4_DSI1_PIPD_MASK;
		pipd_shift = OMAP4_DSI1_PIPD_SHIFT;
	} else if (dsi_id == 1) {
		enable_mask = OMAP4_DSI2_LANEENABLE_MASK;
		enable_shift = OMAP4_DSI2_LANEENABLE_SHIFT;
		pipd_mask = OMAP4_DSI2_PIPD_MASK;
		pipd_shift = OMAP4_DSI2_PIPD_SHIFT;
	} else {
		return -ENODEV;
	}

	reg = omap4_ctrl_pad_readl(OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_DSIPHY);

	reg &= ~enable_mask;
	reg &= ~pipd_mask;

	reg |= (lanes << enable_shift) & enable_mask;
	reg |= (lanes << pipd_shift) & pipd_mask;

	omap4_ctrl_pad_writel(reg, OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_DSIPHY);

	return 0;
}

static int omap_dsi_enable_pads(int dsi_id, unsigned lane_mask)
{
	if (cpu_is_omap44xx())
		return omap4_dsi_mux_pads(dsi_id, lane_mask);

	return 0;
}

static void omap_dsi_disable_pads(int dsi_id, unsigned lane_mask)
{
	if (cpu_is_omap44xx())
		omap4_dsi_mux_pads(dsi_id, 0);
}

static int omap_dss_set_min_bus_tput(struct device *dev, unsigned long tput)
{
	return omap_pm_set_min_bus_tput(dev, OCP_INITIATOR_AGENT, tput);
}

static struct platform_device *create_dss_pdev(const char *pdev_name,
		int pdev_id, const char *oh_name, void *pdata, int pdata_len,
		struct platform_device *parent)
{
	struct platform_device *pdev;
	struct omap_device *od;
	struct omap_hwmod *ohs[1];
	struct omap_hwmod *oh;
	int r;

	oh = omap_hwmod_lookup(oh_name);
	if (!oh) {
		pr_err("Could not look up %s\n", oh_name);
		r = -ENODEV;
		goto err;
	}

	pdev = platform_device_alloc(pdev_name, pdev_id);
	if (!pdev) {
		pr_err("Could not create pdev for %s\n", pdev_name);
		r = -ENOMEM;
		goto err;
	}

	if (parent != NULL)
		pdev->dev.parent = &parent->dev;

	if (pdev->id != -1)
		dev_set_name(&pdev->dev, "%s.%d", pdev->name, pdev->id);
	else
		dev_set_name(&pdev->dev, "%s", pdev->name);

	ohs[0] = oh;
	od = omap_device_alloc(pdev, ohs, 1);
	if (IS_ERR(od)) {
		pr_err("Could not alloc omap_device for %s\n", pdev_name);
		r = -ENOMEM;
		goto err;
	}

	r = platform_device_add_data(pdev, pdata, pdata_len);
	if (r) {
		pr_err("Could not set pdata for %s\n", pdev_name);
		goto err;
	}

	r = omap_device_register(pdev);
	if (r) {
		pr_err("Could not register omap_device for %s\n", pdev_name);
		goto err;
	}

	return pdev;

err:
	return ERR_PTR(r);
}

static struct platform_device *create_simple_dss_pdev(const char *pdev_name,
		int pdev_id, void *pdata, int pdata_len,
		struct platform_device *parent)
{
	struct platform_device *pdev;
	int r;

	pdev = platform_device_alloc(pdev_name, pdev_id);
	if (!pdev) {
		pr_err("Could not create pdev for %s\n", pdev_name);
		r = -ENOMEM;
		goto err;
	}

	if (parent != NULL)
		pdev->dev.parent = &parent->dev;

	if (pdev->id != -1)
		dev_set_name(&pdev->dev, "%s.%d", pdev->name, pdev->id);
	else
		dev_set_name(&pdev->dev, "%s", pdev->name);

	r = platform_device_add_data(pdev, pdata, pdata_len);
	if (r) {
		pr_err("Could not set pdata for %s\n", pdev_name);
		goto err;
	}

	r = platform_device_add(pdev);
	if (r) {
		pr_err("Could not register platform_device for %s\n", pdev_name);
		goto err;
	}

	return pdev;

err:
	return ERR_PTR(r);
}

static enum omapdss_version __init omap_display_get_version(void)
{
	if (cpu_is_omap24xx())
		return OMAPDSS_VER_OMAP24xx;
	else if (cpu_is_omap3630())
		return OMAPDSS_VER_OMAP3630;
	else if (cpu_is_omap34xx()) {
		if (soc_is_am35xx()) {
			return OMAPDSS_VER_AM35xx;
		} else {
			if (omap_rev() < OMAP3430_REV_ES3_0)
				return OMAPDSS_VER_OMAP34xx_ES1;
			else
				return OMAPDSS_VER_OMAP34xx_ES3;
		}
	} else if (omap_rev() == OMAP4430_REV_ES1_0)
		return OMAPDSS_VER_OMAP4430_ES1;
	else if (omap_rev() == OMAP4430_REV_ES2_0 ||
			omap_rev() == OMAP4430_REV_ES2_1 ||
			omap_rev() == OMAP4430_REV_ES2_2)
		return OMAPDSS_VER_OMAP4430_ES2;
	else if (cpu_is_omap44xx())
		return OMAPDSS_VER_OMAP4;
	else if (soc_is_omap54xx())
		return OMAPDSS_VER_OMAP5;
	else
		return OMAPDSS_VER_UNKNOWN;
}

int __init omap_display_init(struct omap_dss_board_info *board_data)
{
	int r = 0;
	struct platform_device *pdev;
	int i, oh_count;
	const struct omap_dss_hwmod_data *curr_dss_hwmod;
	struct platform_device *dss_pdev;
	enum omapdss_version ver;

	/* create omapdss device */

	ver = omap_display_get_version();

	if (ver == OMAPDSS_VER_UNKNOWN) {
		pr_err("DSS not supported on this SoC\n");
		return -ENODEV;
	}

	board_data->version = ver;
	board_data->dsi_enable_pads = omap_dsi_enable_pads;
	board_data->dsi_disable_pads = omap_dsi_disable_pads;
	board_data->set_min_bus_tput = omap_dss_set_min_bus_tput;

	omap_display_device.dev.platform_data = board_data;

	r = platform_device_register(&omap_display_device);
	if (r < 0) {
		pr_err("Unable to register omapdss device\n");
		return r;
	}

	/* create devices for dss hwmods */

	if (cpu_is_omap24xx()) {
		curr_dss_hwmod = omap2_dss_hwmod_data;
		oh_count = ARRAY_SIZE(omap2_dss_hwmod_data);
	} else if (cpu_is_omap34xx()) {
		curr_dss_hwmod = omap3_dss_hwmod_data;
		oh_count = ARRAY_SIZE(omap3_dss_hwmod_data);
	} else {
		curr_dss_hwmod = omap4_dss_hwmod_data;
		oh_count = ARRAY_SIZE(omap4_dss_hwmod_data);
	}

	/*
	 * First create the pdev for dss_core, which is used as a parent device
	 * by the other dss pdevs. Note: dss_core has to be the first item in
	 * the hwmod list.
	 */
	dss_pdev = create_dss_pdev(curr_dss_hwmod[0].dev_name,
			curr_dss_hwmod[0].id,
			curr_dss_hwmod[0].oh_name,
			board_data, sizeof(*board_data),
			NULL);

	if (IS_ERR(dss_pdev)) {
		pr_err("Could not build omap_device for %s\n",
				curr_dss_hwmod[0].oh_name);

		return PTR_ERR(dss_pdev);
	}

	for (i = 1; i < oh_count; i++) {
		pdev = create_dss_pdev(curr_dss_hwmod[i].dev_name,
				curr_dss_hwmod[i].id,
				curr_dss_hwmod[i].oh_name,
				board_data, sizeof(*board_data),
				dss_pdev);

		if (IS_ERR(pdev)) {
			pr_err("Could not build omap_device for %s\n",
					curr_dss_hwmod[i].oh_name);

			return PTR_ERR(pdev);
		}
	}

	/* Create devices for DPI and SDI */

	pdev = create_simple_dss_pdev("omapdss_dpi", 0,
			board_data, sizeof(*board_data), dss_pdev);
	if (IS_ERR(pdev)) {
		pr_err("Could not build platform_device for omapdss_dpi\n");
		return PTR_ERR(pdev);
	}

	if (cpu_is_omap34xx()) {
		pdev = create_simple_dss_pdev("omapdss_sdi", 0,
				board_data, sizeof(*board_data), dss_pdev);
		if (IS_ERR(pdev)) {
			pr_err("Could not build platform_device for omapdss_sdi\n");
			return PTR_ERR(pdev);
		}
	}

	/* create DRM device */
	r = omap_init_drm();
	if (r < 0) {
		pr_err("Unable to register omapdrm device\n");
		return r;
	}

	/* create vrfb device */
	r = omap_init_vrfb();
	if (r < 0) {
		pr_err("Unable to register omapvrfb device\n");
		return r;
	}

	/* create FB device */
	r = omap_init_fb();
	if (r < 0) {
		pr_err("Unable to register omapfb device\n");
		return r;
	}

	/* create V4L2 display device */
	r = omap_init_vout();
	if (r < 0) {
		pr_err("Unable to register omap_vout device\n");
		return r;
	}

	return 0;
}

static void dispc_disable_outputs(void)
{
	u32 v, irq_mask = 0;
	bool lcd_en, digit_en, lcd2_en = false, lcd3_en = false;
	int i;
	struct omap_dss_dispc_dev_attr *da;
	struct omap_hwmod *oh;

	oh = omap_hwmod_lookup("dss_dispc");
	if (!oh) {
		WARN(1, "display: could not disable outputs during reset - could not find dss_dispc hwmod\n");
		return;
	}

	if (!oh->dev_attr) {
		pr_err("display: could not disable outputs during reset due to missing dev_attr\n");
		return;
	}

	da = (struct omap_dss_dispc_dev_attr *)oh->dev_attr;

	/* store value of LCDENABLE and DIGITENABLE bits */
	v = omap_hwmod_read(oh, DISPC_CONTROL);
	lcd_en = v & LCD_EN_MASK;
	digit_en = v & DIGIT_EN_MASK;

	/* store value of LCDENABLE for LCD2 */
	if (da->manager_count > 2) {
		v = omap_hwmod_read(oh, DISPC_CONTROL2);
		lcd2_en = v & LCD_EN_MASK;
	}

	/* store value of LCDENABLE for LCD3 */
	if (da->manager_count > 3) {
		v = omap_hwmod_read(oh, DISPC_CONTROL3);
		lcd3_en = v & LCD_EN_MASK;
	}

	if (!(lcd_en | digit_en | lcd2_en | lcd3_en))
		return; /* no managers currently enabled */

	/*
	 * If any manager was enabled, we need to disable it before
	 * DSS clocks are disabled or DISPC module is reset
	 */
	if (lcd_en)
		irq_mask |= 1 << FRAMEDONE_IRQ_SHIFT;

	if (digit_en) {
		if (da->has_framedonetv_irq) {
			irq_mask |= 1 << FRAMEDONETV_IRQ_SHIFT;
		} else {
			irq_mask |= 1 << EVSYNC_EVEN_IRQ_SHIFT |
				1 << EVSYNC_ODD_IRQ_SHIFT;
		}
	}

	if (lcd2_en)
		irq_mask |= 1 << FRAMEDONE2_IRQ_SHIFT;
	if (lcd3_en)
		irq_mask |= 1 << FRAMEDONE3_IRQ_SHIFT;

	/*
	 * clear any previous FRAMEDONE, FRAMEDONETV,
	 * EVSYNC_EVEN/ODD, FRAMEDONE2 or FRAMEDONE3 interrupts
	 */
	omap_hwmod_write(irq_mask, oh, DISPC_IRQSTATUS);

	/* disable LCD and TV managers */
	v = omap_hwmod_read(oh, DISPC_CONTROL);
	v &= ~(LCD_EN_MASK | DIGIT_EN_MASK);
	omap_hwmod_write(v, oh, DISPC_CONTROL);

	/* disable LCD2 manager */
	if (da->manager_count > 2) {
		v = omap_hwmod_read(oh, DISPC_CONTROL2);
		v &= ~LCD_EN_MASK;
		omap_hwmod_write(v, oh, DISPC_CONTROL2);
	}

	/* disable LCD3 manager */
	if (da->manager_count > 3) {
		v = omap_hwmod_read(oh, DISPC_CONTROL3);
		v &= ~LCD_EN_MASK;
		omap_hwmod_write(v, oh, DISPC_CONTROL3);
	}

	i = 0;
	while ((omap_hwmod_read(oh, DISPC_IRQSTATUS) & irq_mask) !=
	       irq_mask) {
		i++;
		if (i > FRAMEDONE_IRQ_TIMEOUT) {
			pr_err("didn't get FRAMEDONE1/2/3 or TV interrupt\n");
			break;
		}
		mdelay(1);
	}
}

int omap_dss_reset(struct omap_hwmod *oh)
{
	struct omap_hwmod_opt_clk *oc;
	int c = 0;
	int i, r;

	if (!(oh->class->sysc->sysc_flags & SYSS_HAS_RESET_STATUS)) {
		pr_err("dss_core: hwmod data doesn't contain reset data\n");
		return -EINVAL;
	}

	for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++)
		if (oc->_clk)
			clk_prepare_enable(oc->_clk);

	dispc_disable_outputs();

	/* clear SDI registers */
	if (cpu_is_omap3430()) {
		omap_hwmod_write(0x0, oh, DSS_SDI_CONTROL);
		omap_hwmod_write(0x0, oh, DSS_PLL_CONTROL);
	}

	/*
	 * clear DSS_CONTROL register to switch DSS clock sources to
	 * PRCM clock, if any
	 */
	omap_hwmod_write(0x0, oh, DSS_CONTROL);

	omap_test_timeout((omap_hwmod_read(oh, oh->class->sysc->syss_offs)
				& SYSS_RESETDONE_MASK),
			MAX_MODULE_SOFTRESET_WAIT, c);

	if (c == MAX_MODULE_SOFTRESET_WAIT)
		pr_warning("dss_core: waiting for reset to finish failed\n");
	else
		pr_debug("dss_core: softreset done\n");

	for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++)
		if (oc->_clk)
			clk_disable_unprepare(oc->_clk);

	r = (c == MAX_MODULE_SOFTRESET_WAIT) ? -ETIMEDOUT : 0;

	return r;
}

/* list of 'compatible' nodes to convert to omapdss specific */
static const char * const dss_compat_conv_list[] __initconst = {
	"composite-connector",
	"dvi-connector",
	"hdmi-connector",
	"panel-dpi",
	"panel-dsi-cm",
	"sony,acx565akm",
	"svideo-connector",
	"ti,tfp410",
	"ti,tpd12s015",
	"toppoly,td028ttec1",
};

/* prepend compatible string with "omapdss," */
static __init void omapdss_omapify_node(struct device_node *node,
	const char *compat)
{
	char *new_compat;
	struct property *prop;

	new_compat = kasprintf(GFP_KERNEL, "omapdss,%s", compat);

	prop = kzalloc(sizeof(*prop), GFP_KERNEL);

	if (!prop) {
		pr_err("omapdss_omapify_node: kzalloc failed\n");
		return;
	}

	prop->name = "compatible";
	prop->value = new_compat;
	prop->length = strlen(new_compat) + 1;

	of_update_property(node, prop);
}

/*
 * As omapdss panel drivers are omapdss specific, but we want to define the
 * DT-data in generic manner, we convert the compatible strings of the panel
 * nodes from "panel-foo" to "omapdss,panel-foo". This way we can have both
 * correct DT data and omapdss specific drivers.
 *
 * When we get generic panel drivers to the kernel, this will be removed.
 */
void __init omapdss_early_init_of(void)
{
	int i;

	for (i = 0; i < ARRAY_SIZE(dss_compat_conv_list); ++i) {
		const char *compat = dss_compat_conv_list[i];
		struct device_node *node = NULL;

		while ((node = of_find_compatible_node(node, NULL, compat))) {
			if (!of_device_is_available(node))
				continue;

			omapdss_omapify_node(node, compat);
		}
	}
}

struct device_node * __init omapdss_find_dss_of_node(void)
{
	struct device_node *node;

	node = of_find_compatible_node(NULL, NULL, "ti,omap2-dss");
	if (node)
		return node;

	node = of_find_compatible_node(NULL, NULL, "ti,omap3-dss");
	if (node)
		return node;

	node = of_find_compatible_node(NULL, NULL, "ti,omap4-dss");
	if (node)
		return node;

	return NULL;
}

int __init omapdss_init_of(void)
{
	int r;
	enum omapdss_version ver;
	struct device_node *node;
	struct platform_device *pdev;

	static struct omap_dss_board_info board_data = {
		.dsi_enable_pads = omap_dsi_enable_pads,
		.dsi_disable_pads = omap_dsi_disable_pads,
		.set_min_bus_tput = omap_dss_set_min_bus_tput,
	};

	/* only create dss helper devices if dss is enabled in the .dts */

	node = omapdss_find_dss_of_node();
	if (!node)
		return 0;

	if (!of_device_is_available(node))
		return 0;

	ver = omap_display_get_version();

	if (ver == OMAPDSS_VER_UNKNOWN) {
		pr_err("DSS not supported on this SoC\n");
		return -ENODEV;
	}

	pdev = of_find_device_by_node(node);

	if (!pdev) {
		pr_err("Unable to find DSS platform device\n");
		return -ENODEV;
	}

	r = of_platform_populate(node, NULL, NULL, &pdev->dev);
	if (r) {
		pr_err("Unable to populate DSS submodule devices\n");
		return r;
	}

	board_data.version = ver;

	omap_display_device.dev.platform_data = &board_data;

	r = platform_device_register(&omap_display_device);
	if (r < 0) {
		pr_err("Unable to register omapdss device\n");
		return r;
	}

	/* create DRM device */
	r = omap_init_drm();
	if (r < 0) {
		pr_err("Unable to register omapdrm device\n");
		return r;
	}

	/* create vrfb device */
	r = omap_init_vrfb();
	if (r < 0) {
		pr_err("Unable to register omapvrfb device\n");
		return r;
	}

	/* create FB device */
	r = omap_init_fb();
	if (r < 0) {
		pr_err("Unable to register omapfb device\n");
		return r;
	}

	/* create V4L2 display device */
	r = omap_init_vout();
	if (r < 0) {
		pr_err("Unable to register omap_vout device\n");
		return r;
	}

	return 0;
}
Commit	Line	Data
b7ee79ab SS	1	/*
	2	* OMAP2plus display device setup / initialization.
	3	*
	4	* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
	5	* Senthilvadivu Guruswamy
	6	* Sumit Semwal
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License version 2 as
	10	* published by the Free Software Foundation.
	11	*
	12	* This program is distributed "as is" WITHOUT ANY WARRANTY of any
	13	* kind, whether express or implied; without even the implied warranty
	14	* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*/
	17
d44b28c4	18	#include <linux/string.h>
b7ee79ab SS	19	#include <linux/kernel.h>
	20	#include <linux/init.h>
	21	#include <linux/platform_device.h>
	22	#include <linux/io.h>
	23	#include <linux/clk.h>
	24	#include <linux/err.h>
deee6d53	25	#include <linux/delay.h>
dcdf407b TV	26	#include <linux/of.h>
dcdf407b TV	27	#include <linux/of_platform.h>
6a0e6b38	28	#include <linux/slab.h>
b7ee79ab	29
a0b38cc4	30	#include <video/omapdss.h>
2a296c8f	31	#include "omap_hwmod.h"
25c7d49e	32	#include "omap_device.h"
1d5aef49	33	#include "omap-pm.h"
deee6d53	34	#include "common.h"
b7ee79ab	35
e4c060db	36	#include "soc.h"
ee0839c2	37	#include "iomap.h"
dc35835c	38	#include "control.h"
b923d40d	39	#include "display.h"
b13159af	40	#include "prm.h"
b923d40d AT	41
	42	#define DISPC_CONTROL 0x0040
	43	#define DISPC_CONTROL2 0x0238
465698ee	44	#define DISPC_CONTROL3 0x0848
b923d40d AT	45	#define DISPC_IRQSTATUS 0x0018
	46
	47	#define DSS_SYSCONFIG 0x10
	48	#define DSS_SYSSTATUS 0x14
	49	#define DSS_CONTROL 0x40
	50	#define DSS_SDI_CONTROL 0x44
	51	#define DSS_PLL_CONTROL 0x48
	52
	53	#define LCD_EN_MASK (0x1 << 0)
	54	#define DIGIT_EN_MASK (0x1 << 1)
	55
	56	#define FRAMEDONE_IRQ_SHIFT 0
	57	#define EVSYNC_EVEN_IRQ_SHIFT 2
	58	#define EVSYNC_ODD_IRQ_SHIFT 3
	59	#define FRAMEDONE2_IRQ_SHIFT 22
465698ee	60	#define FRAMEDONE3_IRQ_SHIFT 30
b923d40d AT	61	#define FRAMEDONETV_IRQ_SHIFT 24
	62
	63	/*
	64	* FRAMEDONE_IRQ_TIMEOUT: how long (in milliseconds) to wait during DISPC
	65	* reset before deciding that something has gone wrong
	66	*/
	67	#define FRAMEDONE_IRQ_TIMEOUT 100
dc35835c	68
b7ee79ab SS	69	static struct platform_device omap_display_device = {
	70	.name = "omapdss",
	71	.id = -1,
	72	.dev = {
	73	.platform_data = NULL,
	74	},
	75	};
	76
179e0453 AT	77	struct omap_dss_hwmod_data {
	78	const char *oh_name;
	79	const char *dev_name;
	80	const int id;
	81	};
	82
bcad6dc3	83	static const struct omap_dss_hwmod_data omap2_dss_hwmod_data[] __initconst = {
179e0453 AT	84	{ "dss_core", "omapdss_dss", -1 },
	85	{ "dss_dispc", "omapdss_dispc", -1 },
	86	{ "dss_rfbi", "omapdss_rfbi", -1 },
	87	{ "dss_venc", "omapdss_venc", -1 },
	88	};
	89
bcad6dc3	90	static const struct omap_dss_hwmod_data omap3_dss_hwmod_data[] __initconst = {
179e0453 AT	91	{ "dss_core", "omapdss_dss", -1 },
	92	{ "dss_dispc", "omapdss_dispc", -1 },
	93	{ "dss_rfbi", "omapdss_rfbi", -1 },
	94	{ "dss_venc", "omapdss_venc", -1 },
7c68dd96	95	{ "dss_dsi1", "omapdss_dsi", 0 },
179e0453 AT	96	};
179e0453 AT	97
bcad6dc3	98	static const struct omap_dss_hwmod_data omap4_dss_hwmod_data[] __initconst = {
179e0453 AT	99	{ "dss_core", "omapdss_dss", -1 },
	100	{ "dss_dispc", "omapdss_dispc", -1 },
	101	{ "dss_rfbi", "omapdss_rfbi", -1 },
7c68dd96 TV	102	{ "dss_dsi1", "omapdss_dsi", 0 },
7c68dd96 TV	103	{ "dss_dsi2", "omapdss_dsi", 1 },
179e0453 AT	104	{ "dss_hdmi", "omapdss_hdmi", -1 },
	105	};
	106
130f769e TV	107	static int omap4_dsi_mux_pads(int dsi_id, unsigned lanes)
	108	{
	109	u32 enable_mask, enable_shift;
	110	u32 pipd_mask, pipd_shift;
	111	u32 reg;
	112
	113	if (dsi_id == 0) {
	114	enable_mask = OMAP4_DSI1_LANEENABLE_MASK;
	115	enable_shift = OMAP4_DSI1_LANEENABLE_SHIFT;
	116	pipd_mask = OMAP4_DSI1_PIPD_MASK;
	117	pipd_shift = OMAP4_DSI1_PIPD_SHIFT;
	118	} else if (dsi_id == 1) {
	119	enable_mask = OMAP4_DSI2_LANEENABLE_MASK;
	120	enable_shift = OMAP4_DSI2_LANEENABLE_SHIFT;
	121	pipd_mask = OMAP4_DSI2_PIPD_MASK;
	122	pipd_shift = OMAP4_DSI2_PIPD_SHIFT;
	123	} else {
	124	return -ENODEV;
	125	}
	126
	127	reg = omap4_ctrl_pad_readl(OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_DSIPHY);
	128
	129	reg &= ~enable_mask;
	130	reg &= ~pipd_mask;
	131
	132	reg \|= (lanes << enable_shift) & enable_mask;
	133	reg \|= (lanes << pipd_shift) & pipd_mask;
	134
	135	omap4_ctrl_pad_writel(reg, OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_DSIPHY);
	136
	137	return 0;
	138	}
	139
e8a30b25	140	static int omap_dsi_enable_pads(int dsi_id, unsigned lane_mask)
5bc416cb	141	{
130f769e TV	142	if (cpu_is_omap44xx())
	143	return omap4_dsi_mux_pads(dsi_id, lane_mask);
	144
5bc416cb TV	145	return 0;
	146	}
	147
e8a30b25	148	static void omap_dsi_disable_pads(int dsi_id, unsigned lane_mask)
5bc416cb	149	{
130f769e TV	150	if (cpu_is_omap44xx())
130f769e TV	151	omap4_dsi_mux_pads(dsi_id, 0);
5bc416cb TV	152	}
5bc416cb TV	153
62c1dcfc TV	154	static int omap_dss_set_min_bus_tput(struct device *dev, unsigned long tput)
	155	{
	156	return omap_pm_set_min_bus_tput(dev, OCP_INITIATOR_AGENT, tput);
	157	}
	158
966eaed0 TV	159	static struct platform_device create_dss_pdev(const char pdev_name,
	160	int pdev_id, const char oh_name, void pdata, int pdata_len,
	161	struct platform_device *parent)
	162	{
	163	struct platform_device *pdev;
	164	struct omap_device *od;
	165	struct omap_hwmod *ohs[1];
	166	struct omap_hwmod *oh;
	167	int r;
	168
	169	oh = omap_hwmod_lookup(oh_name);
	170	if (!oh) {
	171	pr_err("Could not look up %s\n", oh_name);
	172	r = -ENODEV;
	173	goto err;
	174	}
	175
	176	pdev = platform_device_alloc(pdev_name, pdev_id);
	177	if (!pdev) {
	178	pr_err("Could not create pdev for %s\n", pdev_name);
	179	r = -ENOMEM;
	180	goto err;
	181	}
	182
	183	if (parent != NULL)
	184	pdev->dev.parent = &parent->dev;
	185
	186	if (pdev->id != -1)
	187	dev_set_name(&pdev->dev, "%s.%d", pdev->name, pdev->id);
	188	else
	189	dev_set_name(&pdev->dev, "%s", pdev->name);
	190
	191	ohs[0] = oh;
c1d1cd59	192	od = omap_device_alloc(pdev, ohs, 1);
9ee67723	193	if (IS_ERR(od)) {
966eaed0 TV	194	pr_err("Could not alloc omap_device for %s\n", pdev_name);
	195	r = -ENOMEM;
	196	goto err;
	197	}
	198
	199	r = platform_device_add_data(pdev, pdata, pdata_len);
	200	if (r) {
	201	pr_err("Could not set pdata for %s\n", pdev_name);
	202	goto err;
	203	}
	204
	205	r = omap_device_register(pdev);
	206	if (r) {
	207	pr_err("Could not register omap_device for %s\n", pdev_name);
	208	goto err;
	209	}
	210
	211	return pdev;
	212
	213	err:
	214	return ERR_PTR(r);
	215	}
	216
53f576a8 TV	217	static struct platform_device create_simple_dss_pdev(const char pdev_name,
	218	int pdev_id, void *pdata, int pdata_len,
	219	struct platform_device *parent)
	220	{
	221	struct platform_device *pdev;
	222	int r;
	223
	224	pdev = platform_device_alloc(pdev_name, pdev_id);
	225	if (!pdev) {
	226	pr_err("Could not create pdev for %s\n", pdev_name);
	227	r = -ENOMEM;
	228	goto err;
	229	}
	230
	231	if (parent != NULL)
	232	pdev->dev.parent = &parent->dev;
	233
	234	if (pdev->id != -1)
	235	dev_set_name(&pdev->dev, "%s.%d", pdev->name, pdev->id);
	236	else
	237	dev_set_name(&pdev->dev, "%s", pdev->name);
	238
	239	r = platform_device_add_data(pdev, pdata, pdata_len);
	240	if (r) {
	241	pr_err("Could not set pdata for %s\n", pdev_name);
	242	goto err;
	243	}
	244
c3a21fc7	245	r = platform_device_add(pdev);
53f576a8	246	if (r) {
c3a21fc7	247	pr_err("Could not register platform_device for %s\n", pdev_name);
53f576a8 TV	248	goto err;
	249	}
	250
	251	return pdev;
	252
	253	err:
	254	return ERR_PTR(r);
	255	}
	256
acd18af9 TV	257	static enum omapdss_version __init omap_display_get_version(void)
	258	{
	259	if (cpu_is_omap24xx())
	260	return OMAPDSS_VER_OMAP24xx;
	261	else if (cpu_is_omap3630())
	262	return OMAPDSS_VER_OMAP3630;
	263	else if (cpu_is_omap34xx()) {
	264	if (soc_is_am35xx()) {
	265	return OMAPDSS_VER_AM35xx;
	266	} else {
	267	if (omap_rev() < OMAP3430_REV_ES3_0)
	268	return OMAPDSS_VER_OMAP34xx_ES1;
	269	else
	270	return OMAPDSS_VER_OMAP34xx_ES3;
	271	}
	272	} else if (omap_rev() == OMAP4430_REV_ES1_0)
	273	return OMAPDSS_VER_OMAP4430_ES1;
	274	else if (omap_rev() == OMAP4430_REV_ES2_0 \|\|
	275	omap_rev() == OMAP4430_REV_ES2_1 \|\|
	276	omap_rev() == OMAP4430_REV_ES2_2)
	277	return OMAPDSS_VER_OMAP4430_ES2;
	278	else if (cpu_is_omap44xx())
	279	return OMAPDSS_VER_OMAP4;
	280	else if (soc_is_omap54xx())
	281	return OMAPDSS_VER_OMAP5;
	282	else
	283	return OMAPDSS_VER_UNKNOWN;
	284	}
	285
b7ee79ab SS	286	int __init omap_display_init(struct omap_dss_board_info *board_data)
	287	{
	288	int r = 0;
3528c58e	289	struct platform_device *pdev;
179e0453	290	int i, oh_count;
179e0453	291	const struct omap_dss_hwmod_data *curr_dss_hwmod;
966eaed0	292	struct platform_device *dss_pdev;
acd18af9	293	enum omapdss_version ver;
cf07f531	294
00928eaf TV	295	/* create omapdss device */
00928eaf TV	296
acd18af9 TV	297	ver = omap_display_get_version();
	298
	299	if (ver == OMAPDSS_VER_UNKNOWN) {
	300	pr_err("DSS not supported on this SoC\n");
	301	return -ENODEV;
	302	}
	303
	304	board_data->version = ver;
00928eaf TV	305	board_data->dsi_enable_pads = omap_dsi_enable_pads;
00928eaf TV	306	board_data->dsi_disable_pads = omap_dsi_disable_pads;
00928eaf TV	307	board_data->set_min_bus_tput = omap_dss_set_min_bus_tput;
	308
	309	omap_display_device.dev.platform_data = board_data;
	310
	311	r = platform_device_register(&omap_display_device);
	312	if (r < 0) {
	313	pr_err("Unable to register omapdss device\n");
	314	return r;
	315	}
	316
	317	/* create devices for dss hwmods */
cf07f531	318
179e0453 AT	319	if (cpu_is_omap24xx()) {
	320	curr_dss_hwmod = omap2_dss_hwmod_data;
	321	oh_count = ARRAY_SIZE(omap2_dss_hwmod_data);
	322	} else if (cpu_is_omap34xx()) {
	323	curr_dss_hwmod = omap3_dss_hwmod_data;
	324	oh_count = ARRAY_SIZE(omap3_dss_hwmod_data);
	325	} else {
	326	curr_dss_hwmod = omap4_dss_hwmod_data;
	327	oh_count = ARRAY_SIZE(omap4_dss_hwmod_data);
	328	}
545376e7	329
966eaed0 TV	330	/*
	331	* First create the pdev for dss_core, which is used as a parent device
	332	* by the other dss pdevs. Note: dss_core has to be the first item in
	333	* the hwmod list.
	334	*/
	335	dss_pdev = create_dss_pdev(curr_dss_hwmod[0].dev_name,
	336	curr_dss_hwmod[0].id,
	337	curr_dss_hwmod[0].oh_name,
35deca3d	338	board_data, sizeof(*board_data),
966eaed0	339	NULL);
fd4b34f6	340
966eaed0 TV	341	if (IS_ERR(dss_pdev)) {
	342	pr_err("Could not build omap_device for %s\n",
	343	curr_dss_hwmod[0].oh_name);
	344
	345	return PTR_ERR(dss_pdev);
	346	}
	347
	348	for (i = 1; i < oh_count; i++) {
	349	pdev = create_dss_pdev(curr_dss_hwmod[i].dev_name,
	350	curr_dss_hwmod[i].id,
	351	curr_dss_hwmod[i].oh_name,
35deca3d	352	board_data, sizeof(*board_data),
966eaed0 TV	353	dss_pdev);
	354
	355	if (IS_ERR(pdev)) {
	356	pr_err("Could not build omap_device for %s\n",
	357	curr_dss_hwmod[i].oh_name);
cf07f531	358
966eaed0 TV	359	return PTR_ERR(pdev);
966eaed0 TV	360	}
cf07f531	361	}
b7ee79ab	362
53f576a8 TV	363	/* Create devices for DPI and SDI */
53f576a8 TV	364
35f5df6f	365	pdev = create_simple_dss_pdev("omapdss_dpi", 0,
35deca3d	366	board_data, sizeof(*board_data), dss_pdev);
53f576a8 TV	367	if (IS_ERR(pdev)) {
	368	pr_err("Could not build platform_device for omapdss_dpi\n");
	369	return PTR_ERR(pdev);
	370	}
	371
	372	if (cpu_is_omap34xx()) {
35f5df6f	373	pdev = create_simple_dss_pdev("omapdss_sdi", 0,
35deca3d	374	board_data, sizeof(*board_data), dss_pdev);
53f576a8 TV	375	if (IS_ERR(pdev)) {
	376	pr_err("Could not build platform_device for omapdss_sdi\n");
	377	return PTR_ERR(pdev);
	378	}
	379	}
	380
7a59743d AT	381	/* create DRM device */
	382	r = omap_init_drm();
	383	if (r < 0) {
	384	pr_err("Unable to register omapdrm device\n");
	385	return r;
	386	}
	387
fc8df752 AT	388	/* create vrfb device */
	389	r = omap_init_vrfb();
	390	if (r < 0) {
	391	pr_err("Unable to register omapvrfb device\n");
	392	return r;
	393	}
	394
	395	/* create FB device */
	396	r = omap_init_fb();
	397	if (r < 0) {
	398	pr_err("Unable to register omapfb device\n");
	399	return r;
	400	}
	401
576e5bda AT	402	/* create V4L2 display device */
	403	r = omap_init_vout();
	404	if (r < 0) {
	405	pr_err("Unable to register omap_vout device\n");
	406	return r;
	407	}
	408
00928eaf	409	return 0;
b7ee79ab	410	}
13662dc5	411
b923d40d AT	412	static void dispc_disable_outputs(void)
	413	{
	414	u32 v, irq_mask = 0;
465698ee	415	bool lcd_en, digit_en, lcd2_en = false, lcd3_en = false;
b923d40d AT	416	int i;
	417	struct omap_dss_dispc_dev_attr *da;
	418	struct omap_hwmod *oh;
	419
	420	oh = omap_hwmod_lookup("dss_dispc");
	421	if (!oh) {
	422	WARN(1, "display: could not disable outputs during reset - could not find dss_dispc hwmod\n");
	423	return;
	424	}
	425
	426	if (!oh->dev_attr) {
	427	pr_err("display: could not disable outputs during reset due to missing dev_attr\n");
	428	return;
	429	}
	430
	431	da = (struct omap_dss_dispc_dev_attr *)oh->dev_attr;
	432
	433	/* store value of LCDENABLE and DIGITENABLE bits */
	434	v = omap_hwmod_read(oh, DISPC_CONTROL);
	435	lcd_en = v & LCD_EN_MASK;
	436	digit_en = v & DIGIT_EN_MASK;
	437
	438	/* store value of LCDENABLE for LCD2 */
	439	if (da->manager_count > 2) {
	440	v = omap_hwmod_read(oh, DISPC_CONTROL2);
	441	lcd2_en = v & LCD_EN_MASK;
	442	}
	443
465698ee CM	444	/* store value of LCDENABLE for LCD3 */
	445	if (da->manager_count > 3) {
	446	v = omap_hwmod_read(oh, DISPC_CONTROL3);
	447	lcd3_en = v & LCD_EN_MASK;
	448	}
	449
	450	if (!(lcd_en \| digit_en \| lcd2_en \| lcd3_en))
b923d40d AT	451	return; /* no managers currently enabled */
	452
	453	/*
	454	* If any manager was enabled, we need to disable it before
	455	* DSS clocks are disabled or DISPC module is reset
	456	*/
	457	if (lcd_en)
	458	irq_mask \|= 1 << FRAMEDONE_IRQ_SHIFT;
	459
	460	if (digit_en) {
	461	if (da->has_framedonetv_irq) {
	462	irq_mask \|= 1 << FRAMEDONETV_IRQ_SHIFT;
	463	} else {
	464	irq_mask \|= 1 << EVSYNC_EVEN_IRQ_SHIFT \|
	465	1 << EVSYNC_ODD_IRQ_SHIFT;
	466	}
	467	}
	468
	469	if (lcd2_en)
	470	irq_mask \|= 1 << FRAMEDONE2_IRQ_SHIFT;
465698ee CM	471	if (lcd3_en)
465698ee CM	472	irq_mask \|= 1 << FRAMEDONE3_IRQ_SHIFT;
b923d40d AT	473
	474	/*
	475	* clear any previous FRAMEDONE, FRAMEDONETV,
465698ee	476	* EVSYNC_EVEN/ODD, FRAMEDONE2 or FRAMEDONE3 interrupts
b923d40d AT	477	*/
	478	omap_hwmod_write(irq_mask, oh, DISPC_IRQSTATUS);
	479
	480	/* disable LCD and TV managers */
	481	v = omap_hwmod_read(oh, DISPC_CONTROL);
	482	v &= ~(LCD_EN_MASK \| DIGIT_EN_MASK);
	483	omap_hwmod_write(v, oh, DISPC_CONTROL);
	484
	485	/* disable LCD2 manager */
	486	if (da->manager_count > 2) {
	487	v = omap_hwmod_read(oh, DISPC_CONTROL2);
	488	v &= ~LCD_EN_MASK;
	489	omap_hwmod_write(v, oh, DISPC_CONTROL2);
	490	}
	491
465698ee CM	492	/* disable LCD3 manager */
	493	if (da->manager_count > 3) {
	494	v = omap_hwmod_read(oh, DISPC_CONTROL3);
	495	v &= ~LCD_EN_MASK;
	496	omap_hwmod_write(v, oh, DISPC_CONTROL3);
	497	}
	498
b923d40d AT	499	i = 0;
	500	while ((omap_hwmod_read(oh, DISPC_IRQSTATUS) & irq_mask) !=
	501	irq_mask) {
	502	i++;
	503	if (i > FRAMEDONE_IRQ_TIMEOUT) {
465698ee	504	pr_err("didn't get FRAMEDONE1/2/3 or TV interrupt\n");
b923d40d AT	505	break;
	506	}
	507	mdelay(1);
	508	}
	509	}
	510
13662dc5 TV	511	int omap_dss_reset(struct omap_hwmod *oh)
	512	{
	513	struct omap_hwmod_opt_clk *oc;
	514	int c = 0;
	515	int i, r;
	516
	517	if (!(oh->class->sysc->sysc_flags & SYSS_HAS_RESET_STATUS)) {
	518	pr_err("dss_core: hwmod data doesn't contain reset data\n");
	519	return -EINVAL;
	520	}
	521
	522	for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++)
	523	if (oc->_clk)
4d7cb45e	524	clk_prepare_enable(oc->_clk);
13662dc5	525
b923d40d AT	526	dispc_disable_outputs();
	527
	528	/* clear SDI registers */
	529	if (cpu_is_omap3430()) {
	530	omap_hwmod_write(0x0, oh, DSS_SDI_CONTROL);
	531	omap_hwmod_write(0x0, oh, DSS_PLL_CONTROL);
	532	}
	533
	534	/*
	535	* clear DSS_CONTROL register to switch DSS clock sources to
	536	* PRCM clock, if any
	537	*/
	538	omap_hwmod_write(0x0, oh, DSS_CONTROL);
	539
13662dc5 TV	540	omap_test_timeout((omap_hwmod_read(oh, oh->class->sysc->syss_offs)
	541	& SYSS_RESETDONE_MASK),
	542	MAX_MODULE_SOFTRESET_WAIT, c);
	543
	544	if (c == MAX_MODULE_SOFTRESET_WAIT)
	545	pr_warning("dss_core: waiting for reset to finish failed\n");
	546	else
	547	pr_debug("dss_core: softreset done\n");
	548
	549	for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++)
	550	if (oc->_clk)
4d7cb45e	551	clk_disable_unprepare(oc->_clk);
13662dc5 TV	552
	553	r = (c == MAX_MODULE_SOFTRESET_WAIT) ? -ETIMEDOUT : 0;
	554
	555	return r;
	556	}
dcdf407b	557
6a0e6b38 TV	558	/* list of 'compatible' nodes to convert to omapdss specific */
	559	static const char * const dss_compat_conv_list[] __initconst = {
	560	"composite-connector",
	561	"dvi-connector",
	562	"hdmi-connector",
	563	"panel-dpi",
	564	"panel-dsi-cm",
	565	"sony,acx565akm",
	566	"svideo-connector",
	567	"ti,tfp410",
	568	"ti,tpd12s015",
1f324509	569	"toppoly,td028ttec1",
6a0e6b38 TV	570	};
	571
	572	/* prepend compatible string with "omapdss," */
	573	static __init void omapdss_omapify_node(struct device_node *node,
	574	const char *compat)
	575	{
	576	char *new_compat;
	577	struct property *prop;
	578
	579	new_compat = kasprintf(GFP_KERNEL, "omapdss,%s", compat);
	580
	581	prop = kzalloc(sizeof(*prop), GFP_KERNEL);
	582
	583	if (!prop) {
	584	pr_err("omapdss_omapify_node: kzalloc failed\n");
	585	return;
	586	}
	587
	588	prop->name = "compatible";
	589	prop->value = new_compat;
	590	prop->length = strlen(new_compat) + 1;
	591
	592	of_update_property(node, prop);
	593	}
	594
	595	/*
	596	* As omapdss panel drivers are omapdss specific, but we want to define the
	597	* DT-data in generic manner, we convert the compatible strings of the panel
	598	* nodes from "panel-foo" to "omapdss,panel-foo". This way we can have both
	599	* correct DT data and omapdss specific drivers.
	600	*
	601	* When we get generic panel drivers to the kernel, this will be removed.
	602	*/
	603	void __init omapdss_early_init_of(void)
	604	{
	605	int i;
	606
	607	for (i = 0; i < ARRAY_SIZE(dss_compat_conv_list); ++i) {
	608	const char *compat = dss_compat_conv_list[i];
	609	struct device_node *node = NULL;
	610
	611	while ((node = of_find_compatible_node(node, NULL, compat))) {
	612	if (!of_device_is_available(node))
	613	continue;
	614
	615	omapdss_omapify_node(node, compat);
	616	}
	617	}
	618	}
	619
dcdf407b TV	620	struct device_node * __init omapdss_find_dss_of_node(void)
	621	{
	622	struct device_node *node;
	623
	624	node = of_find_compatible_node(NULL, NULL, "ti,omap2-dss");
	625	if (node)
	626	return node;
	627
	628	node = of_find_compatible_node(NULL, NULL, "ti,omap3-dss");
	629	if (node)
	630	return node;
	631
	632	node = of_find_compatible_node(NULL, NULL, "ti,omap4-dss");
	633	if (node)
	634	return node;
	635
	636	return NULL;
	637	}
	638
	639	int __init omapdss_init_of(void)
	640	{
	641	int r;
	642	enum omapdss_version ver;
	643	struct device_node *node;
	644	struct platform_device *pdev;
	645
	646	static struct omap_dss_board_info board_data = {
	647	.dsi_enable_pads = omap_dsi_enable_pads,
	648	.dsi_disable_pads = omap_dsi_disable_pads,
dcdf407b TV	649	.set_min_bus_tput = omap_dss_set_min_bus_tput,
	650	};
	651
	652	/* only create dss helper devices if dss is enabled in the .dts */
	653
	654	node = omapdss_find_dss_of_node();
	655	if (!node)
	656	return 0;
	657
	658	if (!of_device_is_available(node))
	659	return 0;
	660
	661	ver = omap_display_get_version();
	662
	663	if (ver == OMAPDSS_VER_UNKNOWN) {
	664	pr_err("DSS not supported on this SoC\n");
	665	return -ENODEV;
	666	}
	667
	668	pdev = of_find_device_by_node(node);
	669
	670	if (!pdev) {
	671	pr_err("Unable to find DSS platform device\n");
	672	return -ENODEV;
	673	}
	674
	675	r = of_platform_populate(node, NULL, NULL, &pdev->dev);
	676	if (r) {
	677	pr_err("Unable to populate DSS submodule devices\n");
	678	return r;
	679	}
	680
	681	board_data.version = ver;
	682
	683	omap_display_device.dev.platform_data = &board_data;
	684
	685	r = platform_device_register(&omap_display_device);
	686	if (r < 0) {
	687	pr_err("Unable to register omapdss device\n");
	688	return r;
	689	}
	690
	691	/* create DRM device */
	692	r = omap_init_drm();
	693	if (r < 0) {
	694	pr_err("Unable to register omapdrm device\n");
	695	return r;
	696	}
	697
	698	/* create vrfb device */
	699	r = omap_init_vrfb();
	700	if (r < 0) {
	701	pr_err("Unable to register omapvrfb device\n");
	702	return r;
	703	}
	704
	705	/* create FB device */
	706	r = omap_init_fb();
	707	if (r < 0) {
	708	pr_err("Unable to register omapfb device\n");
	709	return r;
	710	}
	711
	712	/* create V4L2 display device */
713	r = omap_init_vout();
714	if (r < 0) {
715	pr_err("Unable to register omap_vout device\n");
716	return r;
717	}
718
719	return 0;
720	}